CN104810369B - Semiconductor structure and layout structure of memory element - Google Patents
Semiconductor structure and layout structure of memory element Download PDFInfo
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- CN104810369B CN104810369B CN201410031716.8A CN201410031716A CN104810369B CN 104810369 B CN104810369 B CN 104810369B CN 201410031716 A CN201410031716 A CN 201410031716A CN 104810369 B CN104810369 B CN 104810369B
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- 238000004519 manufacturing process Methods 0.000 description 9
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Abstract
本发明公开一种存储器元件的半导体结构及布局结构，其布局结构包含有多个第一栅极图案、多个第一接触垫图案、多个虚置图案、多个第二接触垫图案、以及多个第二栅极图案。该等第一接触垫图案彼此平行且与该等第一栅极图案电性连接。该等虚置图案与该等第一接触垫图案交错排列，而该等第二接触垫图案则分别设置于一该第一接触垫图案与一该虚置图案之间。另外，该等第二栅极图案是电性连接至该等第二接触垫图案。
The present invention discloses a semiconductor structure and layout structure of a memory element, wherein the layout structure includes a plurality of first gate patterns, a plurality of first contact pad patterns, a plurality of dummy patterns, a plurality of second contact pad patterns, and a plurality of second gate patterns. The first contact pad patterns are parallel to each other and electrically connected to the first gate patterns. The dummy patterns are arranged alternately with the first contact pad patterns, and the second contact pad patterns are respectively arranged between one of the first contact pad patterns and one of the dummy patterns. In addition, the second gate patterns are electrically connected to the second contact pad patterns.
Description
Technical field
Semiconductor structure and layout structure of the present invention about a kind of memory component, espespecially a kind of flash memories member
The semiconductor structure and layout structure of part.
Background technique
Semiconductor memery device is commonly used in various electronic devices, and for example, non-volatility semiconductor is deposited
Reservoir (non-volatile semiconductor memory) is usually used in mobile phone, digital camera, personal digital assistant, movement
In computing device, non-moving computing device and other devices.In non-volatile (non-volatile) semiconductor memory, electricity
Erasable programmable read-only memory (Electrically Erasable Programmable Read Only Memory,
EEPROM) and flash memories (flash memory) are most widely used non-volatile semiconductor memory.
And with the progress of semiconductor fabrication process and the diminution of element, semiconductor memery device faces more
Challenge.For example, existing flash memory cell born of the same parents include a storage grid (memory gate) and one with the storage
The selection gate (select gate) of gate adjacent.With the contracting of element and manufacture craft tolerance (process window)
Small, misalignment (misalignment) problem between selection gate and contact plunger influences the performance of element increasingly, or even leads
Cause the failure of flash memory cells.In addition, there is an inclination when selection gate is the selection gate of a clearance wall kenel
And uneven surface, therefore be set in selection gate and must be not easy with the contact plunger of selection gate material contact and this
One surface certainly contacts, and has more caused reliability (reliability) problem.
Summary of the invention
Therefore, one of present invention is designed to provide the semiconductor structure and layout structure of a kind of memory component, with
The problems such as overcoming the alignment and reliability between contact plunger and selection gate.
According to the present invention, a kind of layout structure of memory component is provided, the layout structure of the memory component includes
Multiple first grid patterns, multiple first engagement pads (landing pad) pattern, multiple dummy patterns, multiple second engagement pads
Pattern and multiple second grid patterns.The equal first engagement pad pattern is parallel to each other and waits first grids pattern electrical with this
Connection.The grade dummy patterns are staggered with grade the first engagement pad pattern, and grade the second engagement pad pattern is then respectively set
Between the first engagement pad pattern and the dummy pattern.In addition, the grade second grids pattern is electrically connected to the grade
Two engagement pad patterns.
According to the present invention, a kind of semiconductor structure of memory component is separately provided, the semiconductor structure include a substrate,
Multiple memory components being set in the substrate, multiple are set to multiple storage grid engagement pads being set in the substrate
Nominal grid, multiple selection gate engagement pads being set in the substrate in the substrate and multiple it is respectively formed in this etc.
Selection gate contact plunger in selection gate engagement pad.The grade memory components separately include a storage grid and a selection grid
Pole, the storage grids engagement pad such as this are electrically connected to the storage grids such as this, and the selection gates engagement pad such as this is then electrically connected to this
Etc. selection gates.The grade nominal grids with this etc. storage grids engagement pad be to be staggered, and the selection gates such as this engagement pad is then
It is set between the storage grid engagement pad and the nominal grid.In addition, the selection gates engagement pad such as this includes a recess
Portion, the bottom of the recessed portion has a flat surfaces, and the selection gates contact plunger such as this is to contact the flat surfaces.
The semiconductor structure and layout structure of provided memory component according to the present invention, utilizes setting for nominal grid
It sets, increases the manufacture craft tolerance of selection gate engagement pad, and selection gate engagement pad is made to include one with flat table
The recessed portion in face, therefore selection gate contact plunger can contact the flat surfaces and improve the reliability of memory component.
Detailed description of the invention
Fig. 1 is the schematic diagram of a preferred embodiment of the layout structure of a memory component provided by the present invention.
Fig. 2 is the diagrammatic cross-section of the semiconductor structure of A-A ' tangent line memory component obtained along Fig. 1.
Fig. 3 is the diagrammatic cross-section of the semiconductor structure of B-B ' tangent line memory component obtained along Fig. 1.
Main element symbol description
Specific embodiment
Fig. 1-3 is please referred to, wherein Fig. 1 is a preferably implementation of the layout structure of memory component one of provided by the present invention
Schematic diagram, Fig. 2 of example are the diagrammatic cross-section in Fig. 1 along the semiconductor structure of A-A ' tangent line memory component obtained, Fig. 3
For in Fig. 1 along the diagrammatic cross-section of the semiconductor structure of B-B ' tangent line memory component obtained.
Referring initially to Fig. 1.A preferred embodiment provided by according to the present invention, the layout structure 10 of a memory component
Storage grid (memory gate) comprising multiple first grid pattern 100a, 100b, as memory component.It is prior
It is that first grid pattern 100a, 100b of this preferred embodiment are as shown in Figure 1 in pairs.That is, two are put down each other
Capable first grid pattern 100a, 100b forms a first grid pattern to (pair) 100, and each first grid pattern pair
There is a distance D1 between first grid pattern 100a, 100b in 100.The layout structure 10 of memory component is also comprising multiple
First engagement pad pattern 110, as the storage grid engagement pad of memory component, the first engagement pad pattern 110 it is parallel to each other and
It is electrically connected with first grid pattern 100a, 100b.In detail, each gate pattern is to the first grid pattern in 100
100a and 100b as shown in Figure 1, all with one first engagement pad pattern, 110 entity and electric connection.In addition, the first engagement pad figure
Case 110 has a width W1, and this width W1 is less than first grid pattern connected to it to the first grid pattern in 100
Space D 1 between 100a, 100b.
Please continue to refer to Fig. 1.The layout structure 10 of memory component provided by this preferred embodiment is also comprising multiple the
Two gate patterns 200, multiple second engagement pad patterns 210 and multiple dummy patterns 300.Second grid pattern 200 is as storage
The selection gate (select gate) of device element, the second engagement pad pattern are then used as the selection gate engagement pad of memory component,
And it second grid pattern 200 and 210 entity of the second engagement pad pattern and is electrically connected.Second grid pattern 200 has a width
WS, the second engagement pad pattern 210 has a width W2, and the width W2 of the second engagement pad pattern 210 is greater than second grid pattern
200 width WS.In addition, the first engagement pad pattern 110 with a length L1, the second engagement pad pattern 210 have a length L2,
And dummy pattern 300 has a length L3.In the preferred embodiment, the length L1 of the first engagement pad pattern 110 is greater than second
The length L2 of engagement pad pattern 210, and the length L2 of the second engagement pad pattern 210 is greater than the length L3 of dummy pattern 300.
Please continue to refer to Fig. 1.Second engagement pad pattern 210 corresponds to one first engagement pad pattern 110 with dummy pattern 300
Setting, it is often more important that, dummy pattern 300 is to be staggered with the first engagement pad 110, and the second engagement pad pattern 210 is then set
It is placed between the first engagement pad pattern 110 and dummy pattern 300.In addition, dummy pattern 300 and the first engagement pad pattern 110,
One gate pattern 100a/100b, the second engagement pad pattern 210 and second grid pattern 200 are electrically isolated.
Please referring still to Fig. 1.The layout structure 10 of memory component provided by this preferred embodiment is also comprising multiple the
One doped region pattern 400 and multiple second doped region patterns 410.First doped region pattern 400 is set to each first grid pole figure
Case is within 100, that is, is set between first grid pattern 100a and 100b.And the second doped region pattern 410 is then arranged
Between second grid pattern 200.In the preferred embodiment, source electrode of the first doped region pattern 400 as memory component
Region；And the second doped region pattern 410 is then as the drain region of memory component.In addition, provided by this preferred embodiment
The layout structure 10 of memory component also comprising multiple first contact plunger patterns 120 and multiple second contact plungers 220, divides
It is not formed on the first engagement pad pattern 110 and the second engagement pad pattern 210.As shown in Figure 1, the first contact plunger pattern 120
The position arranged can even in line, and the second contact plunger pattern 220 can also connect in line, but the first contact plunger pattern
The line of 120 line and the second contact plunger pattern 220 is non-overlapping.
The layout structure 10 of the memory component according to provided by this preferred embodiment, due to the first engagement pad pattern 110
Width W1 be less than first grid pattern to the distance between two first grid patterns 100a, 100b in 100 D1, therefore can be considered
A neck is formed in first grid pattern is to 100, and this neck just can accommodate nominal grid 300 and width is greater than
Second engagement pad pattern 210 of second grid pattern 200.Therefore this preferred embodiment can not change first grid pattern 100a/
Under the premise of the width WS of the width of 100b and space D 1 and second grid pattern 200, the width of the second engagement pad pattern 210 is improved
W2 is spent, the alignment issues between the second contact plunger pattern 220 and the second engagement pad pattern 210 is effectively improved, therefore can be promoted
Manufacture craft tolerance.
Fig. 2 and Fig. 3 are please referred to, Fig. 2 and Fig. 3 is the preferable of the semiconductor structure of a memory component provided by the present invention
The diagrammatic cross-section of embodiment, and Fig. 2 is also the diagrammatic cross-section obtained in Fig. 1 along A-A ' tangent line, and 3 figures are in Fig. 1 along B-
The diagrammatic cross-section that B ' tangent line obtains.That is, the semiconductor structure of memory component provided by this preferred embodiment
Top view can correspond to layout structure 10 shown in FIG. 1, therefore can be simultaneously refering to the 1st~3 figure.As shown in Figure 2 and Figure 3, this is preferable
The semiconductor structure 20 of memory component provided by embodiment includes a substrate 102, and is provided in substrate 102 multiple
Isolation structure 104.The semiconductor structure 20 of memory component includes multiple memory components 30, is set in the substrate 102,
And the grade memory components 30 have separately included a storage grid 100a or 100b and a selection gate 200.As shown in Fig. 2, choosing
Select grid 200 respectively the selection gate 200 adjacent and adjacent with storage grid a 100a or 100b and storage grid 100a or
100b is electrically isolated from one another by an insulating layer 106.Memory component 30 also includes source region 400 and a drain region
410, as shown in Fig. 2, source region 400 and selection gate 200 are respectively arranged at the opposite sides of storage grid 100a/100b,
And drain region 410 and storage grid 100a/100b are respectively arranged at the opposite sides of selection gate 200.
Next Fig. 1 and Fig. 3 are please referred to.The semiconductor structure 20 of memory component provided by this preferred embodiment also wraps
Containing multiple storage grid engagement pads 110, multiple selection gate engagement pads 210 and multiple nominal grids 300, it is set to substrate 102
Isolation structure 104 on.As shown in Figure 1, storage grid 100a/100b be in pairs, and each storage grid to 100 electrically
It is connected to storage grid engagement pad 110.Nominal grid 300 is to be staggered, and selection gate connects with storage grid engagement pad 110
Touch pad 210 is then set between a storage grid engagement pad 110 and a nominal grid 300, and is electrically connected to selection gate
200.The semiconductor structure 20 of memory component provided by this preferred embodiment also includes multiple selection gate contact plungers 220
And multiple storage grid contact plungers 120, selection gate contact plunger 220 are respectively formed in selection gate engagement pad 210,
And it is electrically connected respectively with selection gate engagement pad 210.Similarly storage grid contact plunger 120 is respectively formed in storage grid and connects
In touch pad 110, and it is electrically connected respectively with storage grid engagement pad 110.
Please refer to Fig. 2 and Fig. 3.In the preferred embodiment, storage grid engagement pad 110, selection gate engagement pad
210, nominal grid 300, storage grid 100a/100b and selection gate 200 may include identical material, preferably polysilicon.
In addition, storage grid engagement pad 110, storage grid 100a/100b and nominal grid 300 may include identical material, and simultaneously
It is formed；And selection gate engagement pad 210 and selection gate 200 include identical material, and are to form storage grid contact
It is made just now after pad 110, storage grid 100a/100b and nominal grid 300.The semiconductor structure 20 of memory component also wraps
Containing multiple insulating layers 106, to electrically isolate storage grid engagement pad 110, selection gate engagement pad 210 and nominal grid
300.Even more noteworthy, the semiconductor structure 20 of the memory component according to provided by this preferred embodiment, selection gate
200 include a gap wall-shaped selection gate, has an inclined-plane as shown in Figure 2.Forming this gap wall-shaped selectivity grid
When, storage grid is etched to the polysilicon layer of 100 two sides, simultaneously in storage grid to 100 by an etch-back manufacture craft
Two sides form gap wall-shaped selection gate 200.Importantly, in the preferred embodiment, due to storage grid engagement pad 110
The selection gate for being staggered, therefore being located between storage grid engagement pad 110 and nominal grid 300 with nominal grid 300
Engagement pad 210 is influenced in etch-back manufacture craft by nominal grid 300, so that etch-back manufacture craft can not be effective
Ground etches this polysilicon layer, therefore selection gate engagement pad 210 provided by this preferred embodiment has a recessed portion 210r, and
The bottom of this recessed portion 210r has a flat surfaces 212.Briefly, this preferred embodiment is utilizing etch-back manufacture craft
When forming gap wall-shaped selection gate 200, while between storage grid engagement pad 110 and nominal grid 300, automatically form
Selection gate engagement pad 210 with flat surfaces 212.Therefore, when being subsequently formed selection gate contact plunger 220, selection
Gate contact plug 220 can contact this flat surfaces 212, complete the electric connection of memory component.
The semiconductor structure 20 of the memory component according to provided by this preferred embodiment, due to selection gate engagement pad
210 have a flat surfaces 212, therefore selection gate contact plunger 220 contacts this flat surfaces 212, and non-contact just like same
The inclined-plane of gap wall-shaped selection gate 200, therefore can ensure that between selection gate engagement pad 210 and selection gate contact plunger 220
Electric connection success and effectively complete construction, also promote the reliability of memory component 30.
In conclusion the semiconductor structure and layout structure of memory component provided by according to the present invention, reduction storage
The width of gate contact pad makes it be less than the spacing between internal two storage grids of storage grid, and wins increase selection
Gate contact pads width, and adds the space of nominal grid.Since the width of selection gate engagement pad is promoted, therefore it can reduce choosing
The alignment issues between gate contact pad and selection gate contact plunger are selected, and improve the manufacture craft tolerance of memory component
Degree.And due to the setting of nominal grid, it can automatically form while forming gap wall-shaped selection gate with flat surfaces
Selection gate engagement pad, therefore selection gate contact plunger can contact the flat bottom, also promote the reliability of memory component.
The foregoing is merely presently preferred embodiments of the present invention, all equivalent changes done according to the claims in the present invention with repair
Decorations, are all covered by the present invention.
Claims (17)
1. a kind of layout structure of memory component, includes:
Multiple first grid patterns；
Multiple first engagement pad (landing pad) patterns, multiple first engagement pad pattern are parallel to each other and with multiple
One gate pattern is electrically connected；
Multiple dummy patterns, multiple dummy pattern are staggered with multiple first engagement pad pattern；
Multiple second engagement pad patterns are respectively arranged between the first grid pattern and the dummy pattern；And
Multiple second grid patterns are electrically connected to multiple second engagement pad pattern,
Wherein the length of multiple dummy pattern is less than the length and multiple second engagement pad of multiple first engagement pad pattern
The length of pattern.
2. the layout structure of memory component as described in claim 1, wherein multiple dummy pattern connects with multiple first
Touch pad pattern, multiple first grid pattern, multiple second engagement pad pattern and multiple second grid pattern are electrically isolated.
3. the layout structure of memory component as described in claim 1, wherein multiple first grid pattern is in pairs.
4. the layout structure of memory component as claimed in claim 3, wherein the first engagement pad pattern and one this in pairs
First grid pattern be electrically connected.
5. the layout structure of memory component as claimed in claim 4, wherein the width of the first engagement pad pattern, which is less than, is somebody's turn to do
The distance between pairs of first grid pattern.
6. the layout structure of memory component as claimed in claim 5, wherein multiple dummy pattern connects with multiple second
The first engagement pad pattern is corresponding with 1 respectively for touch pad pattern.
7. the layout structure of memory component as claimed in claim 3 includes also multiple first doped region patterns, is respectively set
Between the pairs of first grid pattern.
8. the layout structure of memory component as described in claim 1 includes also multiple second doped region patterns, is respectively set
Between multiple second grid pattern.
9. the layout structure of memory component as described in claim 1, wherein the width of multiple second engagement pad pattern is big
In the width of multiple second grid pattern.
10. the layout structure of memory component as described in claim 1, also comprising multiple first contact plunger patterns with it is multiple
Second contact plunger is respectively formed on multiple first engagement pad pattern and multiple second engagement pad pattern.
11. a kind of semiconductor structure of memory component, includes:
Substrate；
Multiple memory components are set in the substrate, and multiple memory component has separately included storage grid and selection grid
Pole；
Multiple storage grid engagement pads, are set in the substrate, and are electrically connected to multiple storage grid；
Multiple nominal grids are set in the substrate, and multiple nominal grid is staggered with multiple storage grid engagement pad；
Multiple selection gate engagement pads are set between the storage grid engagement pad and the nominal grid, and are electrically connected
To multiple selection gate；And
Multiple selection gate contact plungers are respectively formed in multiple selection gate engagement pad, wherein
Multiple selection gate engagement pad includes recessed portion, and the bottom of the recessed portion includes a flat surfaces, and multiple selection
Gate contact plug contacts the flat surfaces.
12. the semiconductor structure of the memory component such as claim 11, wherein multiple selection gate is deposited with multiple respectively
It stores up the adjacent and adjacent multiple selection gate of grid and multiple storage grid is electrically isolated from one another.
13. the semiconductor structure of the memory component such as claim 11, wherein multiple selection gate includes a gap wall-shaped
Selection gate, and separately include an inclined-plane.
14. the semiconductor structure of the memory component such as claim 11, wherein multiple memory component also includes one respectively
Source region and a drain region, the source region and the selection gate are respectively arranged at the opposite sides of the storage grid, should
Drain region and the storage grid are respectively arranged at the opposite sides of the selection gate.
15. the semiconductor structure of the memory component such as claim 11, wherein multiple storage grid engagement pad, multiple choosing
Selecting gate contact pad, multiple nominal grid, multiple storage grid and multiple selection gate includes identical material.
16. the semiconductor structure of the memory component such as claim 11 includes also multiple insulating layers, electrically isolates multiple deposit
Store up gate contact pad, multiple selection gate engagement pad and multiple nominal grid.
17. as claim 11 memory component semiconductor structure, also include multiple storage grid contact plungers, respectively with
Multiple storage grid engagement pad is electrically connected.
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| CN115172453A (en) * | 2016-08-08 | 2022-10-11 | 联华电子股份有限公司 | Semiconductor device with a plurality of transistors |
| CN107910332A (en) * | 2017-11-09 | 2018-04-13 | 上海华力微电子有限公司 | A kind of gate connection structures of memory and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1637949A (en) * | 2004-01-06 | 2005-07-13 | 阿克特兰斯系统公司 | Nand flash memory with enhanced program and erase performance, and fabrication process |
| CN101308823A (en) * | 2007-05-17 | 2008-11-19 | 力晶半导体股份有限公司 | Layout structure of nonvolatile memory and manufacturing method thereof |
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| JP4599048B2 (en) * | 2003-10-02 | 2010-12-15 | 川崎マイクロエレクトロニクス株式会社 | Semiconductor integrated circuit layout structure, semiconductor integrated circuit layout method, and photomask |
| JP4758625B2 (en) * | 2004-08-09 | 2011-08-31 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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| CN1637949A (en) * | 2004-01-06 | 2005-07-13 | 阿克特兰斯系统公司 | Nand flash memory with enhanced program and erase performance, and fabrication process |
| CN101308823A (en) * | 2007-05-17 | 2008-11-19 | 力晶半导体股份有限公司 | Layout structure of nonvolatile memory and manufacturing method thereof |
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