CN104810380B - Wafer level semiconductor device and preparation method thereof - Google Patents

Abstract

The invention provides a wafer-level semiconductor device and a preparation method thereof. The wafer-level semiconductor device includes a wafer-level substrate; a plurality of series groups formed on the surface of the substrate and arranged in parallel, each series group includes a plurality of parallel groups arranged in series, and each parallel group includes a plurality of parallel groups arranged unit cells, each of which is an independent functional unit formed by processing a semiconductor layer directly grown on the substrate surface; and a wire electrically connected to at least two selected parallel connections in each series group Between the groups, it is used to make the conduction voltage of all series groups basically the same. The device of the invention has simple structure, simple and convenient manufacturing process, low cost and high yield, and is suitable for large-scale manufacturing and application.

Description

Wafer-level semiconductor device and manufacturing method thereof

technical field

The invention relates to a semiconductor device and its preparation process, in particular to a high-power, large-area wafer-level semiconductor device and its preparation method. The wafer-level semiconductor device is a plurality of unit cells formed on a wafer. Devices connected in series and parallel can be used without cutting and separating.

Background technique

In recent years, people have put forward higher and higher requirements for the power of LED lighting. In order to obtain a high-power light source, the current industry usually integrates multiple small-sized LED chips made by traditional processes into one device. As one of the typical solutions, referring to CN103137643A, CN103107250A, etc., \personnel fix and assemble a plurality of small-sized LED chips on a substrate by bonding, etc., and use a certain circuit form to electrically connect the plurality of LED chips. Sexual connection, thus forming a high-power LED device. It is true that high-power LED devices can be obtained through this type of process, but the necessary operations such as chip packaging, system integration, and installation procedures are very complicated, which makes the total manufacturing cost of the device rise sharply and limits the high-power LED devices. promotional application.

Increasing the chip area of LED devices is the most direct and easiest way to realize high-power LEDs. However, in reality, almost no one produces high-power LED devices in this way. The reason is that the yield rate of products is too low. For semiconductor devices, the yield rate of the chip has a great relationship with the chip area, which can usually be expressed by formula (1):

Among them, P1 and _P2 are the yield rate _of the LED chip with the area _of A1 and A2 respectively, assuming that the yield rate of the LED chip with the area of _1mm2 is ⁹⁹ %, then we can calculate the yield rate of the device with the increase of the chip area rate dropped sharply. As shown in Figure 1, when the chip area increases to 500mm ² , the yield rate has dropped to <1%, and if the chip area increases to 1000mm ² , the yield rate is only 0.34/10,000, which cannot be used to produce large-area, large-scale Power LED device products.

Therefore, it is necessary to carefully study and design the layout and interconnection of LED chips, so that it is expected to produce large-area, high-power semiconductor device chips, or even high-power devices for wafer-level chips, reducing packaging and application costs.

Contents of the invention

In view of the shortcomings of the prior art, one of the objectives of the present invention is to provide a wafer-level semiconductor device, which has the characteristics of simple and convenient manufacturing process, low cost, and high yield rate.

Another object of the present invention is to provide a process for preparing the aforementioned wafer-level semiconductor device.

In order to realize the aforementioned object of the invention, the present invention adopts the following technical solutions:

A wafer-level semiconductor device, comprising:

Wafer-level substrates;

A plurality of series groups formed on the surface of the substrate and arranged in parallel, each series group includes a plurality of parallel groups arranged in series, and each parallel group includes a plurality of unit cells arranged in parallel, wherein each unit cell is directly grown An independent functional unit formed by processing the semiconductor layer on the surface of the substrate; and,

Conductive wires, which are electrically connected at least between a selected parallel group in each series group and an electrode of the semiconductor device and/or between two selected parallel groups, so as to conduct conduction of all series groups The voltage is basically the same.

The aforementioned unit cell refers to a device unit with independent and complete functions, and the conductive semiconductor layers of any two unit cells are separated, so that any unit cell is electrically independent; through metal interconnection, multiple unit cells are electrically connected to form Larger devices to achieve higher device performance, such as: power increase, etc.

As a typical example, the aforementioned unit cells may be light-emitting elements such as semiconductor lasers and LEDs, and electronic components such as diodes.

Further, in at least one series group, the two selected parallel groups are non-adjacent.

As one of the typical embodiments, all the unit cells formed on the surface of the substrate include a plurality of normal units and a plurality of redundant units, and the plurality of normal units are arranged as a plurality of multilevel unit groups arranged in parallel, Any multi-level unit group includes a plurality of first parallel groups arranged in series, and the selected M first parallel groups in any multi-level unit group are also connected in series with N second parallel groups to form a series group,

Wherein, any first parallel group includes a plurality of normal cells arranged in parallel, and any second parallel group includes a plurality of redundant cells arranged in parallel, M is a positive integer, and N is 0 or a positive integer.

Preferably, at least one matching resistor is further provided in at least one series group.

As one of typical implementations, two or more first parallel groups selected from at least one multi-level unit group are directly connected in series with at least one second parallel group through wires to form a series group.

Further, the wafer-level semiconductor device may further include a cooling structure that is hermetically connected to the substrate, and a selected area of the second surface of the substrate is exposed to the cooling medium circulation cavity in the cooling structure, and the selected area At least corresponding to the area of the first surface of the substrate where the plurality of unit cells are distributed.

Further, the wafer-level semiconductor device may further include a cooling structure that is hermetically connected to the substrate, and the plurality of unit cells are all exposed to cooling medium circulation cavities in the cooling structure.

Further, the diameter of the wafer-level substrate is more than 2 inches.

Preferably, the conduction voltage of the series group is 110V, 220V or 380V.

Further, the wafer-level semiconductor devices include semiconductor lasers, LEDs or diodes.

A method for preparing a wafer-level semiconductor device, comprising:

A plurality of series groups arranged in parallel are formed on the surface of the wafer-level substrate, wherein each series group includes a plurality of parallel groups arranged in series, each parallel group includes a plurality of unit cells arranged in parallel, and each unit cell is An independent functional unit formed by processing a semiconductor layer directly grown on the surface of the substrate;

And at least one selected parallel group in each series group is electrically connected with an electrode of the semiconductor device and/or two selected parallel groups in each series group are electrically connected by a wire, so that all series groups The conduction voltage of the group is basically the same.

As one of typical embodiments, the preparation method may include the following steps:

(1) providing a wafer-level substrate with a semiconductor layer grown on the first surface;

(2) processing the semiconductor layer to form a plurality of unit cells;

(3) Select some of the multiple units as normal units, and the rest as redundant units, and divide all normal units into two or more multi-level unit groups and set them up in parallel, and any multi-level unit group includes series the two or more first parallel groups of the arrangement, and,

Selecting M first parallel groups and N second parallel groups in any multi-level unit group in series to form a series group, so that the conduction voltages of the two or more series groups are basically the same,

Wherein, any first parallel group includes a plurality of normal units arranged in parallel, and any second parallel group includes a plurality of redundant units arranged in parallel, M is a positive integer, and N is 0 or a positive integer.

Further, the method may include: connecting at least two selected first parallel groups in any multi-level unit group in series with at least one second parallel group directly through wires to form a series group.

Preferably, the method may further include: setting at least one matching resistor in at least one series group.

Further, the method may further include: sealingly connecting the substrate with the cooling structure, and exposing a selected area of the second surface of the substrate to the cooling medium circulation cavity in the cooling structure, wherein the selected area is at least Corresponding to the area on the first surface of the substrate where the plurality of unit cells are distributed.

Further, the method may further include: sealingly connecting the substrate with the cooling structure, and exposing the plurality of unit cells to the cooling medium circulation cavity in the cooling structure.

Compared with the prior art, the present invention has at least the following advantages: the wafer-level semiconductor device has simple structure, simple and convenient manufacturing process, low cost, high yield rate, and is suitable for large-scale manufacturing and application.

Description of drawings

Figure 1 is a graph showing the relationship between LED chip yield and chip area;

Figure 2 is a probability distribution diagram of series LED short-circuit failure series;

Fig. 3 is a structural schematic diagram of an existing integrated high-power LED device;

4a-4b are respectively a top view and a cross-sectional view of a wafer-level LED device in a preferred embodiment of the present invention;

Fig. 5a is a working circuit diagram of a wafer-level LED device in a preferred embodiment of the present invention;

Fig. 5b is a working circuit diagram of another wafer-level LED device in a preferred embodiment of the present invention;

6 is a working circuit diagram of a wafer-level LED device in another preferred embodiment of the present invention;

Among them: 1-substrate, 2-unit cell, 10-transfer substrate, 20-LED chip, 21-substrate, 22-epitaxy layer, 23-working electrode, 30-bonding layer, 4-wire, a- First parallel group, a'-first parallel group, b-series group, b'-series group.

detailed description

Taking LED devices as an example, analyzing from the principle, there are two main failure modes in LED devices, namely: short-circuit failure and open-circuit failure. In order to obtain large-area, high-power LED chips, a multi-level series connection or multiple parallel connection methods can be used.

For the series mode, if one or more stages of short-circuit failure occurs, other LEDs that have not failed can still work, so they have the ability to resist short-circuit failure. However, if there is an open circuit failure in any stage, then the entire LED will not work and is therefore not immune to open circuit failure.

Assuming that in n-level series LEDs, the probability of a certain level of short-circuit is P _s , then the probability of occurrence of k-level short-circuit P _sk can be expressed as follows:

Taking an LED unit cell with an area of 1mm2 in each stage and ²⁴ LED chips connected in series as an example, if the probability of a short circuit in a certain stage is P _s = 2%, then the probability distribution of the k-stage failure can be calculated, as shown in Figure 2 Show.

From Figure 2, it can be seen that the number k of short-circuit series is concentrated below level 5, and the total probability of short-circuit below level 5 can be summed up to more than 98%. From a product point of view, even if there is a level 5 short circuit, the LEDs in series can still work normally. Compared with the level 0 short circuit LED, the maximum power is only reduced by about 20%, and the efficiency is slightly reduced, so the level 5 short circuit device is reduced. It can still be put on the market after a certain quality level (at present, most LED products adopt a similar product classification sales strategy), which means that the total product yield can reach 98%.

In the same way, the failure probability of open circuit can be analyzed. Still taking the 24-level LED in series as an example, if the failure probability of a certain level is P _o = 2%, then the device can only work when all the levels are broken, and the yield rate is only:

Using the method of probability analysis, it is also possible to analyze the yield rate of multiple parallel LEDs. Taking an LED with 24 units connected in parallel as an example, if the short-circuit failure probability (P _s ) and open-circuit failure probability (P _o ) of the unit cells are both 2%, it can be analyzed that: 1) only when 0 unit cells are short-circuited , the LED can work normally, and its yield rate is 13.5%; 2) When k unit cells are disconnected, the LED can still work normally, and when k is less than or equal to 5, the total yield rate reaches more than 98%. Therefore, the parallel mode has the ability to resist open circuit failure.

The short-circuit failure and open-circuit failure mentioned above are the main failure modes in LEDs. Therefore, when designing large-area LED chips, especially wafer-level LED chips, it must be able to resist these two failures at the same time.

Correspondingly, the inventor of this case provided a more effective design method, which can be summarized as:

1) An electrically independent LED unit cell is formed in the chip;

2) First connect these unit cells in parallel in groups to prevent open circuit failure;

3) Connect these parallel groups in series into several series groups to prevent short-circuit failure; the number of series series is limited by the actual power supply, because if the number of series series is too large, such as 500 series in series, each level is 3.5 volts, the driving power supply The voltage needs to reach 1750 volts, which is difficult to achieve in reality and the cost is very high, so it is more reasonable to connect the parallel groups in series, and the rated voltage of each series group is close to the 110V, 220V or 380V of the power supply;

4) Connect several series groups in parallel to form a large-area, high-power LED chip.

Furthermore, LED is a current-mode semiconductor device, and its current is an exponential relationship of voltage, which can be expressed as:

In the formula, I _s is the reverse saturation current, and n _ideal is the ideal factor of the device. For n-level LEDs in series, the voltage of each level is close to the n-level average of the total voltage.

According to the analysis in Figure 2, it can be found that some stages of LEDs in series may be short-circuited. Therefore, several series groups connected in series by parallel groups, even if the number of stages in each group is the same, will be short-circuited after actual production. There will also be differences in the number of stages, and there will be a voltage mismatch. For example: there are two LED chips composed of 24-level series groups, the turn-on voltage of each level is 3.5V, one of the short-circuit failure series is 0, and the other short-circuit failure series is 1, then the total turn-on of the two series groups The voltages are 84V and 80.5V respectively. If the current I ₂ of the 80.5V series group connected to a power supply at the same time far exceeds the current I ₁ of the 84V series group, if the influence of the chip parasitic resistance is ignored, it can be calculated as follows:

Wherein, n _ideal =2, kT/e=0.026V, which means that when the second series group works normally, the first series group cannot work. Therefore, the above design rule 4) must be amended, and the methods adopted include:

Several redundant stages are designed in the series group. The difference between the redundant stage in the series group and the parallel stage in the series group is that the electrode of the redundant stage is larger, and the probe can be used to contact it for electrical testing. When the chip is manufactured After the completion, do an electrical test on the series group and its redundant stage, and then connect the redundant stage to the output electrode with a jumper wire according to the principle of consistent opening voltage. In order to more accurately match the turn-on voltage of each series group and its redundant stage, the method of connecting resistors is used to further match according to the set working current.

The "jumper wire" mentioned here should be understood as: a wire used to directly electrically connect two specific demand points in a circuit, especially a series circuit, and there is more than one wire between the two demand points. To constitute the functional elements of the series circuit, for example, more than one aforementioned parallel group.

Furthermore, as an aspect of the present invention, the wafer-level semiconductor device provided by the present invention is directly formed by processing a wafer-level substrate with a semiconductor material layer (also called an "epitaxial layer") grown on the surface, and its main structure It includes a wafer-level substrate, and a plurality of unit cells with predetermined functions formed by processing a semiconductor layer directly grown on the first surface of the substrate.

As another aspect of the present invention, the present invention provides a process for preparing the aforementioned wafer-level semiconductor device, which mainly includes the following process: after growing and forming an epitaxial layer on a wafer-level substrate, it is processed by a process, thereby forming an epitaxial layer on the substrate. Multiple unit cells arranged in an array form are formed.

Obviously, it can be seen that compared with the packaging process of traditional semiconductor chips or integrated semiconductor devices, the wafer-level semiconductor device manufacturing process of the present invention does not at least need to include operations such as thinning, cutting and splitting of the substrate, and does not need to be processed one by one. For packaging small-sized semiconductor chips, there is no need to bond the small-sized semiconductor chips to the transfer substrate one by one before subsequent operations can be performed. The main structure of high-power semiconductor devices can be constructed with only one package, which is easy to operate. The cost is low, and many operating links that may cause damage to epitaxial wafers or unit cells are avoided, and basically no environmental pollution is caused.

Of course, in order to make the wafer-level semiconductor device work normally, it is necessary to arrange working electrodes in each unit cell so that it can be connected to a power source. However, such operation of disposing the working electrode can be realized by technical means known to those skilled in the art, for example, metal evaporation process, micromachining process, etc., and is not limited thereto.

Especially for semiconductor light-emitting devices, if the selected substrate is a transparent wafer such as a sapphire wafer, when the wafer-level semiconductor device of the present invention is used as a flip-chip device, the unthinned substrate can also be used as a light emitting device. window, thereby further improving the luminous efficiency of the device.

Furthermore, in order to make the wafer-level semiconductor device work more stably, the inventor of this case also conducted research and practice on the electrical connection form of each unit cell, and proposed the following circuit layout concept, including:

Some of the unit cells formed on the substrate are defined as normal units, and the rest are defined as redundant units, wherein, the normal unit cells are used as effective working units of the wafer-level semiconductor device during operation, and the redundant units are A considerable part of the system is used as a spare working unit, so the number of normal units should be as large as possible, and far greater than the redundant units;

Then, the plurality of normal unit cells are divided into two or more multi-level unit groups arranged in parallel, any multi-level unit group includes more than two first parallel groups arranged in series,

In addition, the selected M first parallel groups in any multi-level unit group are also connected in series with N second parallel groups to form a series group, so that the conduction voltages of each series group are basically the same (generally speaking, within ± within 10%).

Wherein, any first parallel group includes more than two normal units arranged in parallel, any second parallel group includes more than two redundant units arranged in parallel, M is a positive integer, and N is 0 or a positive integer.

Through the aforementioned circuit design, it is possible to avoid failure of one or several units to cause other normal units to fail to work, and to eliminate the deviation between the performance of one or more normal units in a multi-level unit group and the rest of the normal units. As a result, the turn-on voltage of a certain series working circuit deviates from that of other series working circuits and cannot work normally.

Particularly preferably, M first parallel groups can be selected from any multi-level unit group and directly connected in series with N second parallel groups via wires to form a series group, and the remaining one or more abnormal first parallel groups It is isolated from the working circuit, so that the conduction voltage of each series group is basically the same, ensuring the working stability of the device and improving its working performance. Of course, in some cases, the second parallel group may not be included in a certain series group, and a part of the first parallel group is selected to be directly electrically connected to the working electrode of the semiconductor device through wires.

As another preferred embodiment, at least one matching resistor can also be provided in each of the above-mentioned series groups, the matching resistor can be selected as a resistor with a fixed resistance, and its resistance can be determined according to the relationship between each series group and the remaining series groups. It is determined by the difference of the conduction voltage, of course, it is also preferable to use an adjustable resistor.

Further, in view of the fact that high-power semiconductor devices usually have the problem of large heat generation and limited heat dissipation capacity when they are working, especially for wafer-level semiconductor devices, because of their high power, heat dissipation has become an unavoidable problem. question. The traditional heat dissipation method of semiconductor devices is usually to paste the chip on the heat sink of the tube shell, and then mount it on the surface of the radiator. of heat. Since the total power of wafer-level devices can reach hundreds of watts or even thousands of watts, such heat dissipation measures are far from meeting the requirements, and new heat dissipation methods must be explored.

One of the effective heat dissipation methods is to use a liquid or gaseous cooling medium to directly contact one surface of the wafer-level device to avoid heat sink thermal resistance, soldering thermal resistance, and heat sink thermal resistance to obtain the smallest heat dissipation path and obtain the best heat dissipation performance.

For example, as one of the more preferred embodiments, an active cooling structure that is hermetically connected to the substrate can be used, and a selected area of the second surface of the substrate is exposed to the cooling medium circulation cavity in the cooling structure, and the The selected area at least corresponds to the area on the first surface of the substrate where the multiple unit cells are distributed, and the circulation speed of the cooling medium can be adjusted according to the actual situation, so that the heat generated by each unit cell during operation can be promptly and quickly transferred , without a large amount of accumulation and damage to the device.

For another example, as one of the more preferred implementations for a device with a flip-chip structure, the cooling structure can also be sealed and connected on the substrate, and the multiple unit cells are exposed to the cooling medium circulation cavity in the cooling structure. .

Furthermore, in the present invention, the term "wafer level" means that the diameter of the substrate is more than 2 inches.

Furthermore, the wafer-level semiconductor devices described in the present invention include semiconductor light emitting devices, such as LEDs, and are not limited thereto.

As a more specific embodiment of the present invention, referring to Fig. 3, the preparation method of the wafer-level semiconductor device may also include:

(1) directly processing the semiconductor material layer to form a plurality of unit cells 2 with set functions, and setting some of all the unit cells 2 in the normal area as normal unit cells, and setting the rest as redundant units unit cell

(2) All normal unit cells are divided into two or more multi-level unit groups arranged in parallel, any multi-level unit group includes more than two first parallel groups arranged in series, and any first parallel group includes more than two parallel groups normal unit cell set;

(3) Test the conduction voltage of each multi-level unit group, and select M first parallel groups and N second parallel groups in series from each multi-level unit group to form a series group according to the test results , and make the conduction voltage of each series group in the working state basically the same,

Wherein, the second parallel group includes more than two redundant unit cells arranged in parallel, M is a positive integer, and N is 0 or a positive integer.

In summary, the wafer-level semiconductor device of the present invention has simple structure, simple and convenient manufacturing process, low cost, high yield, and is suitable for large-scale manufacturing and application.

The technical solution of the present invention will be further described in detail below in conjunction with several preferred embodiments and accompanying drawings.

4a-4b, this embodiment relates to a wafer-level LED device, which includes a wafer-level substrate 1 and a plurality of unit cells 2 fixed on the top surface ("first surface") of the substrate 1 , the plurality of unit cell lines are formed by dividing the semiconductor layer directly grown on the first surface of the substrate.

The substrate can be sapphire wafer, SiC wafer, Si wafer, etc., and is not limited thereto.

The semiconductor layer can also be named an epitaxial layer, which can include PN heterojunction, active layer and other components known in the industry to form light-emitting semiconductor devices, so its structure will not be repeated here. .

The LED unit cell is a functional unit that can normally emit light under a certain working voltage, and, referring to the foregoing, each LED unit cell should be electrically isolated from each other.

Further, the aforementioned single cell line includes multiple normal single cells and multiple redundant single cells,

Wherein, the plurality of normal unit cells are divided into several multi-level unit groups arranged in parallel, any multi-level unit group includes several first parallel groups a arranged in series, and the selected M in any multi-level unit group The first parallel groups are also directly connected in series with the N second parallel groups via wires to form a series group b, and the conduction voltages of all the series groups are basically the same.

Here, "substantially consistent" means that the deviation range of the conduction voltage of each series group is within ±10%.

Any of the aforementioned first parallel groups includes more than two normal units arranged in parallel, any second parallel group includes more than two redundant units arranged in parallel, M is a positive integer, and N is 0 or a positive integer.

Referring to the embodiment shown in Fig. 5a-Fig. 5b, wherein N is 0, in each multi-level cell group, select a specific point to be directly electrically connected to a working electrode of the device through a wire, that is, each multi-level Part or all of the first parallel groups in the unit group are connected in series to form a series group, and finally the conduction voltages of all the series groups are basically the same.

Further, referring to Fig. 6, in another preferred embodiment of the present invention, in the circuit structure of the aforementioned embodiment, at least one matching resistor can be connected in each series group, and the matching resistor can be connected according to the aforementioned implementation In the example, the difference degree of conduction voltage of each series group is specifically adjusted, and finally the difference of conduction voltage of each series group is eliminated, so that the obtained wafer-level LED device has the best working stability and luminous efficiency.

In the aforementioned embodiments, in order to realize the electrical connection between the unit cells, various metal evaporation, deposition and micro-nano processing techniques known in the industry can be used to process the working electrode and the electrical connection between the unit cells on each unit cell. line.

Furthermore, in order to enable the obtained wafer-level LED device to have better light extraction efficiency, etc., it is also possible to introduce an emission wavelength conversion structure, a reflective layer, an anti-reflection and anti-reflection structure, and an optical lens into the device for packaging. In the present invention In fact, because the wafer-level LED device can be regarded as a large-scale LED chip, it is not necessary to package each unit cell separately, but only need to package the whole device once, which greatly simplifies the packaging process. In fact, Packaging materials can also be saved.

Of course, in order to make the wafer-level semiconductor device work normally, it is necessary to arrange working electrodes in each unit cell so that it can be connected to a power source. However, such operation of disposing the working electrode can be realized by technical means known to those skilled in the art, for example, metal evaporation process, micromachining process, etc., and is not limited thereto.

In addition, due to the need for heat dissipation of high-power LED devices, cooling structures can also be added to the wafer-level LED devices obtained in the foregoing embodiments, such as currently commonly used heat sinks, microfluidic cooling structures, and the like.

However, in consideration of the low heat dissipation efficiency of conventional cooling structures, in the present invention, the following two cooling structures can also be used, including:

1. For a device in a positive form, the cooling structure can be sealed and connected to the substrate, and the entire selected area of the second surface of the substrate is exposed to the cooling medium circulation cavity in the cooling structure, and the selected area is at least in contact with the The area of the first surface of the substrate where the plurality of unit cells are distributed corresponds to.

2. For flip-chip devices, the cooling structure can also be sealed and connected to the substrate, but at least all the unit cells distributed in the working circuit are exposed to the cooling medium circulation cavity in the cooling structure.

Through the above design, and by adjusting the flow rate and flow rate of water, oil and other media flowing through the cooling medium circulation cavity, efficient heat dissipation can be realized, and the working stability and service life of the device can be further improved.

In addition, other inorganic or organic phase change materials can also be used as the cooling medium, especially fluid phase change materials, such as acetone, alcohol, and the like.

In addition, for the aforementioned wafer-level LED device, its preparation work may include:

(1) processing the semiconductor material layer to form a plurality of unit cells with set functions, and setting some of all the unit cells in the normal region as normal unit cells, and setting the rest as redundant unit cells;

(2) All normal unit cells are divided into two or more multi-level unit groups arranged in parallel, any multi-level unit group includes more than two first parallel groups arranged in series, and any first parallel group includes more than two parallel groups normal unit cell set;

(3) Test the turn-on voltage of each multi-level unit group, and according to the test results, select M first parallel groups from each multi-level unit group to form directly in series with N second parallel groups through wires A series group, and make the conduction voltage of each series group basically the same under the working state,

Wherein, the second parallel group includes more than two redundant unit cells arranged in parallel, M is a positive integer, and N is 0 or a positive integer.

Furthermore, at least one matching resistor can also be set in each series group.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Those of ordinary skill in the art should understand that they can still modify the technical solutions described in the previous solutions, or modify the technical solutions of the present invention. Some of the technical features are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the spirit and scope of the device solution of the present invention.

Claims (16)

1. A wafer-level semiconductor device, characterized in that, comprising: wafer-level substrates, A plurality of series groups formed on the surface of the substrate and arranged in parallel, each series group includes a plurality of parallel groups arranged in series, and each parallel group includes a plurality of unit cells arranged in parallel, wherein each unit cell is directly grown Independent functional units formed by processing the semiconductor layer on the surface of the substrate, and, Conductive wires, which are electrically connected at least between a selected parallel group in each series group and an electrode of the semiconductor device and/or between two selected parallel groups, so as to conduct conduction of all series groups consistent voltage; Wherein, all the unit cells formed on the surface of the substrate include a plurality of normal units and a plurality of redundant units, and the plurality of normal units are arranged as a plurality of multi-level unit groups arranged in parallel, and any multi-level unit The group includes a plurality of first parallel groups arranged in series, and the selected M first parallel groups in any multi-level unit group are also connected in series with N second parallel groups to form a series group, and any first parallel group includes A plurality of normal units arranged in parallel, any second parallel group includes a plurality of redundant units arranged in parallel, M is a positive integer, and N is 0 or a positive integer. 2. The wafer-level semiconductor device according to claim 1, wherein at least one matching resistor is further provided in at least one series group. 3. The wafer-level semiconductor device according to claim 1, wherein at least two first parallel groups selected in at least one multi-level unit group are directly connected in series with at least one second parallel group through wires to form a series group . 4. The wafer-level semiconductor device according to claim 1, further comprising a cooling structure hermetically connected to the substrate, and selected regions of the second surface of the substrate are exposed to cooling in the cooling structure. In the medium circulation chamber, the selected area at least corresponds to the area of the first surface of the substrate where the plurality of unit cells are distributed. 5. The wafer-level semiconductor device according to claim 1, characterized in that it also includes a cooling structure that is hermetically connected to the substrate, and the plurality of unit cells are exposed to the cooling medium circulation cavity in the cooling structure . 6. The wafer-level semiconductor device according to claim 1, wherein the diameter of the wafer-level substrate is more than 2 inches. 7. The wafer-level semiconductor device according to claim 1, wherein the conduction voltage of the series group is 110V, 220V or 380V. 8. The wafer-level semiconductor device according to any one of claims 1-7, characterized in that the wafer-level semiconductor device is selected from semiconductor lasers, LEDs or diodes. 9. A method for preparing a wafer-level semiconductor device, characterized in that it comprises: A plurality of series groups arranged in parallel are formed on the surface of the wafer-level substrate, wherein each series group includes a plurality of parallel groups arranged in series, each parallel group includes a plurality of unit cells arranged in parallel, and each unit cell is An independent functional unit formed by processing a semiconductor layer directly grown on the surface of the substrate, and all the unit cells formed on the surface of the substrate include a plurality of normal units and a plurality of redundant units, and the plurality of normal units are replaced by A plurality of multi-level unit groups arranged in parallel, any multi-level unit group includes a plurality of first parallel groups arranged in series, and the selected M first parallel groups in any multi-level unit group are also combined with N A second parallel group is connected in series to form a series group, any first parallel group includes a plurality of normal units arranged in parallel, any second parallel group includes a plurality of redundant units arranged in parallel, M is a positive integer, N is 0 or a positive integer; And at least one selected parallel group in each series group is electrically connected with an electrode of the semiconductor device and/or two selected parallel groups in each series group are electrically connected by a wire, so that all series groups The conduction voltage of the group is the same. 10. The method for preparing a wafer-level semiconductor device according to claim 9, comprising the steps of: (1) providing a wafer-level substrate with a semiconductor layer grown on the first surface; (2) processing the semiconductor layer to form a plurality of unit cells; (3) Select some of the multiple units as normal units, and the rest as redundant units, and divide all normal units into two or more multi-level unit groups and set them up in parallel, and any multi-level unit group includes series Two or more first parallel groups are provided, and M first parallel groups selected in any multi-level unit group are connected in series with N second parallel groups to form a series group, so that the conduction of the two or more series groups same voltage. 11. The method for manufacturing a wafer-level semiconductor device according to claim 10, characterized in that the method comprises: connecting two or more first parallel groups selected in any multi-level unit group directly through wires and at least one first Two parallel groups are connected in series to form a series group. 12. The method for manufacturing a wafer-level semiconductor device according to claim 9, further comprising: setting at least one matching resistor in at least one series group. 13. The method for manufacturing a wafer-level semiconductor device according to claim 9, further comprising: sealing the substrate with a cooling structure, and exposing a selected area of the second surface of the substrate to the cooling structure. The cooling medium in the cooling structure flows through the cavity, wherein the selected area at least corresponds to the area of the first surface of the substrate where the plurality of unit cells are distributed. 14. The method for preparing a wafer-level semiconductor device according to claim 9, further comprising: sealing the substrate with the cooling structure, and exposing the plurality of unit cells to the cooling structure. The cooling medium flows through the cavity. 15. The method for manufacturing a wafer-level semiconductor device according to claim 9, wherein the conduction voltage of the series series group is 110V, 220V or 380V. 16. The method for manufacturing a wafer-level semiconductor device according to any one of claims 9-15, wherein the wafer-level semiconductor device is selected from semiconductor lasers, LEDs or diodes.