CN104821871B - A kind of 16QAM demodulates synchronous method - Google Patents

Abstract

The present invention provides a 16QAM demodulation and synchronization method, which includes the following steps: (1) adding power detection technology to the Costas loop of traditional QPSK to complete carrier recovery; (2) performing matched filtering on the in-phase and quadrature component signals respectively , to reduce the impact of noise and prepare for bit synchronization; (3) restore the bit timing of the in-phase and quadrature signals through the "sooner or later gate"; (4) set the threshold to perform sampling judgment and 4‑2 level conversion on the two signals Obtain parallel signals; (5) After performing differential decoding and parallel-to-serial conversion on the parallel signals, the original signals are restored. The new carrier synchronization technology introduced in the present invention uses a phase-locked loop to complete carrier recovery. On the basis of the traditional Costas loop, power detection technology is added to ensure the linear output of the phase detector, which improves the tracking accuracy and speed, and has Verified by FPGA hardware.

Description

A 16QAM Demodulation Synchronization Method

technical field

The invention relates to the communication field, in particular to a 16QAM demodulation synchronization method.

Background technique

In the multi-ary keying system, phase keying has advantages in terms of bandwidth and power occupation, that is, the bandwidth occupation is small, and the bit signal-to-noise ratio requirement is low. MPSK (Multiple Phase Shift Keying) and MDPSK (Multiple Differential Phase Shift Keying) have the characteristics of constant envelope and high power efficiency, but they have high side lobes and large spectrum leakage, and are prone to spectrum expansion. With the increase of M, As the distance between adjacent phases gradually decreases, the noise margin decreases accordingly, and the bit error rate is difficult to guarantee. Quadrature Amplitude Modulation (QAM, Quadrature Amplitude Modulation) is a modulation technique that performs amplitude modulation on two quadrature carriers often used in modern communications. It improves the noise tolerance of MPSK when M is large. 16QAM is a representative signal of QAM modulation. It has the advantages of low bit error rate, high transmission rate and high frequency band utilization. It can be applied in communication fields such as HSDPA (High Speed Downlink Packet Access), satellite communication and broadband wireless access. . However, since 16QAM is a non-constant envelope signal, if the traditional QPSK Costas ring is used in the carrier recovery process, it is easy to cause defects such as low precision and slow tracking speed. In addition, although it is simple and easy to develop QAM modem with FPGA tool software with DSP Builder as the core, its stability and portability are poor, and its application is limited. Since 16QAM has a 90° phase ambiguity problem, if the carrier generated during carrier recovery is not of the same frequency and phase as the carrier during modulation, decoding errors will occur.

This patent adopts the quadrature amplitude modulation method to carry out 16QAM modulation, and performs differential encoding on the baseband signal before modulation, and performs differential decoding after bit synchronization, which can overcome the influence of phase ambiguity. In the carrier synchronization module, this patent adds power detection and judgment on the basis of the traditional QPSK COSTAS loop to overcome the influence of the 16QAM non-constant envelope on the phase detector. In the bit timing recovery module, since the clocks of the transmitter and receiver have a certain phase offset and clock offset, resulting in bit errors, the present invention adopts a self-synchronization-based sooner or later gate algorithm, which is suitable for systems with high sampling rates. The clock offset can be roughly estimated, the structure is simple, and it is easy to realize by FPGA hardware. After reasonable planning and careful design, a complete 16QAM modulation and demodulation system including this new demodulation synchronization technology has been realized in a single chip of ALTERA's large-scale FPGA chip, and detailed test verification has been carried out on the development board .

Contents of the invention

In order to solve the problems of the prior art, the present invention improves on the traditional QPSK COSTAS loop, provides a 16QAM demodulation synchronization method, overcomes the influence of the 16QAM non-constant envelope on the phase detector, and improves the system performance .

The present invention provides a kind of 16QAM demodulation synchronization method, comprises the following steps:

1) Carrier synchronization: Assuming that the signal y(n) is received at time n, the signal q(n) is obtained after demodulation, τ is the power detection threshold, and the output of the phase detector is 0 when |q(n)| ² <τ, When |q(n)| ² >τ, the phase detector outputs the phase error value e(n) of the signal point at this moment. After the phase error is smoothed by the loop filter, the NCO is controlled to gradually eliminate the frequency offset and phase offset to achieve carrier synchronization; Select an appropriate power detection threshold τ, convert the 16QAM phase error detection constellation diagram into a QPSK constellation diagram, and then use the COSTAS loop for demodulation; 16QAM enters the phase detector to calculate a(k), b(k) has only one amplitude, so |a(k)|+|b(k)| is a constant, and the error value is smoothed by the loop filter and controls the NCO to gradually eliminate the frequency offset residual and phase error, reaching the carrier Synchronize.

2) performing matched filtering on the in-phase and quadrature component signals respectively;

3) Since the clocks of the transmitter and the receiver will have a certain phase offset and clock offset, as the offset gradually accumulates, it will lead to bit errors and seriously affect the system performance. The invention adopts the sooner or later gate algorithm based on the self-synchronization method, is suitable for a system with a high sampling rate, can roughly estimate the clock offset, has a simple structure and is easy to realize by hardware. For the in-phase and quadrature signals, the bit timing is recovered through the "sooner or later gate", and τ=T/2, the model of the timing error detector can be deduced:

where τ(n) is the sampling clock for compensation, Represents the transition value of the n+1th and nth code elements, Indicates the transition value of the nth and n-1th symbols. From formula (6), the NCO output can be obtained as:

τ(n+1)=τ(n)+γ·e(n);

4) Setting the threshold to perform sampling judgment and 4-2 level conversion on the two signals respectively to obtain parallel signals;

5) After performing differential decoding and parallel-to-serial conversion on the parallel signal, the original signal is restored.

The phase error value e(n) in step 1) is derived as follows, and the received signal r(k) is set as:

r(k)=a(k)cos[(ω _c ±ω _d )kT _s +θ]-b(k)sin[(ω _c ±ω _d )kT _s +θ]+n(t),

where ω _d is the Doppler frequency shift, θ is the carrier phase shift, n(t) is the Gaussian noise at the receiving end, a(k) and b(k) are the in-phase and quadrature components of the baseband symbols, and T _s is Sampling period; the signal is obtained after quadrature mixing and low-pass filtering to remove high-frequency components:

U _I (k)＝a(k)cos[(ω _c ±ω _d -ω _o )kT _s +θ-θ _o ]-b(k)sin[(ω _c ±ω _d -ω _o )kT _s + θ-θ _o ],

U _Q (k)＝b(k)cos[(ω _c ±ω _d -ω _o )kT _s +θ-θ _o ]+a(k)sin[(ω _c ±ω _d -ω _o )kT _s + θ-θ _o ],

The power detection value P(k) is:

P(k) ₌ (U _I (k)) ² +(U _Q (k)) ²

When P(k)<τ, the phase detector error e(k)=0; when P(k)>τ, set Δφ=(ω _c ±ω _d -ω _o )k _s T+θ- _o θ, the U _I and U _Q are sent to the phase detector, where the phase detector is based on the hard decision algorithm, when very young, The phase detector error e(k) can be obtained:

The beneficial effects of the present invention are:

1. Introduced a new type of carrier synchronization technology, using a phase-locked loop to complete carrier recovery, and on the basis of the traditional Costas loop, adding power detection technology to ensure the linear output of the phase detector and improve tracking accuracy and speed.

2. The sooner or later gate algorithm adopted by carrier synchronization is easy to realize by FPGA.

3. It overcomes the adverse effect of 16QAM on the phase detector during demodulation synchronization, and significantly improves the system performance.

Description of drawings

Figure 1 is a 16QAM constellation map.

Figure 2 is a block diagram of 16QAM modulation FPGA implementation.

Fig. 3 is a 16QAM power spectrum diagram.

Figure 4 is a block diagram of 16QAM demodulation FPGA implementation.

Figure 5 is a functional block diagram of the carrier synchronization loop.

Figure 6 is a block diagram of the timing synchronization loop.

Fig. 7(a) is a schematic diagram of a rectangular pulse signal.

Fig. 7(b) is a schematic diagram of matched filter output for bit timing synchronization by using the symmetry of the signal after passing through the matched filter by the early-early gate algorithm.

Figure 8 is a schematic diagram of the overall system FPGA.

Fig. 9 is a modulated signal after differential encoding at the sending end.

Figure 10(a) is a graph of the FPGA output waveform data read by Matlab

Figure 10(b) is the constellation diagram calculated by Matlab reading the FPGA output waveform.

Figure 11 shows the FPGA test results of carrier recovery when the carrier has no frequency offset and the phase offset is 22.5°.

Figure 12 shows the FPGA test results of carrier recovery when the carrier frequency offset is 3KHz and there is no phase offset.

Figure 13 shows the FPGA test results of carrier recovery when the carrier frequency deviation is 3KHz and the phase deviation is 45°.

FIG. 14 is a constellation diagram after carrier synchronization.

Figure 15(a) is an overall view of the bit-synchronous FPGA test results.

Figure 15(b) is a detailed view of the bit-synchronous FPGA test results.

Figure 16(a) is an overall view of the differential decoding and parallel-to-serial conversion FPGA test results.

Figure 16(b) is a detailed view of the differential decoding and parallel-to-serial conversion FPGA test results.

FIG. 17 is a schematic diagram showing a comparison between the theoretical bit error rate and the simulated bit error rate of 16QAM.

Detailed ways

The complete modulation and demodulation process of the 16QAM signal is described below in conjunction with the accompanying drawings, and verified by FPGA hardware.

1. Modulation principle

1. Differential coding

Considering the phase ambiguity problem of 16QAM, the transmission signal adopts partial differential coding, that is, only the first two bits of 4-bit parallel data are differentially coded. Compared with full differential coding, this coding method reduces the number of bits of differential coding, thus reducing error diffusion and having better bit error performance.

In partial differential coding, use the first two bits a ₁ a ₂ to specify the quadrant where the signal is located, and perform differential coding on it; the remaining two bits b ₁ b ₂ are used to specify the configuration of the signal vector in each quadrant, And make the configuration present the rotational symmetry of π/2, as shown in Fig. 1 .

encoding rules:

If [ab] is an absolute code, that is, the transmitted information symbol, and [cd] is a relative code, that is, a code element after differential encoding.

like but like but

Note: Add modulo 2, i is the symbol time.

2. Modulation principle

The 16QAM modulation of the present invention adopts the quadrature amplitude modulation method, which is formed by superimposing two orthogonal four-level amplitude keying signals, and the modulation FPGA realizes the block diagram as shown in FIG. 2 . The input binary sequence is transformed into 4bit parallel data a ₁ a ₂ b ₁ b ₂ after serial-to-parallel conversion, and a ₁ a ₂ is differentially encoded to obtain a′ ₁ a′ ₂ , b ₁ b ₂ remains unchanged, and then a′ ₁ a' ₂ and b ₁ b ₂ perform 2-4 level conversion respectively to generate a four-level PAM signal, and the PAM signal has 2 kinds of amplitudes and 2 kinds of phases. Two PAM signals modulate the in-phase and quadrature carrier respectively, and each modulation has 4 possible outputs, which are combined by an adder to generate a 16QAM signal. The formula is described as:

s(k)＝a(k)cos[ω _c kT _s +θ ₁ ]-b(k)sin[ω _c kT _s +θ ₁ ]

Where w _c is the carrier frequency shift, θ ₁ is the initial phase, a(k) and b(k) are the in-phase and quadrature components of the baseband symbols, and T _s is the sampling period.

The power spectrum of the 16QAM signal is shown in Figure 3. It can be seen that the 16QAM signal power spectrum is relatively compact, the spectrum utilization rate is high, and the information transmission rate is fast, which can meet the needs of satellite communication.

Two, 16QAM signal demodulation synchronization principle

The satellite received signal after Gaussian channel transmission can be expressed as:

r(k)=a(k)cos[(ω _c ±ω _d )kT _s +θ]-b(k)sin[(ω _c ±ω _d )kT _s +θ]+n(t)

In the formula, θ is the carrier phase shift, ω _d is the Doppler frequency shift, and n(t) is the Gaussian noise at the receiving end. The received signal r(t) undergoes carrier recovery and low-pass filtering (LPF) to obtain the in-phase and quadrature component signals, recovers the bit timing and sets the threshold for 4-level judgment, and finally obtains parallel 4-bit data through level conversion, that is, the constellation The inverse of mapping. Corresponding partial differential decoding is performed on the demodulated 4bit data, and the original information data can be recovered through parallel-to-serial conversion. The functional block diagram of demodulation synchronous FPGA is shown in Fig. 4 .

Three, 16QAM signal demodulation process

1. Carrier synchronization ring

Since 16QAM is a non-constant envelope signal, the traditional QPSK COSTAS loop demodulation must set the loop bandwidth very small to ensure the linearity of the phase detector output, and the accuracy is not high, and the tracking speed is slow. The invention adds a power detection and judgment method on the basis of the traditional QPSK COSTAS loop. The method is briefly described as follows: Assume that the signal y(n) is received at time n, and the signal q(n) is obtained after demodulation. Then perform power detection on the signal q(n), that is, select the received signal point that requires phase detection by judging whether q(n) ² >τ (τ is the power detection threshold) holds true. When |q(n)| ² <τ, the output of the phase detector is 0, and when |q(n)| ² >τ, the phase detector outputs the phase error value e(n) of the signal point at this moment. After the phase error is smoothed by the loop filter (LF), the NCO is controlled to gradually eliminate the frequency offset and phase offset to achieve carrier synchronization. By selecting an appropriate power detection threshold τ, the 16QAM phase error detection constellation diagram can be converted into a QPSK constellation diagram, and then demodulated by the classic COSTAS loop, which overcomes the 16QAM non-constant envelope phase detector. influences. The block diagram of its FPGA implementation is shown in Figure 5.

The loop algorithm is derived as follows. Let the received signal r(k) be:

r(k)=a(k)cos[(ω _c ±ω _d )kT _s +θ]-b(k)sin[(ω _c ±ω _d )kT _s +θ]+n(t)

where ω _d is the Doppler frequency shift, θ is the carrier phase shift, n(t) is the Gaussian noise at the receiving end, a(k) and b(k) are the in-phase and quadrature components of the baseband symbols, and T _s is The sampling period. The signal is obtained after quadrature mixing and low-pass filtering to remove high-frequency components:

U _I (k)＝a(k)cos[(ω _c ±ω _d -ω _o )kT _s +θ-θ _o ]-b(k)sin[(ω _c ±ω _d -ω _o )kT _s + θ-θ _o ]

U _Q (k)＝b(k)cos[(ω _c ±ω _d -ω _o )kT _s +θ-θ _o ]+a(k)sin[(ω _c ±ω _d -ω _o )kT _s + θ-θ _o ]

Power detection value P(k):

P(k)＝(U _I (k)) ² +(U _Q (k)) ²

When P(k)<τ, phase detector error e(k)=0; when P(k)>τ, set Δφ=(ω _c ±ω _d -ω _o )kT _s +θ-θ _o , and U _I and U _Q are sent to the phase detector, where the phase detector is based on a hard decision algorithm. when very young, The phase detector error e(k) can be obtained:

After 16QAM is judged by power detection, the a(k) and b(k) calculated by the phase detector have only one amplitude, so |a(k)|+|b(k)| is a constant, and the error value passes through the loop After the filter is smoothed, the NCO is controlled to gradually eliminate the frequency offset residual and phase error to achieve carrier synchronization.

2. Bit timing synchronization ring

Since the clocks of the transmitter and the receiver will have a certain phase offset and clock offset, as the offset gradually accumulates, it will lead to bit errors and seriously affect the system performance. The invention adopts the sooner or later gate algorithm based on the self-synchronization method, is suitable for a system with a high sampling rate, can roughly estimate the clock offset, has a simple structure and is easy to realize by hardware. Its FPGA implementation block diagram is shown in Figure 6.

The sooner or later gate algorithm uses the symmetry of the signal after the matched filter to perform bit timing synchronization, as shown in Figure 7, where Figure 7(a) is a schematic diagram of a rectangular pulse signal, and Figure 7(b) is a schematic diagram of the matched filter output. .

After the signal passes through the matched filter, the best sampling time is t=nT, but due to noise and clock offset, sampling cannot be performed at the time when the signal-to-noise ratio of the symbol is maximum. When the transition values t=nT-τ and t'=nT+τ are equal, the best sampling moment is at the midpoint of the two sampling moments. If late sampling occurs, the difference between adjacent transition values will be detected, and the sampling clock is controlled through a feedback loop, and the same is true for early sampling. Based on this principle, using whether the transition values of two adjacent symbols are equal, plus the information of the amplitude and polarity of the best sampling point, let τ=T/2, the model of the timing error detector can be deduced:

where τ(n) is the sampling clock for compensation, Represents the transition value of the n+1th and nth code elements, Represents the transition value of the nth and n-1th symbols, and the NCO output can be obtained from the above formula:

τ(n+1)=τ(n)+γ·e(n)

Where γ is the step size parameter, τ(n) is the sampling clock for compensation. After multi-level sampling and judgment, the demodulated 4-bit parallel data is finally obtained through level conversion. At this time, differential decoding and parallel-serial conversion are required to restore the original binary code stream.

3. Differential decoding

Corresponding to the differential encoding, let [ab] be the absolute code, that is, the restored information symbol, and [cd] be the relative code, that is, the demodulated symbol.

like but like but

Note: Add modulo 2, i is the symbol time.

4. FPGA verification of the overall system

The FPGA schematic diagram of the overall system is shown in Figure 8. The transmitting module generates a 16QAM modulated signal, which is converted into an analog signal through D/A; the A/D samples the signal generated by the transmitting module through an SMA cable, and the receiving module in the chip performs sampling on the signal. Demodulation, the data interacts with the PC through the JTAG port.

1. Modulation signal generation

Test conditions: sampling rate f _s =100MHz, information rate R _b =100M/16=6.25Mbps, carrier frequency f _c =100M/8=12.5MHz.

The modulated signal after differential encoding at the sending end is shown in FIG. 9 .

Using MATLAB to read the FPGA output waveform captured by QUARTUS-II software is shown in Figure 10(a), and the constellation diagram of the calculated 16QAM modulation signal is shown in Figure 10(b).

It can be seen from the time-domain waveform and constellation diagram that the 16QAM signal modulated in the FPGA meets the requirements. Due to the frequency difference and phase difference between the modulated carrier in the FPGA and the local carrier generated by the MATLAB software demodulation, the square constellation diagram is tilted, and the correct constellation diagram can be obtained through carrier synchronization, and then the signal is demodulated.

2. Carrier recovery test

The FPGA test results of carrier recovery are as follows:

(1) The carrier has no frequency offset, and the phase offset is 22.5°. As shown in Figure 11, the first signal is a phase tracking curve. Since the phase offset is fixed and there is no frequency offset, the tracking value is constant, indicating that the phase offset is successfully tracked. The second and third signals are respectively baseband in-phase and quadrature components after carrier recovery, and both are 4-level signals after recovery.

(2) Carrier frequency offset 3KHz, no phase offset As shown in Figure 12, when there is frequency offset in the carrier, the phase tracking value changes linearly as a linear function to track the frequency change. After carrier recovery, 4-level baseband in-phase and quadrature signals are obtained.

(3) The carrier frequency deviation is 3KHz, and the phase deviation is 45°, as shown in Figure 13.

The constellation diagram after carrier synchronization is shown in Figure 14. It can be seen that the constellation diagram of the 16QAM baseband signal obtained after carrier synchronization has been restored to the level and can be sampled and judged.

3. Bit synchronization test

The test results of bit-synchronous FPGA are shown in Figure 15, where Figure 15(a) is the overall view and Figure 15(b) is the detail view. Test conditions: carrier frequency deviation 3KHz, phase deviation 45°, bit synchronization clock phase deviation 40% (relative to the symbol period).

The first channel signal is the recovered bit synchronous clock, the second and third channels are the baseband in-phase and quadrature component matched-filtered output signals respectively, and the fourth and fifth channels are the in-phase and quadrature components after sampling and judgment respectively. level signal. It can be seen from the figure that the bit synchronization clock recovered based on the sooner or later gate algorithm can accurately sample the peak time after the matched filter, indicating that the bit synchronization circuit in the FPGA works well.

4. Differential decoding, parallel-to-serial conversion test

The test results of differential decoding and parallel-to-serial conversion FPGA are shown in Figure 16, where Figure 16(a) is the overall view and Figure 16(b) is the detail view. Test conditions: carrier frequency deviation 3KHz, phase deviation 45°, bit synchronization clock phase deviation 40% (relative to the symbol period).

Through level conversion, the reverse process of constellation diagram mapping can be obtained to obtain 4-bit parallel data, and then differential decoding and parallel-to-serial conversion are performed, and finally the binary code stream is restored.

The first channel is the 4-bit parallel data after the input binary code stream has been serialized and combined; the second channel is the 4-bit parallel data recovered after carrier recovery, bit synchronization recovery, and level conversion, that is, the reverse process of constellation mapping. There is phase ambiguity in modulation, so the second channel data may be different from the first channel data; the third channel is the output after differential decoding, at this time the data is already the same as the first channel data; the fourth channel is the input binary code stream, The fifth channel is the binary code stream restored after the parallel-to-serial conversion of the differentially decoded data. It can be seen from the figure that the signal is correctly demodulated after a delay of about 500 sampling points.

The above results show that adding differential coding technology to 16QAM can solve the phase ambiguity problem well. In the carrier synchronization module, the power detection technology is introduced on the basis of the traditional Costas ring to ensure the linear output of the phase detector, improve the tracking accuracy and speed, and overcome the adverse effects of 16QAM on the phase detector in the demodulation synchronization, significantly Improved system performance. In the bit synchronization module, the self-synchronization-based sooner or later gate algorithm adopted by the present invention is suitable for a system with a high sampling rate, can roughly estimate the clock offset, and has a simple structure and is easy to realize by FPGA hardware.

In order to further verify the performance of the algorithm proposed in the present invention, Fig. 17 shows the theoretical BER and simulated BER of 16QAM, and the BER of 16QAM using this algorithm is very close to the theoretical value.

There are many specific application approaches of the present invention, and the above description is only a preferred embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, some improvements can also be made without departing from the principles of the present invention. Improvements should also be regarded as the protection scope of the present invention.

Claims (2)

1. a 16QAM demodulation synchronization method is characterized in that comprising the following steps: 1) Carrier synchronization: Assuming that the signal y(n) is received at time n, the signal q(n) is obtained after demodulation, τ is the power detection threshold, and the output of the phase detector is 0 when |q(n)| ² <τ, When |q(n)| ² >τ, the phase detector outputs the phase error value e(n) of the signal point at this moment. After the phase error is smoothed by the loop filter, the NCO is controlled to gradually eliminate the frequency offset and phase offset to achieve carrier synchronization; Select the power detection threshold τ, convert the 16QAM phase error detection constellation diagram into a QPSK constellation diagram, and then use the COSTAS loop for demodulation; 2) performing matched filtering on the in-phase and quadrature component signals respectively; 3) Perform bit timing recovery on the in-phase and quadrature signals through the "sooner or later gate", let τ=T/2, the model of the timing error detector can be deduced: <mfenced open = "" close = ""><mtable><mtr><mtd><mrow><mi>e</mi><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow><mo>=</mo><msub><mi>u</mi><mi>I</mi></msub><mrow><mo>(</mo><mrow><mi>n</mi><mo>+</mo><mi>&amp;tau;</mi><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mrow><mo>&amp;lsqb;</mo><mrow><msub><mi>u</mi><mi>I</mi></msub><mrow><mo>(</mo><mrow><mi>n</mi><mo>+</mo><mfrac><mn>1</mn><mn>2</mn></mfrac><mo>+</mo><mi>&amp;tau;</mi><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mo>-</mo><msub><mi>u</mi><mi>I</mi></msub><mrow><mo>(</mo><mrow><mi>n</mi><mo>-</mo><mfrac><mn>1</mn><mn>2</mn></mfrac><mo>+</mo><mi>&amp;tau;</mi><mrow><mo>(</mo><mrow><mi>n</mi><mo>-</mo><mn>1</mn></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow></mrow><mo>&amp;rsqb;</mo></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>+</mo><msub><mi>u</mi><mi>Q</mi></msub><mrow><mo>(</mo><mrow><mi>n</mi><mo>+</mo><mi>&amp;tau;</mi><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mrow><mo>&amp;lsqb;</mo><mrow><msub><mi>u</mi><mi>Q</mi></msub><mrow><mo>(</mo><mrow><mi>n</mi><mo>+</mo><mfrac><mn>1</mn><mn>2</mn></mfrac><mo>+</mo><mi>&amp;tau;</mi><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow><mo>)</mo></mrow><mo>-</mo><msub><mi>u</mi><mi>Q</mi></msub><mrow><mo>(</mo><mrow><mi>n</mi><mo>-</mo><mfrac><mn>1</mn><mn>2</mn></mfrac><mo>+</mo><mi>&amp;tau;</mi><mrow><mo>(</mo><mrow><mi>n</mi><mo>-</mo><mn>1</mn></mrow><mo>)</mo></mrow></mrow><mo>)</mo></mrow></mrow><mo>&amp;rsqb;</mo></mrow></mrow></mtd></mtr></mtable></mfenced> where τ(n) is the sampling clock for compensation, Represents the transition value of the n+1th and nth symbol, Represents the transition value of the nth and n-1th symbols, and the NCO output can be obtained from the above formula: τ(n+1)=τ(n)+γ·e(n), where γ is the step parameter; 4) Setting the threshold to perform sampling judgment and 4-2 level conversion on the two signals respectively to obtain parallel signals; 5) After performing differential decoding and parallel-to-serial conversion on the parallel signal, the original signal is recovered. 2. 16QAM demodulation synchronous method according to claim 1, is characterized in that: step 1) in phase error value e (n) derives as follows, if receiving signal r (k) is: r(k)=a(k)cos[(ω _c ±ω _d )kT _s +θ]-b(k)sin[(ω _c ±ω _d )kT _s +θ]+n(t), where ω _d is the Doppler frequency shift, θ is the carrier phase shift, n(t) is the Gaussian noise at the receiving end, a(k) and b(k) are the in-phase and quadrature components of the baseband symbols, and T _s is Sampling period; the signal is obtained after quadrature mixing and low-pass filtering to remove high-frequency components: U _I (k)＝a(k)cos[(ω _c ±ω _d -ω _o )kT _s +θ-θ _o ]-b(k)sin[(ω _c ±ω _d -ω _o )kT _s + θ-θ _o ], U _Q (k)＝b(k)cos[(ω _c ±ω _d -ω _o )kT _s +θ-θ _o ]+a(k)sin[(ω _c ±ω _d -ω _o )kT _s + θ-θ _o ], The power detection value P(k) is: P(k)＝(U _I (k)) ² +(U _Q (k)) ² When P(k)<τ, the phase detector error e(k)=0; when P(k)>τ, set Δφ=(ω _c ±ω _d -ω _o )k _s T+θ- _o θ, the U _I and U _Q are sent to the phase detector, where the phase detector is based on the hard decision algorithm, when very young, The phase detector error e(k) can be obtained: