CN104822032B - A kind of signal acquisition and automatic exposure circuit and its method based on linear CCD - Google Patents

Abstract

The invention discloses a linear CCD-based signal acquisition and automatic exposure circuit and a method thereof, which belong to the field of photoelectric technology. The circuit includes a microprocessor, a CCD signal acquisition and conversion unit connected to the microprocessor through the microprocessor SPI interface and an I/O interface, and the linear CCD is respectively connected to the microprocessor SPI interface and the CCD signal acquisition and conversion unit through its interface The units are connected, wherein the CCD signal acquisition and conversion unit includes a comparison trigger module, and a CCD output voltage amplification module and a dynamic threshold generation module connected to the comparison trigger module. The signal acquisition and automatic exposure circuit and the method thereof in the present invention do not need A/D conversion, can automatically adjust the exposure time of the CCD within a certain light intensity range, and have strong adaptability.

Description

A linear CCD-based signal acquisition and automatic exposure circuit and its method

technical field

The invention relates to a linear CCD-based signal acquisition and automatic exposure circuit and a method thereof, belonging to the field of photoelectric technology.

Background technique

TSL1401CL is a linear CCD. Its core is a photosensitive array composed of 128 photodiodes. There is a row of integrating capacitors behind the array. The photodiodes generate photocurrent under the impact of light energy to form an active integrating circuit. The integrating capacitors are used to store Electric charge after conversion of light energy. The more charges stored in the integrating capacitor, the greater the light intensity collected by the corresponding photodiode in front. It is reflected in the pixels that the grayscale of the pixels is low. The light intensity is close to saturation, and the gray scale of the pixel point is close to full white, then it is white level, and the larger the output voltage value is. The first 18 clock cycles are the pixel reset time, no integration and exposure are performed, the exposure time is from the 19th CLK to the next SI, so during the operation of the linear CCD, the SI signal is equivalent to a sign, when it becomes high After leveling, the data can be sampled after the high level of each CLK signal arrives, and the exposure time of the sampled data is determined by the time from the 19th CLK of the previous time to the appearance of the SI high level this time. The stronger the light, the faster the charge stored in the integrating capacitor, and the shorter the exposure period should be; the weaker the light, the slower the charge stored in the integrating capacitor, and the longer the exposure period should be.

The current linear CCD exposure time adjustment and data acquisition methods mainly include the following two methods:

1. The microprocessor directly collects the analog voltage data output by the CCD through A/D conversion and converts it into digital information. The microprocessor adjusts the time interval between two SIs through data analysis. This method mainly uses microprocessor software to Analyzing data, the CPU program is complicated, the data acquisition speed is slow, and the environmental adaptability is poor;

2. The hardware circuit is used to binarize black and white pixel voltages, but the threshold reference voltages of the 128 pixel points of the CCD are the same, resulting in misjudgment of the corresponding pixels on both sides of the CCD.

In view of this, the inventor conducted research on this, and specially developed a linear CCD-based signal acquisition and automatic exposure circuit and its method, and this case arose from it.

Contents of the invention

The purpose of the present invention is to provide a linear CCD-based signal acquisition and automatic exposure circuit and its method, which can automatically adjust the exposure time of the CCD within a certain light intensity range without A/D conversion, and has strong adaptability.

In order to achieve the above object, the solution of the present invention is:

A signal acquisition and automatic exposure circuit based on a linear CCD, including a microprocessor, a CCD signal acquisition and conversion unit connected to the microprocessor through an SPI interface and an I/O interface of the microprocessor, and the linear CCD is respectively connected to the microprocessor through its interface. The SPI interface of the processor is connected to the CCD signal acquisition and conversion unit, wherein the CCD signal acquisition and conversion unit includes a comparison trigger module, and a CCD output voltage amplification module and a dynamic threshold generation module connected to the comparison trigger module.

As preferably, the CCD output voltage amplifying module includes an amplifier, a sliding rheostat connected to the amplifier, the same input terminal of the amplifier is connected to the voltage output terminal of the linear CCD through a resistor, and the output terminal of the amplifier is connected to the first comparison trigger module. The first comparator and the second comparator are connected, and the amplification factor of the amplifier is adjusted by changing the resistance value of the first sliding rheostat.

Preferably, the dynamic threshold generating module includes a counter, a P-type MOS transistor and an N-type MOS transistor connected to the counter through an AND gate, and a follower connected to the P-type MOS transistor and the N-type MOS transistor, wherein the P-type MOS transistor The tube is connected to the third sliding rheostat, and the N-type MOS tube is connected to the fourth sliding rheostat. The output terminal of the follower is first connected in series with a resistor, and then connected in parallel with a charging capacitor, and then connected to the input terminal of the first comparator.

Preferably, the comparison trigger module includes a first comparator connected in parallel to the output terminal of the amplifier, a second comparator, and a flip-flop connected to the output terminal of the second comparator, and the non-inverting input terminal of the second comparator is connected to the output terminal of the first comparator. The two sliding rheostats are connected, and the output terminals of the first comparator and the flip-flop are connected with the SPI interface of the microprocessor.

Preferably, the trigger is a trigger with a model number of 74HC74.

A signal acquisition and automatic exposure method based on a linear CCD, comprising the steps of:

1) First, make the SPI interface of the microprocessor work in the main mode, set the working frequency CLK to 400KHZ, and at the same time use CLK as the working clock of the linear CCD, set the timer of the microprocessor so that the timing time (ie exposure time) is initially The value is set to 5 milliseconds, as the initial value of the linear CCD exposure, a timing interrupt is generated every 5 milliseconds, and the SPI is enabled to continuously output 16 bytes of data through the MOSI port (1 0x80, the remaining 15 0x00, and the SI high level starts the linear CCD) to form the SI signal required by the linear CCD, and at the same time use the MOSI signal and CLK signal sent by the microprocessor as the linear CCD start signal SI, CLK to start the linear CCD work;

2) Under the conditions of CLK and SI, the linear CCD transmits the output voltage to the amplifier through a resistor, adjusts the multiple of the amplifier through the first sliding rheostat, and observes the output voltage value of the amplifier through an oscilloscope to make the middle pixel point white point level The value is close to 4V, and the average voltage of the white point and black point of the middle and both sides of the pixel is recorded at the same time;

3) Adjust the resistance of the third sliding rheostat and the fourth sliding rheostat, that is, adjust the output voltage of the two sliding rheostats, and then control the conduction and/or cut-off of the P-type MOS transistor and the N-type MOS transistor by combining field effect transistors, The dynamic threshold reference voltage VREF of the charging and discharging output of the charging capacitor;

4) Adjust the second sliding rheostat to divide the output voltage VMAX so that VMAX=4V;

5) The output voltage value of the linear CCD is amplified by the amplifier and then enters two comparators. Compared with the voltage value VREF output by the dynamic threshold generation module, the output value MISO represents the black and white of the pixel in front of the linear CCD. When MISO=1, it means that this pixel The point is white, otherwise it is black. After the first high-level output of MOSI, the MISO input of 128 consecutive CLK clocks represents the value of 128 black and white pixels in front of the CCD; compare the output value with VMAX to connect the trigger The setting terminal of the flip-flop, MOSI controls the reset terminal of the flip-flop. When the MOSI signal outputs the first high-level signal, the flip-flop reset output signal OVER is low. Once the output voltage of the amplifier is between 1-128 CLK As long as the value is greater than VMAX once, the trigger is set, and the output signal OVER will remain high until the next high level of the MOSI signal comes;

6) Whenever the timer generates an interrupt, the microprocessor will judge whether the exposure is excessive according to the value of the OVER signal. The exposure time (about the time interval between two SI signals) is the timing time. If OVER=1, the exposure time If it is too long, change the timing parameters, shorten the timing time, and reduce the exposure time; otherwise, if the exposure time is considered insufficient, lengthen the timing time, and repeat this adjustment to ensure that the output voltage of the linear CCD remains at a maximum of about 4V after being amplified.

The linear CCD-based signal acquisition and automatic exposure circuit and method thereof in the present invention can automatically adjust the exposure time of the CCD within a certain light intensity range, which can not only ensure that the output voltage of the white pixel is not saturated when the light intensity is high, but also can Ensure that when the light is weak, the pixel output voltage is not too low, which can basically ensure that the output voltage corresponding to black and white pixels remains within a certain dynamic range under different light conditions, and a dynamic threshold reference voltage can be used to distinguish black and white pixels The characteristics of the dynamic threshold reference voltage are: the threshold reference voltage corresponding to the 128 pixels in front of the CCD presents an arc shape, high in the middle, and low on both sides. This feature is consistent with the characteristics of the linear CCD itself. Under the same environment, the two sides The output voltage of the photocell circuit is low, and the dynamic threshold reference voltage can well avoid misjudgment of pixels on both sides. In addition, the exposure method has strong adaptability, does not use A/D conversion, and does not require a special timing drive generation circuit. The SPI works in the main mode, and sends out the start signal and receives the pixel information at the same time, which not only provides the start signal CLK and SI required by the linear CCD, but also collects the information of 128 pixels in front of the CCD, which saves CPU resources and makes software programming easier. Simple, it can be used for normal exposure in the fluorescent environment of the laboratory and the strong light of the gymnasium.

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

Description of drawings

Fig. 1 is the signal acquisition based on linear CCD and the functional block diagram of automatic exposure circuit of the present embodiment;

Fig. 2 is the functional block diagram of the CCD signal acquisition and conversion unit of the present embodiment;

Fig. 3 is the circuit diagram of the CCD output voltage amplification module and comparison trigger module of the present embodiment;

FIG. 4 is a circuit diagram of the dynamic threshold generation module of this embodiment.

detailed description

As shown in Figure 1-2, a linear CCD-based signal acquisition and automatic exposure circuit includes a microprocessor 1, and the CCD signal acquisition and conversion connected to the microprocessor 1 through the microprocessor SPI interface and I/O interface Unit 2, the linear CCD3 is respectively connected with the microprocessor SPI interface and the CCD signal acquisition and conversion unit 2 through its interface, wherein, the CCD signal acquisition and conversion unit 2 includes a comparison trigger module 22, and the comparison trigger module 22 is connected CCD output voltage amplification module 21 and dynamic threshold generation module 23 .

As shown in Figure 3-4, described CCD output voltage amplifying module 21 comprises amplifier U2, the sliding rheostat RV1 that is connected with amplifier U2, the same direction input terminal of described amplifier U2 is connected with the voltage output terminal ( AO terminal) is connected, the output terminal of the amplifier U2 is connected with the first comparator U6 and the second comparator U7 of the comparison trigger module 22, and the amplification factor of the amplifier U2 is adjusted by changing the resistance value of the first sliding rheostat RV1. The dynamic threshold generation module 23 includes a counter U1, a P-type MOS transistor Q2 and an N-type MOS transistor Q1 connected to the counter U1 through an AND gate U5, and a follower U3 connected to the P-type MOS transistor Q2 and the N-type MOS transistor Q1 , wherein, the P-type MOS transistor Q2 is connected to the third sliding rheostat RV3, the N-type MOS transistor Q1 is connected to the fourth sliding rheostat RV4, the output terminal of the follower U3 is first connected in series with a resistor R9, and then connected in parallel with a charging capacitor C1, and then connected to the first A comparator U6 input terminal is connected. The comparison trigger module 22 includes a first comparator U6, a second comparator U7 connected in parallel to the output terminal of the amplifier U2, and a flip-flop U4 connected to the output terminal of the second comparator U7, the same direction of the second comparator U7 The input end is connected with the second sliding rheostat RV2 , and the output ends of the first comparator U6 and the flip-flop U4 are both connected with the SPI interface of the microprocessor 1 . In this embodiment, the flip-flop U4 is a flip-flop of the type 74HC74.

A signal acquisition and automatic exposure method based on a linear CCD, comprising the following steps:

1) First, the SPI interface of microprocessor 1 works in the main mode, and the working frequency CLK is set to 400KHZ. At the same time, CLK is used as the working clock of linear CCD3, and the timer of microprocessor 1 is set so that the timing time (ie exposure time) The initial value is set to 5 milliseconds. As the initial value of linear CCD3 exposure, a timing interrupt is generated every 5 milliseconds to enable SPI to continuously output 16 bytes of data through the MOSI port (that is, 128 bits, the first bit is high level 1, other 127 bit is 0), forming the SI signal (high level of a CLK clock) required by the linear CCD3, and at the same time, the MOSI signal and the CLK signal sent by the microprocessor 1 are respectively used as the start signal SI and CLK of the linear CCD3 to start the linear CCD3 start working;

2) The working voltage of linear CCD3 is 5V, (at different exposure times and different light intensities, the output voltage range of each pixel can be between 0-5V after the amplifier embedded in the linear CCD circuit module or external amplification.) Linear Under the conditions of CLK and SI, CCD3 adjusts the multiple of amplifier U2 through the first sliding rheostat RV1, and observes the output voltage value CCD-AO of amplifier U2 through an oscilloscope, so that the white point level of the middle pixel is close to 4V, and records the middle and both sides at the same time Average voltage V _w , V _b of pixel white point and black point;

3) Adjust the resistance values of the third sliding rheostat RV3 and the fourth sliding rheostat RV4, that is, adjust the output voltages of the two sliding rheostats to generate voltage values V _w and V _{b respectively.} In the dynamic threshold generation module, _{Vw and Vb are} used as the reference voltage for charging and discharging. In the first 96 cycles of 128 CLK cycles, the AND gate U5 outputs a low level, and the combined field effect transistor P-type MOS transistor Q2 is turned on. The N-type MOS transistor Q1 is turned off, the charging capacitor C1 charges and outputs the threshold reference voltage VREF, and the voltage value VREF rises from V _b to approach and maintain V _w ; in the last 32 cycles of 128 CLK cycles, the AND gate U5 outputs a high voltage Ping, P-type MOS transistor Q2 is cut off, N-type MOS transistor Q1 is turned on, charging capacitor C1 is discharged, and the output reference voltage VREF starts to drop from V _w to close to V _b, ; after 128 clocks, SPI ends, CLK stops, and gate U5 outputs Keep the high level, the output reference voltage VREF keeps V _b, to ensure that when the SI starts the CCD next time, the reference voltage VREF starts from V _b (because the defect of the linear CCD is: the output voltage corresponding to the middle pixel point is high, and the output voltage on both sides low, so the circuit ensures that the threshold reference voltage for binarization of black and white pixels on both sides is low on both sides and high in the middle; and because the discharge is fast, the charging time is longer than the discharging time.)

4) Adjust the second sliding rheostat RV2 to divide the output voltage VMAX so that VMAX=4V;

5) The output voltage AO value of the linear CCD3 is amplified by the amplifier U2 and becomes CCD-AO, and the CCD-AO enters two comparators, and compares it with VREF to output MISO, which represents the black and white value of the pixel in front of the linear CCD. When MISO=1, it means this The pixel is white, otherwise it is black. After the first high-level output of MOSI, the MISO input of 128 consecutive CLK clocks represents the value of 128 black and white pixels in front of the CCD; the value compared with VMAX is connected to the trigger The set end of the trigger U4, MOSI controls the reset end of the flip-flop U4, when the MOSI signal outputs the first high-level signal, the reset output signal OVER of the flip-flop U4 is low, once between 1-128 CLKs as long as Once the CCD-AO signal value is greater than VMAX, the trigger U4 is set, and the output signal OVER will remain high until the next high level of the MOSI signal comes;

6) Whenever the timer generates an interrupt, the microprocessor 1 will judge whether the exposure is excessive according to the value of the OVER signal. The exposure time (about the time interval between two SI signals) is the timing time. If OVER=1, the exposure If the time is too long, change the timing parameters, shorten the timing time, and reduce the exposure time; otherwise, if the exposure time is considered insufficient, lengthen the timing time, and repeat this adjustment to ensure that the output voltage of the linear CCD remains at a maximum of about 4V after being amplified.

The above-mentioned embodiments and drawings do not limit the form and style of the product of the present invention, and any appropriate changes or modifications made by those skilled in the art should be considered as not departing from the patent scope of the present invention.

Claims (4)

1. a kind of signal acquisition and automatic exposure circuit based on linear CCD, it is characterised in that：Including microprocessor, by micro- The ccd signal collection and converter unit, linear CCD that processor SPI interface, I/O interfaces are connected with microprocessor pass through its interface It is connected respectively with microprocessor SPI interface and ccd signal collection with converter unit, wherein, the ccd signal collection and conversion are single Member includes comparing trigger module, and the connected CCD output voltages amplification module of trigger module and dynamic threshold produce compared with Module；The CCD output voltages amplification module includes amplifier, the slide rheostat being connected with amplifier, the amplifier Input in the same direction is connected by a resistance with the voltage output end of linear CCD, the output end of the amplifier trigger module compared with First comparator, the second comparator are connected, the times magnification of the big minor adjustment amplifier of resistance by changing the first slide rheostat Number；The dynamic threshold generation module includes counter, by p-type metal-oxide-semiconductor, the N-type metal-oxide-semiconductor being connected with door with counter, with And the follower being connected with p-type metal-oxide-semiconductor, N-type metal-oxide-semiconductor, wherein, p-type metal-oxide-semiconductor is connected with the 3rd slide rheostat, N-type metal-oxide-semiconductor It is connected with the 4th slide rheostat, the output end of follower is first connected after a resistance, then a charging capacitor in parallel with first Comparator input terminal is connected.

2. a kind of signal acquisition and automatic exposure circuit based on linear CCD as claimed in claim 1, it is characterised in that：Institute State and compare trigger module and include being connected in parallel on first comparator, the second comparator of amplifier out, and with the second comparator The connected trigger of output end, the input in the same direction of second comparator are connected with the second slide rheostat, first comparator It is connected with the output end of trigger with the SPI interface of microprocessor.

3. a kind of signal acquisition and automatic exposure circuit based on linear CCD as claimed in claim 2, it is characterised in that：Institute State the trigger that trigger uses model 74HC74.

4. the signal acquisition of as claimed in claim 1 a kind of signal acquisition and automatic exposure circuit based on linear CCD and from Dynamic exposure method, it is characterised in that comprise the following steps：

1）The SPI interface of microprocessor is operated under holotype first, it is 400KHZ to set working frequency CLK, while by CLK As the work clock of linear CCD, the timer of microprocessor is set, timing initial value is set to 5 milliseconds, as linear The initial value of CCD exposures, every 5 milliseconds of generations Interruption, enables SPI and continuously exports 16 byte datas, shape by MOSI mouths The SI signals that linear CCD needs, while MOSI signals that microprocessor is sent and CLK signal are as linear CCD Enabling signal SI and CLK, start linear CCD work；

2）Linear CCD is transported to amplifier under conditions of CLK and SI, by output voltage by a resistance, is slided by first Rheostat adjusts the multiple of amplifier, and the output voltage values of amplifier are observed by oscillograph, makes intermediary image vegetarian refreshments white point electric Level values record middle and both sides pixel white point and stain average voltage close to 4V；

3）The resistance of the 3rd slide rheostat and the 4th slide rheostat is adjusted, that is, adjusts the output electricity of two slide rheostats Pressure, and then by combining the conducting and/or cut-off of field-effect management and control p-type metal-oxide-semiconductor, N-type metal-oxide-semiconductor, charging capacitor discharge and recharge is defeated Go out dynamic threshold reference voltage VREF；

4）The second slide rheostat is adjusted, pressure-dividing output voltage value VMAX, makes VMAX=4V；

5）The output voltage values of linear CCD are amplified into two comparators by amplifier, defeated with dynamic threshold generation module The magnitude of voltage VREF gone out compares, and output represents the value MISO of pixel black and white in front of linear CCD, when MISO=1, illustrates this pixel Point is white, and otherwise to be black, after MOSI first high level output, the MISO inputs of continuous 128 CLK clocks are exactly Represent the value of 128 monochrome pixels points in front of CCD；The set end of the value connection trigger of the output compared with VMAX, MOSI controls The reset terminal of trigger, in first high level signal of MOSI signal outputs, trigger reset output signal OVER is low electricity It is flat, once as long as the magnitude of voltage that amplifier exports between 1-128 CLK is once more than VMAX, make trigger set, export Signal OVER can be always maintained at high level, until the high level of next MOSI signals arrives；

6）Whenever timer produces interruption, microprocessor will judge to expose whether excessive, the time for exposure according to the value of OVER signals As timing, if OVER=1, the time for exposure is long, changes timing parameters, shortens timing, when reducing exposure Between；Otherwise it is assumed that the time for exposure is inadequate, timing is lengthened, is so adjusted repeatedly, ensure the output voltage of linear CCD by putting Maximum is maintained at 4V after big.