CN104952847A - Wafer acceptance testing structure and forming method therefor - Google Patents
Wafer acceptance testing structure and forming method therefor Download PDFInfo
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- CN104952847A CN104952847A CN201410124015.9A CN201410124015A CN104952847A CN 104952847 A CN104952847 A CN 104952847A CN 201410124015 A CN201410124015 A CN 201410124015A CN 104952847 A CN104952847 A CN 104952847A
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- wafer
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- contact hole
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 43
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 9
- 239000004411 aluminium Substances 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 abstract 6
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000005267 amalgamation Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a wafer acceptance testing structure and a forming method therefor. The structure comprises a dielectric layer and one or more capacitors formed in the dielectric layer, wherein each capacitor is used for storing charges so as to carry out the charge testing of a wafer. The forming method comprises the steps: providing the dielectric layer; and forming one or more capacitors in the dielectric layer, wherein each capacitor is used for storing charges so as to carry out the charge testing of the wafer. The capacitors which are formed in the dielectric layer are used for locking charges, so as to carry out the charge testing of the wafer. The charge-locking capacity of the capacitors is very strong, and especially is much stronger than the locking capability of an oxidation layer or surfaces of other dielectric layers, thereby preventing/alleviating the escape of charges along with the flying of time, and improving the testing accuracy.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of receivable test structure of wafer and forming method thereof.
Background technology
Usual wafer, after creating, after entering before continuous cutting encapsulation, needs to carry out selection test to it.By selection test by minimum unit, i.e. crystal granules sorted, by defectiveness or the upper mark of crystal grain mark not possessing normal ability to work, and when cutting crystal wafer, these crystal grain are filtered out and abandon.Thus avoid bad crystal grain to enter encapsulation and successive process, avoid the waste for no reason of cost.Selection test generally includes wafer acceptance test (WAT, Wafer Acceptance Test) and circuit detection (CP, Circuit Probe).
WAT detecting step is after completing wafer production in early stage, and before wafer cutting and encapsulation, be used for ensureing, once occur by the mistake in wafer production in early stage and make the situation that crystal grain cannot normally work, to be detected in advance by WAT, with cost-saving.Due in the project that WAT tests; contain the destroyed test of many items; if directly apply on crystal grain; the destruction to crystal grain must be caused; thus the yield affected when dispatching from the factory; therefore usually can when making crystal grain, the space between each crystal grain and crystal grain, namely Cutting Road (scribe line) makes test structure (test key).WAT test is exactly by the detection to these test structures, thus infers that whether the service behaviour of element in crystal grain near it is intact.Usually said WAT test parameter refers to, carries out the electrical parameter data that electrical property measurement obtains, such as threshold voltage, drain saturation current etc. to these elements.
In WAT detects, also comprise the test to wafer electric charge.In prior art, usually carry out the test of wafer electric charge by the electric charge of an oxide layer or the locking of other dielectric layer surface, its structure can with reference to figure 1.As shown in Figure 1, the test of wafer electric charge is carried out by the electric charge 11 of oxide layer 10 surface lock.But, carry out the test of wafer electric charge by this structure and there is some problem following:
1, the electric charge of oxide layer or the locking of other dielectric layer surface is escaped very easily as time goes by, thus makes the accuracy of test not high;
2, the precision of test is not high enough, usually only can test the electric charge of 10-10V level;
3, this structure only can be only used once, and namely can not be recycled.
Therefore, provide a kind of receivable test structure of wafer, it can realize good electric charge lock function etc., has become those skilled in the art's a great problem to be solved.
Summary of the invention
The object of the present invention is to provide a kind of receivable test structure of wafer and forming method thereof, escape very easily as time goes by with the electric charge solving receivable test structure of wafer of the prior art locking, thus make the problem that the accuracy of test is not high.
For solving the problems of the technologies described above, the invention provides a kind of receivable test structure of wafer, described receivable test structure of wafer comprises: dielectric layer and one or more electric capacity be formed in described dielectric layer, each electric capacity in order to stored charge to carry out the test of wafer electric charge.
Optionally, in described receivable test structure of wafer, also comprise and be formed at Ti layer on described dielectric layer and TiN layer.
Optionally, in described receivable test structure of wafer, each electric capacity comprises metal electrode, lower metal electrode and the dielectric isolation structure between upper metal electrode and lower metal electrode, and wherein, described upper metal electrode is near described Ti layer and TiN layer.
Optionally, in described receivable test structure of wafer, described upper metal electrode is TaN layer.
Optionally, in described receivable test structure of wafer, described lower metal electrode is copper metal line or aluminum metal lines.
Optionally, in described receivable test structure of wafer, described dielectric isolation structure is silicon oxide layer.
Optionally, in described receivable test structure of wafer, in described dielectric layer, be also formed with multiple contact hole, in described multiple contact hole, be filled with metallic aluminium.
Optionally, in described receivable test structure of wafer, the material of described dielectric layer is silica.
The present invention also provides a kind of formation method of receivable test structure of wafer, and the formation method of described receivable test structure of wafer comprises: provide dielectric layer; In described dielectric layer, form one or more electric capacity, each electric capacity in order to stored charge to carry out the test of wafer electric charge.
Optionally, in the formation method of described receivable test structure of wafer, form one or more electric capacity in described dielectric layer after, also comprise:
In described dielectric layer, form multiple contact hole, in each contact hole, fill metallic aluminium.
Optionally, in the formation method of described receivable test structure of wafer, in described dielectric layer, form multiple contact hole, fill metallic aluminium in each contact hole after, also comprise:
Form Ti layer and TiN layer at described dielectric layer and contact hole surface, wherein, Ti layer and the TiN layer on each contact hole surface are mutually isolated.
In receivable test structure of wafer provided by the invention and forming method thereof, by being formed at one or more electric capacity locked-in charge in dielectric layer to carry out the test of wafer electric charge, because electric capacity is very strong for the locking ability of electric charge, especially, much better than relative to the locking ability of oxide layer or other dielectric layer surface, thus, avoid/alleviate electric charge to escape as time goes by, thus improve the accuracy of test.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the receivable test structure of wafer carrying out the test of wafer electric charge in prior art;
Fig. 2 is a schematic diagram of the receivable test structure of wafer of the embodiment of the present invention;
Fig. 3 is another schematic diagram of the receivable test structure of wafer of the embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, receivable test structure of wafer that the present invention proposes and forming method thereof is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, by being formed at one or more electric capacity locked-in charge in dielectric layer to carry out the test of wafer electric charge, because electric capacity is very strong for the locking ability of electric charge, especially, much better than relative to the locking ability of oxide layer or other dielectric layer surface, thus, avoid/alleviate electric charge to escape as time goes by, thus improve the accuracy of test.
Concrete, please refer to Fig. 2, it is a schematic diagram of the receivable test structure of wafer of the embodiment of the present invention.As shown in Figure 2, described receivable test structure of wafer comprises: dielectric layer 20 and one or more electric capacity 21 be formed in described dielectric layer 20, each electric capacity 21 in order to stored charge to carry out the test of wafer electric charge.Fig. 2 shows a kind of general aspect of receivable test structure of wafer, or perhaps one the most substantially, the most Utopian form.Namely a dielectric layer 20 is comprised, be formed in described dielectric layer 20 and organize bonding jumper more, often organize bonding jumper and comprise two bonding jumpers, often two bonding jumpers organized in bonding jumper are isolated by dielectric isolation structure, thus form a kind of mim structure (metal-dielertric-metal), namely form capacitance structure.And by this capacitance structure locked-in charge.Further, the top electrode of each electric capacity 21 and bottom electrode are all connected to dielectric layer 20 surface by a metal wire, thus are easy to the electric charge on receiver media layer 20 surface.
By being formed at one or more electric capacity locked-in charge in dielectric layer to carry out the test of wafer electric charge, because electric capacity is very strong for the locking ability of electric charge, especially, much better than relative to the locking ability of oxide layer or other dielectric layer surface, thus, avoid/alleviate electric charge to escape as time goes by, thus improve the accuracy of test.Meanwhile, the electric charge locked by described electric capacity, its quantity and precision are also more increased, thus when carrying out the test of wafer electric charge, can realize more high-precision test, usually can test the electric charge of 10-12V level.
Easy to know, on the basis of the receivable test structure of wafer shown in Fig. 2, the receivable test structure of wafer of other concrete structures multiple can be formed.Such as, multiple contact hole structures etc. can also be formed in described dielectric layer.
Further, please refer to Fig. 3, it is another schematic diagram of the receivable test structure of wafer of the embodiment of the present invention.Fig. 3 shows a kind of receivable test structure of wafer, and itself and existing integrated circuit technology have better amalgamation, thus, more simple and feasible on technique realizes.
Concrete, please refer to Fig. 3, described receivable test structure of wafer comprises: dielectric layer 30, and the material of described dielectric layer 30 can be silica also can be silicon nitride etc.; Be positioned at the metal wire 31 of dielectric layer 30 lower surface, described metal wire 31 can be copper metal line also can be aluminum metal lines; Be arranged in the TaN layer 32 of dielectric layer 30; Described metal wire 31 is isolated by a dielectric isolation structure 33 with described TaN layer 32, wherein, the material of described dielectric isolation structure 33 can be silica also can be silicon nitride etc., and namely described dielectric isolation structure 33 can be achieved by described dielectric layer 30.Thus, just can form an electric capacity in described dielectric layer 30, described electric capacity comprises the lower metal electrode formed by metal wire 31, the upper metal electrode formed by TaN layer 32 and is positioned at metal wire 31 and namely TaN layer 32(go up metal electrode and lower metal electrode) between dielectric isolation structure 33.
In the embodiment of the present application, in described dielectric layer 30, be also formed with multiple contact hole 34, in described multiple contact hole 34, be filled with metallic aluminium.Concrete, metal electrode is gone up with TaN layer 32(in part contact hole 34 namely) be connected, namely part contact hole 34 and metal wire 31(descend metal electrode), by described contact hole 34, described upper metal electrode and lower metal electrode can be connected to the surface of dielectric layer 30, thus are easy to the electric charge on receiver media layer 30 surface.
In the embodiment of the present application, Ti layer and TiN layer (namely usually said Ti/TiN layer) 35 is also comprised, the described upper surface of Ti/TiN layer 35 blanket dielectric layer 30 and the surface of contact hole 34.Dielectric layer 30 under it and contact hole 34 can be protected by described Ti/TiN layer 35, thus described receivable test structure of wafer can be recycled.
Accordingly, the present embodiment also provides a kind of formation method of receivable test structure of wafer, specifically comprises: provide dielectric layer; One or more electric capacity is formed in described dielectric layer, each electric capacity in order to stored charge to carry out the test of wafer electric charge, concrete, in described dielectric layer, form two metal layers by techniques such as etching, deposits, described two metal layers is respectively the upper metal electrode of electric capacity and lower metal electrode.Then, in described dielectric layer, form multiple contact hole, in each contact hole, be filled with metallic aluminium.Wherein, part contact hole connects upper metal electrode, and part contact hole connects lower metal electrode.Then, Ti layer and TiN layer is formed at described dielectric layer and contact hole surface.Wherein, in order to prevent making described upper metal electrode and lower metal electrode short circuit by described Ti layer and TiN layer, Ti layer and TiN layer (adaptability is with reference to figure 3) can be formed by following technique: first, forming Ti layer and a TiN layer on contact hole surface; Then, an additional dielectric layer is formed, described additional dielectric layer blanket dielectric layer and contact hole surface; The 2nd Ti layer and TiN layer is formed on described additional dielectric layer surface; Etch described 2nd Ti layer and TiN layer and additional dielectric layer, expose Ti layer and a TiN layer.Thus, Ti layer and the TiN layer on each contact hole surface are kept apart by additional dielectric layer, thus avoid metal electrode and lower metal electrode short circuit; Meanwhile, by Ti layer and TiN layer, good protection has all been done to dielectric layer and contact hole again, thus described receivable test structure of wafer can be recycled.
As fully visible, in receivable test structure of wafer that the embodiment of the present invention provides and forming method thereof, by being formed at one or more electric capacity locked-in charge in dielectric layer to carry out the test of wafer electric charge, because electric capacity is very strong for the locking ability of electric charge, especially, much better than relative to the locking ability of oxide layer or other dielectric layer surface, thus, avoid/alleviate electric charge to escape as time goes by, thus improve the accuracy of test.
Foregoing description is only the description to present pre-ferred embodiments, any restriction not to the scope of the invention, and any change that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (11)
1. a receivable test structure of wafer, is characterized in that, comprising: dielectric layer and one or more electric capacity be formed in described dielectric layer, each electric capacity in order to stored charge to carry out the test of wafer electric charge.
2. receivable test structure of wafer as claimed in claim 1, is characterized in that, also comprises and is formed at Ti layer on described dielectric layer and TiN layer.
3. receivable test structure of wafer as claimed in claim 2, it is characterized in that, each electric capacity comprises metal electrode, lower metal electrode and the dielectric isolation structure between upper metal electrode and lower metal electrode, and wherein, described upper metal electrode is near described Ti layer and TiN layer.
4. receivable test structure of wafer as claimed in claim 3, it is characterized in that, described upper metal electrode is TaN layer.
5. receivable test structure of wafer as claimed in claim 3, it is characterized in that, described lower metal electrode is copper metal line or aluminum metal lines.
6. receivable test structure of wafer as claimed in claim 3, it is characterized in that, described dielectric isolation structure is silicon oxide layer.
7. the receivable test structure of wafer according to any one of claim 1 ~ 6, is characterized in that, is also formed with multiple contact hole in described dielectric layer, is filled with metallic aluminium in described multiple contact hole.
8. the receivable test structure of wafer according to any one of claim 1 ~ 6, is characterized in that, the material of described dielectric layer is silica.
9. a formation method for receivable test structure of wafer, is characterized in that, comprising: provide dielectric layer; In described dielectric layer, form one or more electric capacity, each electric capacity in order to stored charge to carry out the test of wafer electric charge.
10. the formation method of receivable test structure of wafer as claimed in claim 9, is characterized in that, after forming one or more electric capacity, also comprise in described dielectric layer:
In described dielectric layer, form multiple contact hole, in each contact hole, fill metallic aluminium.
The formation method of 11. receivable test structure of wafer as claimed in claim 10, is characterized in that, in described dielectric layer, form multiple contact hole, after filling metallic aluminium, also comprise in each contact hole:
Form Ti layer and TiN layer at described dielectric layer and contact hole surface, wherein, Ti layer and the TiN layer on each contact hole surface are mutually isolated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410124015.9A CN104952847A (en) | 2014-03-28 | 2014-03-28 | Wafer acceptance testing structure and forming method therefor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410124015.9A CN104952847A (en) | 2014-03-28 | 2014-03-28 | Wafer acceptance testing structure and forming method therefor |
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| CN104952847A true CN104952847A (en) | 2015-09-30 |
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| CN201410124015.9A Pending CN104952847A (en) | 2014-03-28 | 2014-03-28 | Wafer acceptance testing structure and forming method therefor |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0874395A2 (en) * | 1997-04-23 | 1998-10-28 | Lam Research Corporation | Methods and apparatus for detecting pattern dependent charging on a workpiece in a plasma processing system |
| US6582977B1 (en) * | 2002-08-29 | 2003-06-24 | Texas Instruments Incorporated | Methods for determining charging in semiconductor processing |
| US6614051B1 (en) * | 2002-05-10 | 2003-09-02 | Applied Materials, Inc. | Device for monitoring substrate charging and method of fabricating same |
| CN101055848A (en) * | 2006-04-10 | 2007-10-17 | 旺宏电子股份有限公司 | Test Structure and Method for Detecting Charging Effect Using Delayed Inversion Point Technology |
-
2014
- 2014-03-28 CN CN201410124015.9A patent/CN104952847A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0874395A2 (en) * | 1997-04-23 | 1998-10-28 | Lam Research Corporation | Methods and apparatus for detecting pattern dependent charging on a workpiece in a plasma processing system |
| US6614051B1 (en) * | 2002-05-10 | 2003-09-02 | Applied Materials, Inc. | Device for monitoring substrate charging and method of fabricating same |
| US6582977B1 (en) * | 2002-08-29 | 2003-06-24 | Texas Instruments Incorporated | Methods for determining charging in semiconductor processing |
| CN101055848A (en) * | 2006-04-10 | 2007-10-17 | 旺宏电子股份有限公司 | Test Structure and Method for Detecting Charging Effect Using Delayed Inversion Point Technology |
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Application publication date: 20150930 |
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