CN104978295A - Auxiliary erasing apparatus and method for NVM - Google Patents
Auxiliary erasing apparatus and method for NVM Download PDFInfo
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Abstract
The present invention relates to an auxiliary erasing apparatus and method for an NVM. The apparatus comprises a setting module, a system bus hanging module and a system bus recovering module, wherein the setting module is used for receiving a target erased page address and a setting indicating signal which are sent by a system bus, sending the target erased page address to an NVM controller and setting an erasing enabling site; the system bus hanging module is used for sending an erasing operation starting signal of executing an erasing operation on a target erased page corresponding to the target erased page address to the NVM controller according to the set erasing enabling site and enabling the system bus to be in a hung state; and the system bus recovering module is used for receiving an erasing operation completion signal sent after the NVM controller completes the erasing operation and recovering the system bus to a normal working state from the hung state according to the erasing operation completion signal. The auxiliary erasing apparatus and method for the NVM is used for omitting the inquiring operation, improving efficiency and meanwhile, ensuring the data dependency before and after the erasing operation.
Description
Technical field
The present invention relates to embedded system field, particularly relate to auxiliary erasing apparatus and the method for a kind of NVM.
Background technology
Along with the progress of society, the development of science and technology, embedded system obtains vigorous growth, and is used in multiple key areas.In embedded systems, nonvolatile memory (non-volatile memory, be called for short: pith NVM) being, NVM is mainly used in storing the necessary program code of embedded system or critical data, NVM mainly comprises embedded flash memory (embedded flash usually, EFLASH), electricallyerasable ROM (EEROM) (electricallyerasable programmable read only memory be called for short:, be called for short: EEPROM) and ROM (read-only memory) (read only memory, abbreviation: ROM).In recent years, along with the continuous lifting to embedded system performance demand, to the performance such as reading and writing and erasing of storer, especially higher requirement is proposed to the erasing performance of NVM.
The concrete methods of realizing that existing NVM performs erase operation is: first, be written in the special function register of NVM controller by system bus by needing the page information of erasing, then the erasing enable bit of system bus again in set special function register, then this erasing enable bit makes NVM start erase operation.Perform in whole erase operation process at NVM, because NVM is in the busy state carrying out erase operation always, so other all Access status to NVM will get clogged in system bus, by query manipulation, system bus judges whether NVM completes erase operation, until NVM perform erase operation terminate after, NVM controller can remove erasing enable bit automatically, thus system bus recovers the Access status before NVM execution erase operation after NVM erase operation terminates.
Above-mentioned this NVM performs erase operation method and implements relatively simple, but perform in erase operation process at NVM, by query manipulation, system bus constantly must judge whether the erase operation that NVM performs terminates, will make whole erase operation more complicated like this, efficiency is lower.In addition, query manipulation is also very important for guarantee data dependency, this is because the data when operation after erase operation performs may need the data relied on when erase operation completes to carry out, because system bus does not know that NVM performs the end time of erase operation, if do not carry out query manipulation, when NVM execution erase operation does not complete, system bus just may think that the erase operation that NVM performs completes, now system bus will send the order performing erase operation operation below, because the erase operation of NVM does not also complete, so the mistake operated can be there is because of needing the data relied on to change in erase operation operation below.
Summary of the invention
The invention provides auxiliary erasing apparatus and the method for a kind of NVM, in order to save query manipulation, raise the efficiency, ensure the dependence of data before and after erase operation simultaneously.
The invention provides the auxiliary erasing apparatus of a kind of nonvolatile memory NVM, comprising:
Set module, the target erasure page address sent for receiving system bus and set indicator signal, send to NVM controller by described target erasure page address, according to described set indicator signal set erasing enable bit;
Module hung up by system bus, for according to the erasing enable bit after set, send to described NVM controller the erase operation enabling signal that the target erasure page corresponding to described target erasure page address performs erase operation, and make described system bus be in suspended state;
System bus recovers module, for receiving the erase operation settling signal that described NVM controller sends after completing described erase operation, according to described erase operation settling signal, described system bus is reverted to normal operating conditions from described suspended state.
The present invention also provides a kind of nonvolatile memory NVM controller, comprising:
Writing module, the target erasure page address that the auxiliary erasing apparatus for receiving NVM sends, writes described target erasure page address in described NVM controller;
Erasing module, the target erasure page corresponding to described target erasure page address for the auxiliary erasing apparatus transmission receiving described NVM carries out the erase operation enabling signal of erase operation, according to described erase operation enabling signal, erase operation is carried out to the target erasure page corresponding with described target erasure page address;
Signal processing module, for after described erase operation terminates, removes erasing enable bit, generates erase operation settling signal, described erase operation settling signal is sent to the auxiliary erasing apparatus of described NVM.
The present invention also provides a kind of disposal system, comprise the auxiliary erasing apparatus of aforesaid NVM, processor, aforesaid NVM controller and NVM, the auxiliary erasing apparatus of described NVM is connected by system bus with between described processor, the auxiliary erasing apparatus of described NVM is connected by internal bus with between described NVM controller, is connected between described NVM with described NVM controller by internal interface.
The present invention also provides the auxiliary method for deleting of a kind of nonvolatile memory NVM, comprising:
The target erasure page address that receiving system bus sends and set indicator signal, send to NVM controller by described target erasure page address, according to described set indicator signal set erasing enable bit;
According to the erasing enable bit after set, send to described NVM controller the erase operation enabling signal that the target erasure page corresponding to described target erasure page address performs erase operation, and make described system bus be in suspended state;
Receive the erase operation settling signal that described NVM controller sends after completing described erase operation, according to described erase operation settling signal, described system bus is reverted to normal operating conditions from described suspended state.
The present invention also provides a kind of method of work of nonvolatile memory NVM controller, comprising:
The target erasure page address that the auxiliary erasing apparatus receiving NVM sends, writes described target erasure page address in described NVM controller;
The target erasure page corresponding to described target erasure page address that the auxiliary erasing apparatus receiving described NVM sends carries out the erase operation enabling signal of erase operation, according to described erase operation enabling signal, erase operation is carried out to the target erasure page corresponding with described target erasure page address;
After described erase operation terminates, remove erasing enable bit, generate erase operation settling signal, described erase operation settling signal is sent to the auxiliary erasing apparatus of described NVM.
In the present invention, the target erasure page address that set module receiving system bus sends and set indicator signal, target erasure page address is sent to NVM controller, and set erasing enable bit, system bus is hung up module and is sent to NVM controller the erase operation enabling signal that the target erasure page corresponding to target erasure page address performs erase operation according to the erasing enable bit after set, and make system bus be in suspended state, system bus recovers the erase operation settling signal that module reception NVM controller sends after completing erase operation, according to erase operation settling signal, system bus is reverted to normal operating conditions from suspended state, like this, by the suspended state of system bus with recover this two states of normal operating conditions can judge erase operation and the time of end from suspended state, make system bus need not carry out constantly query manipulation again and judge the time that erase operation terminates, eliminate query manipulation, improve efficiency, and be in the process of suspended state at system bus, no longer perform erase operation operation below, ensure that the dependence between the data before and after erase operation, prevent the situation of the operating mistake due to the generation of data dependence problem.
Accompanying drawing explanation
Fig. 1 is the structural representation of auxiliary erasing apparatus first embodiment of NVM of the present invention;
Fig. 2 is the specific works process schematic of auxiliary erasing apparatus first embodiment of NVM of the present invention;
Fig. 3 is the structural representation of auxiliary erasing apparatus second embodiment of NVM of the present invention;
Fig. 4 is the workflow schematic diagram of an example of auxiliary erasing apparatus second embodiment of NVM of the present invention;
Fig. 5 is the structural representation of NVM controller embodiment of the present invention;
Fig. 6 is the specific works process schematic of NVM controller embodiment of the present invention;
Fig. 7 is the structural representation of disposal system embodiment of the present invention.
Embodiment
Below in conjunction with specification drawings and specific embodiments, the invention will be further described.
As shown in Figure 1, for the structural representation of auxiliary erasing apparatus first embodiment of NVM of the present invention, this device specifically can comprise: module 12 hung up by set module 11, system bus and system bus recovers module 13, wherein, system bus is hung up module 12 and is connected with set module 11, and system bus recovery module 13 is hung up module 12 with system bus and is connected.
In the present embodiment, the target erasure page address that set module 11 sends for receiving system bus and set indicator signal, target erasure page address is sent to NVM controller, according to set indicator signal set erasing enable bit, particularly, target erasure page address can be sent in NVM controller by set module 11, then this target erasure page address can specifically be written in the special function register in NVM controller by NVM controller; System bus hangs up module 12 for according to the erasing enable bit after set, the erase operation enabling signal that the target erasure page corresponding to target erasure page address performs erase operation is sent to NVM controller, and make system bus be in suspended state, particularly, system bus is hung up module 12 and the erase operation enabling signal that the target erasure page corresponding to target erasure page address carries out erase operation is sent to NVM controller, then NVM controller carries out erase operation according to erase operation enabling signal to target erasure page; System bus recovers the erase operation settling signal that module 13 sends after completing erase operation for receiving NVM controller, according to erase operation settling signal, system bus is reverted to normal operating conditions from suspended state, thus system bus can send the order performing erase operation latter acts.
The specific works process of the present embodiment is as follows: as shown in Figure 2, is the specific works process schematic of auxiliary erasing apparatus first embodiment of NVM of the present invention, specifically can comprises the following steps:
The target erasure page address that step 21, set module 11 receiving system bus send and set indicator signal, send to NVM controller by target erasure page address, according to set indicator signal set erasing enable bit;
Particularly, in this step, target erasure page address can send in the special function register in NVM controller by set module 11;
Step 22, system bus hang up module 12 according to the erasing enable bit after set, send the erase operation enabling signal that the target erasure page corresponding to target erasure page address performs erase operation, and make system bus be in suspended state to NVM controller;
Wherein, NVM controller carries out erase operation according to erase operation enabling signal to target erasure page, this erase operation enabling signal makes system bus be suspended, and namely NVM starts real erase operation according to this erase operation enabling signal, i.e. the start time of erase operation; And before the erase operation that NVM performs completes, obstruction is not all performed by erase operation operation below, after NVM executes erase operation, the erasing enable bit of set can be removed by NVM controller, and sends erase operation settling signal to system bus recovery module 13;
Step 23, system bus recovery module 13 receives the erase operation settling signal that NVM controller sends after completing erase operation, according to erase operation settling signal, system bus is reverted to normal operating conditions from suspended state;
Like this, system bus recovers normal work, just can send the order performing erase operation latter acts.
In the present embodiment, the target erasure page address that set module 11 receiving system bus sends and set indicator signal, target erasure page address is sent to NVM controller, and set erasing enable bit, system bus is hung up module 12 and is sent to NVM controller the erase operation enabling signal that the target erasure page corresponding to target erasure page address performs erase operation according to the erasing enable bit after set, and make system bus be in suspended state, system bus recovery module 13 receives the erase operation settling signal that NVM controller sends after completing erase operation, according to erase operation settling signal, system bus is reverted to normal operating conditions from suspended state, like this, by the suspended state of system bus with recover this two states of normal operating conditions can judge erase operation and the time of end from suspended state, make system bus need not carry out constantly query manipulation again and judge the time that erase operation terminates, eliminate query manipulation, improve efficiency, and be in the process of suspended state at system bus, no longer perform erase operation operation below, ensure that the dependence between the data before and after erase operation, prevent the situation of the operating mistake due to the generation of data dependence problem.
Alternatively, in the present embodiment, erase operation enabling signal is specifically as follows write operation, can also be read operation or other operation, such as: make NVM perform erase operation to target erasure page by performing read operation or write operation etc. to some registers.The execution of this erase operation enabling signal is to make NVM start erase operation, so no matter this erase operation enabling signal specifically what operation, its object is all finally to make NVM perform erase operation, make system bus be in the state of hang-up simultaneously.
Alternatively, in the present embodiment, the auxiliary erasing apparatus of NVM, except existing as independent device, can also be arranged in NVM controller, the auxiliary erasing apparatus of NVM is communicated by internal bus with between NVM controller, thus realizes concrete function.
Alternatively, in the present embodiment, NVM is specifically as follows EEPROM, can also EFLASH or ROM.
As shown in Figure 3, for the structural representation of auxiliary erasing apparatus second embodiment of NVM of the present invention, the present embodiment adds auxiliary erasing module 31 on the basis of a upper embodiment and buffer memory removes module 32, auxiliary erasing module 31 is removed module 32 with buffer memory and is connected, and buffer memory removing module 32 is hung up module 12 with system bus and is connected.The target erasure page address that auxiliary erasing module 31 sends for the erasing indicator signal and system bus receiving the transmission of NVM controller, erasing auxiliary signal is generated according to erasing indicator signal and target erasure page address, wherein, wipe auxiliary signal and comprise erasing indicator signal and target erasure page address; Buffer memory removes module 32 for according to the erasing indicator signal of carrying in erasing auxiliary signal, remove buffer unit corresponding with target erasure page address in buffer memory, particularly, buffer memory is removed module 32 and is searched buffer unit identical with target erasure page address in buffer memory according to erasing indicator signal, then remove the content of this buffer unit in buffer memory, make the content in buffer memory consistent with content in the NVM performed after erase operation like this.
Because generally have in the system of buffer memory, the function of buffer memory is the content of caching system bus access in the past, such as: data or instruction, when system bus next time visit again the content of identical address time, directly search this content in the buffer, do not need to access NVM, can the plenty of time be saved, improve system performance.When NVM carries out erase operation, because buffer memory does not know the specifying information needing erasing, so the content after the content in buffer memory and NVM can be caused to perform erase operation occurs inconsistent, therefore, in the present embodiment, generate erasing auxiliary signal by auxiliary erasing module 31 and send to buffer memory to remove module 32, the content making buffer memory remove buffer unit identical with target erasure page address in module 32 pairs of buffer memorys is removed, and ensure that the consistance of the content in buffer memory and the content of the NVM performed after erase operation.
Alternatively, in the present embodiment, system bus hang-up module 12 can also be removed module 32 to buffer memory and send the erase operation enabling signal that the target erasure page corresponding to target erasure page address carries out erase operation, and buffer memory is removed module 32 and this erase operation enabling signal is sent to NVM controller.Remove module 32 by buffer memory and erase operation enabling signal is sent to NVM controller, the object that the NVM controller control NVM pair target erasure page corresponding with target erasure page address carries out erase operation can be reached equally.
Alternatively, in the present embodiment, system bus recovery module 13 can also receive buffer memory and remove the erase operation settling signal of module 32 transmission and the operation settling signal of the content of buffer unit in removing buffer memory.Particularly, when NVM completes erase operation, NVM controller is removed module 32 to buffer memory and is sent erase operation settling signal, buffer memory is removed module 32 and erase operation settling signal can be sent to system bus to recover module 13, and the operation settling signal of the content removing buffer unit in buffer memory can send to system bus to recover module 13 by the module 32 of buffer memory removing simultaneously.So erase operation settling signal directly can send to system bus to recover module 13 by NVM controller, also can remove module 32 by buffer memory and send to system bus to recover module 13, make system bus revert to normal operating conditions from suspended state.
Alternatively, in the present embodiment, auxiliary erasing module 31 can also receive the erasing indicator signal that the module with bus interface sends, and wherein, the module with bus interface refers to can carry out with system bus the module that communicates.But this erasing indicator signal is first sent to the module with bus interface by NVM controller, then the module having bus interface by this is sent in auxiliary erasing module 31.Particularly, erasing indicator signal is sent to the module with bus interface by NVM controller, and erasing indicator signal is sent to auxiliary erasing module 31 by this module with bus interface under the control of system bus.No matter which kind of mode, erasing indicator signal is all provided by NVM controller, can arrive in auxiliary erasing module 31 via different modes.
Alternatively, in the present embodiment, buffer memory removes module 32 except removing the content of buffer unit corresponding with target erasure page address in buffer memory, the content of other buffer units in buffer memory can also be removed, be specifically as follows remove buffer memory comprise target erasure page interior several pages content or remove contents whole in buffer memory.Like this, while guaranteeing to make to remove the buffer unit content corresponding with the target erasure page address performing erase operation in NVM in buffer memory, can also remove by buffer memory the operation that module 32 realizes the content execution removing of non-targeted being wiped to buffer unit corresponding to page address.
Alternatively, in the present embodiment, buffer memory specifically can adopt mirror-image structure, can also adopt complete association structure or set associative structure.No matter buffer memory adopts any structure, all can realize the function of the content that caching system bus is accessed in the past.
As shown in Figure 4, be the workflow schematic diagram of an example of auxiliary erasing apparatus second embodiment of NVM of the present invention, in this example, connected by internal interface between NVM and NVM controller; Buffer memory is removed between module 32 and NVM and is carried out information transmission by NVM controller, wherein, NVM controller is used for removing according to buffer memory signal that module 32 sent by internal bus or the clock signal that NVM needs removes transmission of information between module 32 and NVM at buffer memory, and the specified register in NVM controller can assist certain operations, such as: aforesaid erasing enable bit is present in this special function register; Erase operation enabling signal is specially write operation.This example specifically can comprise the following steps:
Step 401, start to enter execution erase operation;
Target erasure page address is sent to NVM controller by step 402, set module 11, and set erasing enable bit;
Particularly, the target erasure page address that set module 11 receiving system bus sends and set indicator signal, send to NVM controller by target erasure page address, according to set indicator signal set erasing enable bit;
Erasing indicator signal operational module in step 403, NVM controller generates erasing indicator signal according to the erasing enable bit of set;
Step 404, system bus are hung up module 12 and are sent write operation order to buffer memory removing module 32, perform write operation, and make system bus be in suspended state to target erasure page;
By sending write operation order, in NVM controller actual think need perform erase operation, this write operation can cause system bus to be in suspended state, the execution and erase operation operation below gets clogged, until completing of erase operation, ensure that the dependence before and after data;
Step 405, auxiliary erasing module 31, according to the current state of target erasure page address and system bus and erasing indicator signal, generate erasing auxiliary signal;
Step 406, buffer memory are removed module 32 and are searched the buffer unit corresponding with target erasure page address in the buffer according to erasing auxiliary signal, and remove the content of this buffer unit;
Step 407, buffer memory are removed module 32 and are sent the control signal and data that perform write operation by internal bus to NVM controller;
In this step, system bus keeps suspended state, and namely system bus keeps waiting status, waits for that NVM performs completing of erase operation;
Step 408, NVM controller remove control signal and the data of the execution write operation that module 32 sends according to buffer memory, and simultaneously according to the erasing enable bit of set, control NVM starts to perform erase operation to target erasure page;
Why write operation herein can be performed as erase operation by NVM controller, because when performing write operation to NVM, need first to carry out erase operation and could perform write operation, so NVM can be made to start real erase operation by write operation herein;
Step 409, NVM controller wait for that NVM completes erase operation, continue to wait for if then perform step 410 otherwise return this step;
The erasing enable bit of set removed by step 410, NVM controller, removes module 32 send erase operation settling signal to buffer memory;
Step 411, buffer memory are removed module 32 and are sent to by erase operation settling signal system bus to recover module 13, send to system bus to recover module 13 settling signal of the content removing buffer unit simultaneously;
Step 412, system bus recover module 13 and are recovered from suspended state by system bus according to above-mentioned erase operation settling signal, continue to perform follow-up operation.
As shown in Figure 5, for the structural representation of NVM controller embodiment of the present invention, this NVM controller specifically can comprise: writing module 51, erasing module 52 and signal processing module 53, and erasing module 52 is connected with writing module 51, and signal processing module 53 is connected with erasing module 52.
In the present embodiment, the target erasure page address that writing module 51 sends for the auxiliary erasing apparatus receiving NVM, by target erasure page address write NVM controller, particularly, can by the special function register of target erasure page address write NVM controller; Erasing module 52 carries out the erase operation enabling signal of erase operation for the target erasure page corresponding to target erasure page address that the auxiliary erasing apparatus receiving NVM sends, according to erase operation enabling signal, erase operation is carried out to the target erasure page corresponding with target erasure page address; Signal processing module 53, for after erase operation terminates, is removed erasing enable bit, is generated erase operation settling signal, erase operation settling signal is sent to the auxiliary erasing apparatus of NVM.
As shown in Figure 6, be the specific works process schematic of NVM controller embodiment of the present invention, specifically can comprise the steps:
The target erasure page address that the auxiliary erasing apparatus that step 61, writing module 51 receive NVM sends, by target erasure page address write NVM controller;
Particularly, writing module 51 receives the target erasure page address that in the auxiliary erasing apparatus of NVM, set module 11 sends;
The target erasure page corresponding to target erasure page address that the auxiliary erasing apparatus that step 62, erasing module 52 receive NVM sends carries out the erase operation enabling signal of erase operation, according to erase operation enabling signal, erase operation is carried out to the target erasure page corresponding with target erasure page address;
Particularly, wipe module 52 to receive system bus in the auxiliary erasing apparatus of NVM and hang up the erase operation enabling signal that the target erasure page corresponding to target erasure page address that module 12 sends carries out erase operation;
Step 63, signal processing module 53, after erase operation terminates, are removed erasing enable bit, are generated erase operation settling signal, erase operation settling signal is sent to the auxiliary erasing apparatus of NVM.
In the present embodiment, the target erasure page address that the auxiliary erasing apparatus that writing module 51 receives NVM sends, by target erasure page address write NVM controller; The target erasure page corresponding to target erasure page address that the auxiliary erasing apparatus that erasing module 52 receives NVM sends carries out the erase operation enabling signal of erase operation, according to erase operation enabling signal, erase operation is carried out to the target erasure page corresponding with target erasure page address, now, system bus is hung up module 12 and is made system bus be in suspended state; Signal processing module 53 is after erase operation terminates, remove erasing enable bit, generate erase operation settling signal, erase operation settling signal is sent to the auxiliary erasing apparatus of NVM, the system bus in the auxiliary erasing apparatus of NVM recovers module 13, according to erase operation settling signal, system bus is reverted to normal operating conditions from suspended state.Like this, by the reciprocation of the auxiliary erasing apparatus of NVM controller and NVM, realize from the suspended state of system bus with from suspended state recovers to judge erase operation in this two states of normal operating conditions and the time of end, make system bus need not carry out constantly query manipulation again and judge the time that erase operation terminates, eliminate query manipulation, improve efficiency; And be in the process of suspended state at system bus, no longer perform erase operation operation below, ensure that the dependence between the data before and after erase operation, prevent the situation of the operating mistake due to the generation of data dependence problem.
Alternatively, then schematic diagram shown in Figure 5, NVM controller also comprises erasing indicator signal operational module 54, and writing module 51 is connected with erasing indicator signal operational module 54.Erasing indicator signal operational module 54 for generating erasing indicator signal according to the erasing enable bit after set, and sends erasing indicator signal to the auxiliary erasing apparatus of NVM.Particularly, erasing indicator signal operational module 54 assists the erasing enable bit of set module 11 set in erasing apparatus to generate erasing indicator signal according to NVM, and sends this erasing indicator signal to the auxiliary erasing module 31 in the auxiliary erasing apparatus of NVM.
As shown in Figure 7, for the structural representation of disposal system embodiment of the present invention, this system can comprise: the auxiliary erasing apparatus 72 of processor 71, NVM, NVM controller 73 and NVM 74, the auxiliary erasing apparatus 72 of NVM is connected by system bus with between processor 71, the auxiliary erasing apparatus 72 of NVM is connected by internal bus with between NVM controller 73, and NVM 74 and NVM control to be connected by internal interface between 73 devices.Wherein, the auxiliary erasing apparatus 72 of NVM can comprise the arbitrary module in the auxiliary erasing apparatus embodiment of aforementioned NVM, does not repeat them here; NVM controller 73 can comprise the arbitrary module in aforementioned NVM controller embodiment, does not repeat them here; Processor 71 is for the reading of instruction in completion system, decoding, transmitting and some executable operations, and to complete be the operation such as reading and process to data in system.
In the present embodiment, by sending erase operation enabling signal in the auxiliary erasing apparatus 72 of NVM, system bus is suspended, the NVM of NVM controller 73 control simultaneously 74 starts to perform erase operation, ensure that erase operation operation is not below performed, thus ensure that the dependence of data in system, and after NVM 74 executes erase operation, system bus just recovers normal operating conditions, so system can perform the beginning of erase operation and the time of end by accurate assurance NVM 74, make system bus or else be used in NVM 74 to perform in the process of erase operation and constantly inquire about, simplify operation, improve efficiency.
Alternatively, in the present embodiment, processor 71 is specifically as follows microcontroller (Micro ControlUnit, abbreviation: MCU).
Alternatively, in the present embodiment, the auxiliary erasing apparatus 72 of NVM can exist as an independent device, and can also be arranged in NVM controller 73, the auxiliary erasing apparatus 72 of NVM is communicated by internal bus with between NVM controller 73.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not depart from the spirit and scope of technical solution of the present invention.
Claims (10)
1. an auxiliary erasing apparatus of nonvolatile memory NVM, is characterized in that, comprising:
Set module, the target erasure page address sent for receiving system bus and set indicator signal, send to NVM controller by described target erasure page address, according to described set indicator signal set erasing enable bit;
Module hung up by system bus, for according to the erasing enable bit after set, send to described NVM controller the erase operation enabling signal that the target erasure page corresponding to described target erasure page address performs erase operation, and make described system bus be in suspended state;
System bus recovers module, for receiving the erase operation settling signal that described NVM controller sends after completing described erase operation, according to described erase operation settling signal, described system bus is reverted to normal operating conditions from described suspended state.
2. device according to claim 1, is characterized in that, the auxiliary erasing apparatus of described NVM is arranged in described NVM controller.
3. device according to claim 1, is characterized in that, also comprises:
Auxiliary erasing module, the target erasure page address that erasing indicator signal and described system bus for receiving the transmission of described NVM controller send, according to described erasing indicator signal and described target erasure page address, generates erasing auxiliary signal;
Buffer memory removes module, for according to the described erasing indicator signal of carrying in described erasing auxiliary signal, removes buffer unit corresponding with the described target erasure page address carried in described auxiliary erase signal in buffer memory.
4. a nonvolatile memory NVM controller, is characterized in that, comprising:
Writing module, the target erasure page address that the auxiliary erasing apparatus for receiving NVM sends, writes described NVM controller by described target erasure page address;
Erasing module, the target erasure page corresponding to described target erasure page address for the auxiliary erasing apparatus transmission receiving described NVM carries out the erase operation enabling signal of erase operation, according to described erase operation enabling signal, erase operation is carried out to the target erasure page corresponding with described target erasure page address;
Signal processing module, for after described erase operation terminates, removes erasing enable bit, generates erase operation settling signal, described erase operation settling signal is sent to the auxiliary erasing apparatus of described NVM.
5. NVM controller according to claim 4, is characterized in that, also comprise:
Erasing indicator signal operational module, for generating erasing indicator signal according to the erasing enable bit after set, and sends described erasing indicator signal to the auxiliary erasing apparatus of described NVM.
6. a disposal system, comprise the auxiliary erasing apparatus of the arbitrary described NVM of claim 1-3, processor, the arbitrary described NVM controller of claim 4-5 and NVM, the auxiliary erasing apparatus of described NVM is connected by system bus with between described processor, the auxiliary erasing apparatus of described NVM is connected by internal bus with between described NVM controller, is connected between described NVM with described NVM controller by internal interface.
7. an auxiliary method for deleting of nonvolatile memory NVM, is characterized in that, comprising:
The target erasure page address that receiving system bus sends and set indicator signal, send to NVM controller by described target erasure page address, according to described set indicator signal set erasing enable bit;
According to the erasing enable bit after set, send to described NVM controller the erase operation enabling signal that the target erasure page corresponding to described target erasure page address performs erase operation, and make described system bus be in suspended state;
Receive the erase operation settling signal that described NVM controller sends after completing described erase operation, according to described erase operation settling signal, described system bus is reverted to normal operating conditions from described suspended state.
8. method according to claim 7, is characterized in that, also comprises:
Receive the erasing indicator signal of described NVM controller transmission and the target erasure page address of described system bus transmission, according to described erasing indicator signal and described target erasure page address, generate erasing auxiliary signal;
According to the described erasing indicator signal of carrying in described erasing auxiliary signal, remove buffer unit corresponding with described target erasure page address in buffer memory.
9. a method of work for nonvolatile memory NVM controller, is characterized in that, comprising:
The target erasure page address that the auxiliary erasing apparatus receiving NVM sends, writes described target erasure page address in described NVM controller;
The target erasure page corresponding to described target erasure page address that the auxiliary erasing apparatus receiving described NVM sends carries out the erase operation enabling signal of erase operation, according to described erase operation enabling signal, erase operation is carried out to the target erasure page corresponding with described target erasure page address;
After described erase operation terminates, remove erasing enable bit, generate erase operation settling signal, described erase operation settling signal is sent to the auxiliary erasing apparatus of described NVM.
10. method of work according to claim 9, is characterized in that, also comprises:
Generate erasing indicator signal according to the erasing enable bit of the auxiliary erasing apparatus set of described NVM, and send described erasing indicator signal to the auxiliary erasing apparatus of described NVM.
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| CN201510399122.7A CN104978295A (en) | 2015-07-08 | 2015-07-08 | Auxiliary erasing apparatus and method for NVM |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1653547A (en) * | 2002-04-15 | 2005-08-10 | 索尼株式会社 | Recording/reproducing device and recording/reproducing method |
| CN1790549A (en) * | 2004-12-15 | 2006-06-21 | 富士通株式会社 | Semiconductor memory device |
| US20110258366A1 (en) * | 2010-04-19 | 2011-10-20 | Mosaid Technologies Incorporated | Status indication in a system having a plurality of memory devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1653547A (en) * | 2002-04-15 | 2005-08-10 | 索尼株式会社 | Recording/reproducing device and recording/reproducing method |
| CN1790549A (en) * | 2004-12-15 | 2006-06-21 | 富士通株式会社 | Semiconductor memory device |
| US20110258366A1 (en) * | 2010-04-19 | 2011-10-20 | Mosaid Technologies Incorporated | Status indication in a system having a plurality of memory devices |
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