CN104979187A - Method for dividing wafer - Google Patents
Method for dividing wafer Download PDFInfo
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- CN104979187A CN104979187A CN201410131256.6A CN201410131256A CN104979187A CN 104979187 A CN104979187 A CN 104979187A CN 201410131256 A CN201410131256 A CN 201410131256A CN 104979187 A CN104979187 A CN 104979187A
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- Prior art keywords
- wafer
- adhesive tape
- dividing method
- dielectric layer
- dividing
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 239000002390 adhesive tape Substances 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000005520 cutting process Methods 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- -1 polyethylene Polymers 0.000 claims description 4
- 239000004698 Polyethylene Substances 0.000 claims description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 claims description 3
- 229920002577 polybenzoxazole Polymers 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 229920000573 polyethylene Polymers 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 claims 29
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000011218 segmentation Effects 0.000 description 11
- 238000003698 laser cutting Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Dicing (AREA)
- Drying Of Semiconductors (AREA)
Abstract
A method for dividing a wafer comprises the steps of providing a wafer which comprises a plurality of chip areas and dividing channel areas between adjacent chips, and furthermore the wafer is provided with a dielectric layer; etching the dielectric layer on the dividing channel areas and partial thickness of wafer, and forming a plurality of grooves in the dielectric layer and the wafer; forming an adhesive tape layer on the dielectric layer, wherein the adhesive tape layer closes the openings of the grooves; and performing an expansion process for dividing the wafer into a plurality of chips along the dividing channel areas. According to the method for dividing the wafer, through combination of an etching process and the expansion process, wafer dividing can be realized on condition that the width of each dividing channel is relatively small, and furthermore a relatively high dividing speed and a relatively low dividing cost are obtained. Compared with a laser dividing process, the method has an advantage that about 28% of the manufacture cost is saved.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of dividing method of wafer.
Background technology
In semiconductor process, after wafer (wafer) upper formation integrated circuit, need wafer to be cut into some separate chip (chip) or crystal grain (die), then discrete chip (chip) or crystal grain (die) are encapsulated, form chip-packaging structure.
Blade cuts is traditional wafer cutting technique, utilizes cutting tool during blade cuts, along the Cutting Road on wafer, cuts from the back side of wafer, makes the chip one by one on wafer discrete, forms independently chip.
Along with the improving constantly of integrated level of device, the number of chips that single wafer is formed also gets more and more, the region of the Cutting Road between adjacent chips is also more and more narrow, particularly along with the width of Cutting Road is reduced to less than 80 microns, when adopting blade cuts to cut wafer, larger stress can be born near Cutting Road, easily cause and collapse limit and wafer breaks or the problem such as breakage.
For this problem, industry propose a kind of new cutting technique--laser ablation, laser ablation be with high-power Laser Focusing in crystal column surface, make wafer local temperature raise and decompose.The advantage of laser cutting is that cutting speed is fast, and not easily more crisp to quality wafer causes mechanical destruction.
But it is high that laser cutting exists cutting cost, and cutting mouth easily produces the problems such as hallrcuts.
Summary of the invention
The problem that the present invention solves is when Cutting Road width is less, reduces the cost of wafer cutting.
For solving the problem, the invention provides a kind of dividing method of wafer, comprising: providing wafer, described wafer comprises some chip areas and the Cutting Road region between adjacent chips, and described wafer has dielectric layer; Dielectric layer on etching Cutting Road region and the wafer of segment thickness, form some grooves in dielectric layer and wafer; Described dielectric layer forms adhesive tape layer, and described adhesive tape layer closes described groove opening; Carry out expansion process, described wafer is become some chips along Cutting Road regional split.
Optionally, the width in described Cutting Road region is 20 ~ 30 microns.
Optionally, the width of described groove is equal to or less than the width in Cutting Road region.
Optionally, the width of described groove is 20 ~ 30 microns.
Optionally, the sidewalls orthogonal of described groove is in the surface of wafer, and the degree of depth that described groove is arranged in wafer is 200 ~ 300 microns.
Optionally, the formation process of described groove is plasma etch process.
Optionally, the gas that the wafer of described plasma etching industrial etched portions thickness adopts is SF
6, C
4f
8, SF
6flow be 1300 ~ 1700sccm, C
4f
8flow be 500 ~ 700sccm, chamber temp 5 ~ 15 degrees Celsius, chamber pressure are 30 ~ 70mtorr, and source power is 2300 ~ 2700W, and bias power is 35 ~ 35W.
Optionally, described plasma etching industrial etches the gas CF that described dielectric layer adopts
4, CHF
3and O
2, CF
4, CHF
3and O
2flow be 500 ~ 1500sccm, chamber temp 5 ~ 15 degrees Celsius, chamber pressure are 30 ~ 70mtorr, and source power is 2300 ~ 2700W, and bias power is 40 ~ 100W.
Optionally, after described dielectric layer forms adhesive tape layer, also comprise, carry out thinning to the back side of wafer.
Optionally, the thickness between the back side of the wafer after thinning and channel bottom is 40 ~ 60 microns.
Optionally, the detailed process of described expansion process is: be placed in expansion chamber by described wafer, the back side of described wafer applies the pressure perpendicular to crystal column surface, applies outside pulling force at the edge of wafer, the wafer material of channel bottom is ruptured, forms some discrete chips.
Optionally, the thickness of described adhesive tape layer is 70 ~ 120 microns.
Optionally, described adhesive tape layer material is blue adhesive tape, epoxy resin adhesive tape, Kapton Tape, polyethylene tape, UV adhesive tape, benzocyclobutene adhesive tape or polybenzoxazoles adhesive tape.
Optionally, be formed with some semiconductor device in described chip area, have some interconnection structures in described dielectric layer, described interconnection structure is connected with semiconductor device, and described semiconductor device and interconnection structure form the integrated circuit in chip.
Compared with prior art, technical scheme of the present invention has the following advantages:
Cutting method of the present invention, provides wafer, and described wafer comprises some chip areas and the Cutting Road region between adjacent chips, and described wafer has dielectric layer; Dielectric layer on etching Cutting Road region and the wafer of segment thickness, form some grooves in dielectric layer and wafer; Described dielectric layer forms adhesive tape layer, and described adhesive tape layer closes described groove opening; Carry out expansion process, described wafer is become some chips along Cutting Road regional split.By the combination of etching technics and expansion process, can realize the segmentation of wafer when Cutting Road width is less, segmentation progress is higher, and the cost of segmentation is lower, is compared to the cost of manufacture that laser cutting parameter saves about 28%.
Further, thickness between the back side of the wafer after thinning and channel bottom is 40 ~ 60 microns, if the thickness between the back side of the wafer after thinning and channel bottom is too thin, follow-up carry out expansion process time, easily produce top rake defect (chipping) in bottom, affect the performance of chip and be unfavorable for follow-up encapsulation, if the thickness between the back side of the wafer after thinning and channel bottom is too thick, be unfavorable for that follow-up expansion technique is carried out, easily cause expansion process failure.
Accompanying drawing explanation
Fig. 1 ~ Fig. 7 is the structural representation of embodiment of the present invention wafer dividing method.
Embodiment
As background technology sayed, along with the reduction gradually of the width of Cutting Road, adopt blade cuts when cutting along Cutting Road, easily cause and collapse limit and wafer breaks or the problem such as breakage, and when adopting laser cutting, due to laser cutting device costly, make the cost of laser cutting higher.
For this reason, the present invention proposes a kind of dividing method of wafer, first etching technics is passed through, dielectric layer on etching Cutting Road and the part wafer material in Cutting Road region, groove is formed in dielectric layer and wafer, then on dielectric layer, form adhesive tape film, then use expansion process that wafer is split into some chips.Dividing method of the present invention, by the combination of etching technics and expansion process, can realize the segmentation of wafer when Cutting Road width is less, segmentation progress is higher, and the cost of segmentation is lower.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 1 ~ Fig. 7 is the structural representation of embodiment of the present invention wafer dividing method.
Please refer to Fig. 1 and Fig. 2, Fig. 2 is the cross-sectional view of Fig. 1 along line of cut AB direction, provides wafer 100, and described wafer 100 comprises some chip areas 11 and the Cutting Road region 12 between adjacent chips 11, and described wafer 100 has dielectric layer 101.It should be noted that, facilitate not shown dielectric layer in Fig. 1 in order to illustrated.
The material of described wafer 100 is silicon (Si), germanium (Ge) or SiGe (GeSi), carborundum (SiC); Also can be silicon-on-insulator (SOI), germanium on insulator (GOI); Or can also be other material, such as GaAs etc. III-V compounds of group.In this enforcement, the material of described wafer 100 is silicon, and the thickness of described wafer is 400 ~ 1000 microns.
Described wafer 100 is the carrier forming some chips, described wafer comprises some chip areas 11, chip area 11 is formed with integrated circuit, the corresponding chip of each chip area 11, some chip areas 11 are the distribution in ranks on wafer, be Cutting Road region 12 between chip area 11 and chip area 11, follow-up along wafer described in Cutting Road Region Segmentation, form some discrete chips.
Some semiconductor device are formed in described chip area 11, described semiconductor device can comprise passive device and active device (not shown), described active device can be MOS transistor, diode, triode, power transistor etc., described passive device can be resistance, electric capacity, inductance etc., form semiconductor device in the chip area 11 of wafer 100 after, wafer 100 is formed dielectric layer 101, some interconnection structure (not shown)s are formed in dielectric layer 101, described interconnection structure is connected with semiconductor device, described semiconductor device and interconnection structure form the integrated circuit in chip.
Described dielectric layer 101 can be multilayer lamination structure, forms interconnection structure and also can comprise more metal layers in corresponding dielectric layer 101, and by the conductive plunger of adjacent layer metal interconnection.The material of described dielectric layer 101 can be silica, silicon nitride, low-K material or ultra low-K material.
Described dielectric layer 101 can also form passivation layer (not shown), and described passivation layer is for the protection of the semiconductor device of beneath formation and interconnection structure, and the material of described passivation layer can be silicon nitride, high molecular polymer etc.
In the present embodiment, in order to improve the quantity of the chip that unit are is formed on wafer 100 and improve the integrated level of device, the width in described Cutting Road region 12 is 20 ~ 30 microns.
Please continue to refer to Fig. 2, dielectric layer 101 forms mask layer 103, have the opening 104 exposing dielectric layer surface in described mask layer 103, the position of described opening 104 is corresponding with the position in Cutting Road region 12.
The mask during wafer 100 of described mask layer 103 as subsequent etching dielectric layer 101 and segment thickness.
The material of described mask layer 103 can be photoresist, amorphous carbon, SiN, SiON, SiCN, SiC, TiN, TaN or BN etc.
Described mask layer 103 can be single or multiple lift stacked structure.When described mask layer 103 is multilayer lamination structure, in the particular embodiment, described mask layer 103 can be the double stacked structure of silicon oxide layer and photoresist layer, or the three level stack structure of silicon oxide layer, titanium nitride layer and photoresist layer.
In the present embodiment, described mask layer 103 is the photoresist layer of individual layer, in photoresist layer, opening 104 is formed by exposure and developing process, described opening 104 is positioned at directly over Cutting Road region 12, and width and the position of the width of described opening 104 and position and the groove formed in subsequent dielectric layers 101 and wafer 100 are corresponding.Adopt Other substrate materials as mask layer, after formation of the groove follow-up, described mask layer 103 can be removed by cineration technics, remove technique simple, when preventing from adopting wet etching or dry etching to remove mask material, the pattern of trenched side-wall is had an impact.
With reference to figure 3, with described mask layer 103 for mask, etch the wafer 100 of dielectric layer 101 on Cutting Road region 12 and segment thickness along opening 104, in dielectric layer 101 and wafer 100, form some grooves 105.
Etch described dielectric layer 101 and wafer 100 using plasma etching technics.
The gas that plasma etch process etches the employing of described dielectric layer 101 is CF
4, CHF
3and O
2, CF
4, CHF
3and O
2flow be 500 ~ 1500sccm, chamber temp 5 ~ 15 degrees Celsius, chamber pressure are 30 ~ 70mtorr, and source power is 2300 ~ 2700W, and bias power is 40 ~ 100W, make groove 105 width of formation comparatively accurate, and make the sidewalls orthogonal of the groove 105 of formation in the surface of wafer 100.
The gas that the wafer 100 of plasma etching industrial etched portions thickness adopts is SF
6, C
4f
8, SF
6flow be 1300 ~ 1700sccm, C
4f
8flow be 500 ~ 700sccm, chamber temp 5 ~ 15 degrees Celsius, chamber pressure are 30 ~ 70mtorr, and source power is 2300 ~ 2700W, and bias power is 35 ~ 35W, make groove 105 width of formation comparatively accurate, and make the sidewalls orthogonal of the groove 105 of formation in the surface of wafer 100.
Etch described dielectric layer 101 and segment thickness wafer 100 in same etching cavity, also can carry out in different etching cavities.In the present embodiment, etch described dielectric layer 101 and segment thickness wafer 100 carries out in same etching cavity.
In the embodiment of the present invention, can form the less groove of width 105 by plasma etch process, the Cutting Road region 12 making the width of groove 105 and width less is corresponding, is separated in adjacent chips region 11 by groove 105.The width W of described groove 105 can be equal to or less than the width in Cutting Road region 12, and the width of described groove 105 is 20 ~ 30 microns.
In the present embodiment, the degree of depth D being arranged in wafer 100 part of described groove 105 is 200 ~ 300 microns, reduces technology difficulty when forming groove 105, makes groove 105 keep preferably sidewall profile, is beneficial to the follow-up encapsulation to the chip after segmentation.In other embodiments of the present invention, the degree of depth being arranged in wafer part of described groove can be other numerical value.
With reference to figure 4, remove described mask layer 103(with reference to figure 3).
Remove described mask layer 103 and adopt cineration technics, the gas that described cineration technics adopts is oxygen, and temperature is 500 ~ 1200 degrees Celsius.
With reference to figure 5, described dielectric layer 101 forms adhesive tape layer 106.
Described adhesive tape layer 106 is directly pasted and is formed in dielectric layer 101 surface, described adhesive tape layer 106 is when follow-up expansion technique, some discrete chip after division is clung, prevent the distribution that the chip after dividing is at random, and prevent mutual shock or the dislocation of the chip in expansion process process after division.Described adhesive tape layer 106 can also adopt other technique to be formed in the surface of described dielectric layer 101.
The thickness of adhesive tape layer 106 is 70 ~ 120 microns, and the material of described adhesive tape layer 106 can be blue adhesive tape, epoxy resin adhesive tape, Kapton Tape, polyethylene tape, UV adhesive tape, benzocyclobutene adhesive tape or polybenzoxazoles adhesive tape.In the present embodiment, described adhesive tape layer 106 material is blue adhesive tape, and the adhesiveness of blue adhesive tape is better, and less expensive.
After formation adhesive tape layer, chemical mechanical milling tech can also be adopted to carry out thinning to the back side of wafer 100, subsequently through wafer 100 material bottom expansion process division groove 105, form discrete chip.If the thickness T between bottom the back side of the wafer after thinning 100 and groove 105 is too thin, follow-up carry out expansion process time, easily produce top rake defect (chipping) in bottom, affect the performance of chip and be unfavorable for follow-up encapsulation, if the thickness T between bottom the back side of the wafer after thinning 100 and groove 105 is too thick, be unfavorable for that follow-up expansion technique is carried out, easily cause expansion process failure, thus, in the embodiment of the present invention, the thickness T between bottom the back side of the wafer 100 after thinning and groove 105 is 40 ~ 60 microns.
With reference to figure 6 and Fig. 7, carry out expansion process, described wafer 100 is become some chips 109 along Cutting Road regional split.
Before carrying out expansion process, first wafer 100 is fixed in metal framework (not shown), then described wafer 100 is placed in expansion chamber, the back side of described wafer 100 applies the pressure 13 perpendicular to crystal column surface, outside pulling force 14 is applied at the edge of wafer 100, make wafer 100 Materials Fracture bottom groove 105, form some discrete chips 109.
The position that described pulling force 14 applies is positioned at top bottom groove 105 (vertical range bottom the position that pulling force 14 applies and groove 105 is 50 ~ 200 microns), and the pulling force 14 applied was around wafer frontside edge one week, described pressure 13 is evenly distributed in the back side of wafer 100, pulling force 14 and pressure 13 act on simultaneously and described wafer 100 are more easily divided along Cutting Road region, and make broken face keep smooth.
The cutting method of the embodiment of the present invention, by the combination of etching technics and expansion process, can realize the segmentation of wafer when Cutting Road width is less, segmentation progress is higher, and the cost of segmentation is lower, is compared to the cost of manufacture that laser cutting parameter saves about 28%.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. a dividing method for wafer, is characterized in that, comprising:
There is provided wafer, described wafer comprises some chip areas and the Cutting Road region between adjacent chips, and described wafer has dielectric layer;
Dielectric layer on etching Cutting Road region and the wafer of segment thickness, form some grooves in dielectric layer and wafer;
Described dielectric layer forms adhesive tape layer, and described adhesive tape layer closes described groove opening;
Carry out expansion process, described wafer is become some chips along Cutting Road regional split.
2. the dividing method of wafer as claimed in claim 1, it is characterized in that, the width in described Cutting Road region is 20 ~ 30 microns.
3. the dividing method of wafer as claimed in claim 1, it is characterized in that, the width of described groove is equal to or less than the width in Cutting Road region.
4. the dividing method of wafer as claimed in claim 2 or claim 3, it is characterized in that, the width of described groove is 20 ~ 30 microns.
5. the dividing method of wafer as claimed in claim 2, it is characterized in that, the sidewalls orthogonal of described groove is in the surface of wafer, and the degree of depth that described groove is arranged in wafer is 200 ~ 300 microns.
6. the dividing method of wafer as claimed in claim 5, it is characterized in that, the formation process of described groove is plasma etch process.
7. the dividing method of wafer as claimed in claim 6, is characterized in that, the gas that the wafer of described plasma etching industrial etched portions thickness adopts is SF
6, C
4f
8, SF
6flow be 1300 ~ 1700sccm, C
4f
8flow be 500 ~ 700sccm, chamber temp 5 ~ 15 degrees Celsius, chamber pressure are 30 ~ 70mtorr, and source power is 2300 ~ 2700W, and bias power is 35 ~ 35W.
8. the dividing method of wafer as claimed in claim 6, is characterized in that, described plasma etching industrial etches the gas CF that described dielectric layer adopts
4, CHF
3and O
2, CF
4, CHF
3and O
2flow be 500 ~ 1500sccm, chamber temp 5 ~ 15 degrees Celsius, chamber pressure are 30 ~ 70mtorr, and source power is 2300 ~ 2700W, and bias power is 40 ~ 100W.
9. the dividing method of wafer as claimed in claim 1, is characterized in that, after described dielectric layer forms adhesive tape layer, also comprise, carry out thinning to the back side of wafer.
10. the dividing method of wafer as claimed in claim 9, it is characterized in that, the thickness between the back side of the wafer after thinning and channel bottom is 40 ~ 60 microns.
The dividing method of 11. wafers as described in claim 1 or 10, it is characterized in that, the detailed process of described expansion process is: be placed in expansion chamber by described wafer, the back side of described wafer applies the pressure perpendicular to crystal column surface, outside pulling force is applied at the edge of wafer, the wafer material of channel bottom is ruptured, forms some discrete chips.
The dividing method of 12. wafers as claimed in claim 1, is characterized in that, the thickness of described adhesive tape layer is 70 ~ 120 microns.
The dividing method of 13. wafers as claimed in claim 1, is characterized in that, described adhesive tape layer material is blue adhesive tape, epoxy resin adhesive tape, Kapton Tape, polyethylene tape, UV adhesive tape, benzocyclobutene adhesive tape or polybenzoxazoles adhesive tape.
The dividing method of 14. wafers as claimed in claim 1, it is characterized in that, some semiconductor device are formed in described chip area, in described dielectric layer, there is some interconnection structures, described interconnection structure is connected with semiconductor device, and described semiconductor device and interconnection structure form the integrated circuit in chip.
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| CN201410131256.6A CN104979187A (en) | 2014-04-02 | 2014-04-02 | Method for dividing wafer |
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| CN201410131256.6A CN104979187A (en) | 2014-04-02 | 2014-04-02 | Method for dividing wafer |
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| CN107068617A (en) * | 2016-02-10 | 2017-08-18 | 台湾积体电路制造股份有限公司 | The method of semiconductor devices and its manufacture method and dividing semiconductor device |
| CN108257864A (en) * | 2018-01-12 | 2018-07-06 | 上海华虹宏力半导体制造有限公司 | Wafer processing method |
| CN108529554A (en) * | 2017-03-02 | 2018-09-14 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS device and preparation method thereof |
| CN108597982A (en) * | 2018-01-12 | 2018-09-28 | 上海华虹宏力半导体制造有限公司 | Wafer processing method |
| CN108615706A (en) * | 2018-07-04 | 2018-10-02 | 南通沃特光电科技有限公司 | A kind of wafer singualtion method |
| CN108609577A (en) * | 2016-12-12 | 2018-10-02 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of MEMS device |
| CN108701651A (en) * | 2016-03-03 | 2018-10-23 | 应用材料公司 | Hybrid Wafer Dicing Method Using Split Beam Laser Scribing Process and Plasma Etching Process |
| CN108899302A (en) * | 2018-07-04 | 2018-11-27 | 南通沃特光电科技有限公司 | A kind of back-illuminated type CMOS sensor singualtion method |
| CN109894725A (en) * | 2018-11-30 | 2019-06-18 | 全讯射频科技(无锡)有限公司 | A kind of technique that plasma cut realizes ultra-narrow Cutting Road |
| CN109979879A (en) * | 2019-03-29 | 2019-07-05 | 长江存储科技有限责任公司 | Manufacturing method for semiconductor chips |
| CN110265475A (en) * | 2019-06-24 | 2019-09-20 | 长江存储科技有限责任公司 | A kind of wafer and its manufacturing method, wafer dividing method |
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| CN114023846A (en) * | 2021-10-29 | 2022-02-08 | 浙江光特科技有限公司 | A method for reducing the dark current of indium phosphide-based detectors |
| CN114093926A (en) * | 2021-11-10 | 2022-02-25 | 长江存储科技有限责任公司 | Wafer, wafer preparation method and wafer cutting method |
| CN114695258A (en) * | 2022-04-02 | 2022-07-01 | 北京北方华创微电子装备有限公司 | Wafer dividing method |
| CN115295409A (en) * | 2022-07-20 | 2022-11-04 | 武汉光谷信息光电子创新中心有限公司 | Wafer scribing method |
| CN115939040A (en) * | 2022-12-22 | 2023-04-07 | 武汉新芯集成电路制造有限公司 | Wafer dicing system and wafer dicing method |
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Application publication date: 20151014 |