CN104979294B - A kind of manufacturing method of semiconductor devices - Google Patents
A kind of manufacturing method of semiconductor devices Download PDFInfo
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- CN104979294B CN104979294B CN201410142686.8A CN201410142686A CN104979294B CN 104979294 B CN104979294 B CN 104979294B CN 201410142686 A CN201410142686 A CN 201410142686A CN 104979294 B CN104979294 B CN 104979294B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 89
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 86
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 83
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 78
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 39
- 239000011856 silicon-based particle Substances 0.000 claims abstract description 14
- 238000005516 engineering process Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 60
- 239000000463 material Substances 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 17
- 230000000873 masking effect Effects 0.000 claims description 15
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000007789 gas Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 150000007529 inorganic bases Chemical class 0.000 claims description 6
- 150000007530 organic bases Chemical class 0.000 claims description 6
- 239000012495 reaction gas Substances 0.000 claims description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910005883 NiSi Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- -1 silicon nitrides Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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Abstract
The present invention provides a kind of manufacturing method of semiconductor devices, is related to technical field of semiconductors.The manufacturing method of semiconductor devices of the invention, by using the silicon nitride rich in nitrogen as the hard exposure mask of dummy grid and germanium silicon shielding layer and the interim side wall of germanium silicon, can be to avoid improper germanium silicon particle be formed on the surface of germanium silicon shielding layer, the interim side wall of germanium silicon and the hard exposure mask of dummy grid in germanium silicon technology, thus the yield of semiconductor devices obtained can be improved.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacturing method of semiconductor devices.
Background technique
In technical field of semiconductors, for advanced semiconductor technology, stress engineering becomes device performance and is promoted most
One of important factor.For PMOS, germanium silicon (SiGe) can improve carrier mobility by applying compression to channel
Rate.By adjusting the growth of germanium silicon well, stress can be optimized to stronger.
Germanium siliceous deposits is a kind of selective growth, is only grown on silicon (Si) material.In order to avoid germanium silicon is on NMOS
Growth needs to form germanium silicon shielding layer in NMOS area.Silicon nitride (SiN) and silica (SiO2) be used as covering
Layer；It is usually mainly (simple using silicon nitride since silica is removed easily and unstable in the wet processing of germanium silicon
Using silicon nitride, or simultaneously using silica and silicon nitride) it is used as shielding layer.HCl is widely used as the selection gas of germanium silicon growth
Body (selective gas) is to avoid in silicon nitride (SiN) and silica (SiO2) on grow germanium silicon.By adjusting HCl, germanium silicon
Selection window can be greatly improved.But HCl is unfavorable for the filling of germanium silicon and the quality of germanium silicon.Sometimes, due to
HCl reaches the limitation in region, unwanted germanium silicon particle often occurs in the technique for forming germanium silicon.In addition, some other originals
Cause, such as silicon particle, boron dose ratio or SiH4Gas ratio of/DCS etc., also results in the generation of germanium silicon particle.
In addition, the inventors of the present application found that the surface key (surface bound) of silicon nitride film is to generate germanium silicon
One most important reason of grain.The silicon nitride formed by ALD technique, CVD technique and furnace process (furnance) is equal
It may be used as hard exposure mask (HM) or germanium silicon shielding layer.Hard exposure mask (HM) or germanium silicon shielding layer are used as used by the prior art
Silicon nitride film in, for therein most of, dangle key (Si dangling on the surface of film there are many silicon
Bounds), as shown in Figure 1, these silicon pendency key is easy to the seed as nucleation and grows germanium silicon.It is outstanding in the silicon of film surface
Vertical key is more, and the selectivity of germanium silicon growth is poorer and germanium defect silicon is more serious.Therefore, in the prior art, after germanium silicon technology
Improper germanium silicon particle 101 often is formed on hard exposure mask and side wall (etched and formed by germanium silicon shielding layer), as shown in Figure 2.
These are located at the improper germanium silicon particle on hard exposure mask and side wall, will affect subsequent formation source-drain electrode, form metal silication
Object (NiSi) forms interlayer dielectric layer, removal dummy grid and the technique for forming contact hole, eventually leads to entire semiconductor devices
The yield of (such as SRAM) declines.
It can be seen that in the manufacturing method of existing semiconductor devices, due to as hard exposure mask or germanium silicon shielding layer
Often there are many silicon pendencys key (Si dangling bounds) in the surface of silicon nitride film, therefore in germanium silicon technology often
Improper germanium silicon particle is formed on hard exposure mask and side wall, eventually leads to the decline of the yield of semiconductor devices obtained.Cause
This, in order to solve the above problem, it is necessary to propose a kind of manufacturing method of new semiconductor devices.
Summary of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, comprising:
Step S101: provide semiconductor substrate, the NMOS area of the semiconductor substrate and the area PMOS be respectively formed including
The dummy gate structure of dummy grid and the hard exposure mask of dummy grid, wherein the material of the hard exposure mask of the dummy grid is the silicon nitride rich in nitrogen；
Step S102: forming the masking material bed of material for covering the semiconductor substrate and the hard exposure mask of the dummy grid, wherein
The material of the masking material bed of material is the silicon nitride rich in nitrogen；
Step S103: the masking material bed of material is performed etching to form the germanium silicon shielding layer of covering NMOS area and be located at
The interim side wall of germanium silicon of the dummy grid two sides of PMOS；
Step S104: it is formed in the semiconductor substrate positioned at the dummy grid two sides of PMOS for accommodating germanium silicon layer
Groove；
Step S105: germanium silicon layer is formed in the groove.
Optionally, the step S101 includes:
Step S1011: providing semiconductor substrate, forms polysilicon layer and disposed thereon hard on the semiconductor substrate
Mask layer, wherein the hardmask material is the silicon nitride layer rich in nitrogen；
Step S1012: the hardmask material is performed etching to form the hard exposure mask of dummy grid, passes through the dummy grid
Hard exposure mask performs etching to form dummy grid the polysilicon layer.
Optionally, the silicon nitride rich in nitrogen includes: CVD silicon nitride or PVD silicon nitride, and wherein CVD silicon nitride includes
Furnace process silicon nitride.
Optionally, the silicon nitride rich in nitrogen is the nitridation formed by the ratio for adjusting the reaction gas of CVD technique
Silicon.
Optionally, the silicon nitride rich in nitrogen is the silicon nitride formed by adjusting the target elements ratio of PVD process.
Optionally, in the step S104, the method for forming the groove includes dry etching and wet etching, and
The etching liquid that the wet etching uses includes inorganic base or organic base.
Optionally, the inorganic base includes KOH, NaOH, NH4At least one of OH.
Optionally, the organic base includes at least one of TMAH and EDP.
Optionally, further include step S1045 between the step S104 and the step S105:
Prerinse is carried out to the groove.
Optionally, the cleaning solution that the prerinse uses includes HF.
Optionally, in the step S105, the germanium silicon in situ used during forming the germanium silicon layer selects gas
Body includes at least one of HCl and HBr.
Optionally, after the step S105 further include:
Step S106: forming major side wall, forms source electrode and drain electrode, forms the metal silication being located above the source and drain electrodes
Object, and carry out stress and close on technical treatment；
Step S107: forming contact hole etching barrier layer and interlayer dielectric layer, remove the hard exposure mask of the dummy grid with it is described
Dummy grid simultaneously forms metal gates, forms contact hole.
The manufacturing method of semiconductor devices of the invention, by using rich in nitrogen silicon nitride as the hard exposure mask of dummy grid with
Germanium silicon shielding layer and the interim side wall of germanium silicon, can to avoid in germanium silicon technology germanium silicon shielding layer, the interim side wall of germanium silicon and
Improper germanium silicon particle is formed on the surface of the hard exposure mask of dummy grid, thus the yield of semiconductor devices obtained can be improved.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 is in the prior art as hard exposure mask or the schematic diagram of the surface texture of the silicon nitride film of germanium silicon shielding layer；
Fig. 2 is schematically cuing open for the structure of semiconductor devices prepared by the manufacturing method of semiconductor devices in the prior art
Face figure；
Fig. 3 is used by the embodiment of the present invention as hard exposure mask or the surface texture of the silicon nitride film of germanium silicon shielding layer
Schematic diagram；
Fig. 4 A to 4E is the figure that the committed step of the manufacturing method for the semiconductor devices that the embodiment of the present invention proposes is formed
Schematic cross sectional view；
Fig. 5 is a kind of flow chart of the manufacturing method for semiconductor devices that the embodiment of the present invention proposes.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram as desirable embodiment (and intermediate structure) of the invention
Bright embodiment.As a result, it is contemplated that from the variation of shown shape as caused by such as manufacturing technology and/or tolerance.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, being shown as the injection region of rectangle usually has round or bending features and/or implantation concentration ladder at its edge
Degree, rather than binary from injection region to non-injection regions changes.Equally, which can lead to by the disposal area that injection is formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
Due to the silicon pendency key (Si on the surface in the prior art as hard exposure mask or the silicon nitride film of germanium silicon shielding layer
Dangling bounds) be easy the seed in germanium silicon technology as nucleation, cause in germanium silicon technology often in hard exposure mask and
Improper germanium silicon particle is formed on side wall, eventually leads to the decline of the yield of semiconductor devices obtained, and therefore, the present invention is real
It applies example and reduces silicon pendency key by adjusting as the configuration of surface of hard exposure mask or the silicon nitride film of germanium silicon shielding layer, that is, use
Silicon nitride rich in nitrogen (N), so that mitigation even avoids in germanium silicon technology, formation germanium defect silicon is (non-on hard exposure mask and side wall
Normal germanium silicon particle), improve the yield of semiconductor devices obtained.Specifically, on the surface of the silicon nitride rich in nitrogen (N)
Rich in nitrogen pendency key, as shown in figure 3, and germanium silicon cannot (nitrogen dangles key cannot in the silicon nitride surface growth rich in nitrogen pendency key
The seed for being used as germanium silicon to be nucleated as silicon pendency key), therefore, improper germanium silicon growth will not occur on its surface.Accordingly
Ground, subsequent formation major side wall form source-drain electrode, form metal silicide (NiSi), form interlayer dielectric layer, removal dummy grid
And the technique of contact hole is formed, it will not be influenced by germanium defect silicon, the yield of final semiconductor devices obtained is incited somebody to action
To raising.
In the following, describing one example of manufacturing method of semiconductor devices proposed by the present invention referring to Fig. 4 A to 4E and Fig. 5
The detailed step of property method.Wherein, Fig. 4 A to 4E shows the key step of the manufacturing method of semiconductor devices proposed by the present invention
Suddenly the schematic cross sectional view of the figure formed；Fig. 5 is a kind of manufacturing method for semiconductor devices that the embodiment of the present invention proposes
Flow chart.
Step A1: semiconductor substrate 100 is provided, is respectively formed in the NMOS area of the semiconductor substrate 100 and the area PMOS
Dummy gate structure including dummy grid 101 and the hard exposure mask 102 of dummy grid, as shown in Figure 4 A.
Wherein, the material of the hard exposure mask 102 of dummy grid is the silicon nitride (SiN) rich in nitrogen (N), that is, is dangled rich in nitrogen on surface
The silicon nitride of key.The surface texture of the silicon nitride, as shown in Figure 3.In embodiments of the present invention, the silicon nitride rich in nitrogen refers to nitrogen
Content make the silicon nitride that content is high in the silicon nitride of the hard exposure mask 102 of dummy grid than in the prior art.Illustratively, it is rich in nitrogen
Silicon nitride refer to number of nitrogen atoms be more than silicon atom quantity silicon nitride.
It in the present embodiment, should can be with rich in the silicon nitride (SiN) of nitrogen (N) are as follows: CVD silicon nitride (including furnace process nitrogen
SiClx), PVD silicon nitride or other silicon nitrides.It further, can should be to pass through adjusting rich in the silicon nitride (SiN) of nitrogen (N)
The silicon nitride that the ratio (reaction gas ratio) of the reaction gas of CVD technique (including furnace process) is formed；It can be with
For the silicon nitride formed by the target elements ratio (target ratio) for adjusting PVD process.
Illustratively, the material of dummy grid 101 is polysilicon.
As an example, in the present embodiment, semiconductor substrate 100 selects single crystal silicon material to constitute.It is served as a contrast in the semiconductor
Shallow trench isolation is formed in bottom, semiconductor substrate is divided into the part NMOS and the part PMOS by the shallow trench isolation.Described half
Various traps (well) structure is also formed in conductor substrate 100, to put it more simply, being omitted in diagram.Above-mentioned formation trap
(well) structure, isolation structure, gate structure processing step be familiar with by those skilled in the art, herein no longer in detail
It is described.
Illustratively, step A1 is realized by following sub-step:
Step A11: providing semiconductor substrate 100, and polysilicon layer and disposed thereon is formed in the semiconductor substrate 100
Hardmask material, wherein the hardmask material be the silicon nitride layer rich in nitrogen (N)；
Step A12: performing etching the silicon nitride layer rich in nitrogen, forms the hard exposure mask 102 of dummy grid；It is covered firmly by dummy grid
Film 102 performs etching polysilicon layer, forms dummy grid 101.
In addition, can also include the steps that the step of forming clearance wall 103 and carrying out LDD processing in this step A1.
Step A2: it is formed and covers the semiconductor substrate 100, the hard exposure mask 102 of the dummy grid and the clearance wall 103
The masking material bed of material 1040, as shown in Figure 4 B.
Wherein, the material of the masking material bed of material 1040 is the silicon nitride (SiN) rich in nitrogen (N), that is, surface is rich in nitrogen pendency key
Silicon nitride.The surface texture of the silicon nitride, as shown in Figure 3.In embodiments of the present invention, the silicon nitride rich in nitrogen refers to nitrogen
Content makes the silicon nitride that content is high in the silicon nitride of the masking material bed of material 1040 than in the prior art.Illustratively, rich in nitrogen
Silicon nitride refers to that number of nitrogen atoms is more than the silicon nitride of silicon atom quantity.
It in the present embodiment, should can be with rich in the silicon nitride (SiN) of nitrogen (N) are as follows: CVD silicon nitride (including furnace process nitrogen
SiClx), PVD silicon nitride or other silicon nitrides.It further, can should be to pass through adjusting rich in the silicon nitride (SiN) of nitrogen (N)
The silicon nitride that the ratio (reaction gas ratio) of the reaction gas of CVD technique (including furnace process) is formed；It can be with
For the silicon nitride formed by the target elements ratio (target ratio) for adjusting PVD process.
Step A3: performing etching the masking material bed of material 1040, forms germanium silicon shielding layer (PSR) 104 and the position of covering NMOS
The interim side wall 1041 of germanium silicon in the dummy grid two sides of PMOS, as shown in Figure 4 C.
Step A4: it is formed in semiconductor substrate 100 positioned at 101 two sides of dummy grid of PMOS by etching for accommodating
The groove 105 of germanium silicon layer, as shown in Figure 4 D.
Wherein, the method for forming groove 105 can add dry etching for wet etching, dry etching or wet etching.Show
Example property, the method for forming groove 105 is first dry etching wet etching again.Wherein, the etching liquid that wet etching uses can be with
For inorganic base or organic base.The inorganic base that can be used includes KOH, NaOH, NH4At least one of OH etc..It can use
Organic base includes at least one of TMAH, EDP etc..
Illustratively, the shape of groove 105 can be ∑ type, bowl-shape or other suitable shapes.
Step A5: prerinse is carried out to groove 105；Then the deposit Germanium silicon layer 106 in groove 105, as shown in Figure 4 E.
Wherein, carrying out the cleaning solution that prerinse uses to groove 105 can be HF.Prewashed purpose includes removal groove
The oxide on surface.
During deposit Germanium silicon layer 106, the germanium silicon in situ selection gas that can be used includes HCl, HBr etc..
Wherein it is possible to reduce germanium silicon particle defect by the flow velocity for increasing HCl gas.But increase the stream of HCl gas
Speed is unfavorable for the filling (loading) of germanium silicon and the quality (quality) of germanium silicon.
In the present embodiment, since the hard exposure mask 102 of dummy grid and masking material bed of material 1040(are that is, germanium silicon shielding layer 104 and germanium
The interim side wall 1041 of silicon) it has been all made of the silicon nitride (SiN) rich in nitrogen (N), therefore, and during deposit Germanium silicon, Bu Hui
Improper germanium silicon particle is formed on the surface of germanium silicon shielding layer and the interim side wall of germanium silicon and the hard exposure mask of dummy grid, such as Fig. 4 E institute
Show.
So far, the introduction of the committed step of the manufacturing method of the semiconductor devices of the embodiment of the present invention is completed.In addition,
It can also include other steps after step A5.Illustratively, after step A5 further include:
Step A6: forming major side wall, forms source electrode and drain electrode, forms the metal silicide being located above the source and drain electrodes,
And it carries out stress and closes on technical treatment；
Step A7: forming contact hole etching barrier layer and interlayer dielectric layer, removes the hard exposure mask of dummy grid and dummy grid and shape
At metal gates, contact hole is formed.
The manufacturing method of the semiconductor devices of the embodiment of the present invention is made due to using the silicon nitride (SiN) rich in nitrogen (N)
For the hard exposure mask 102 of dummy grid and germanium silicon shielding layer 104 and the interim side wall 1041 of germanium silicon, it can thus be avoided in germanium silicon technology
In form improper germanium silicon particle on the surface of germanium silicon shielding layer and the interim side wall of germanium silicon and the hard exposure mask of dummy grid, can be with
Improve the yield of semiconductor devices obtained.
Referring to Fig. 5, one of the manufacturing method of semiconductor devices proposed by the present invention typical method is shown
Flow chart, for schematically illustrating the process of entire manufacturing process.
Step S101: provide semiconductor substrate, the NMOS area of the semiconductor substrate and the area PMOS be respectively formed including
The dummy gate structure of dummy grid and the hard exposure mask of dummy grid, wherein the material of the hard exposure mask of the dummy grid is the silicon nitride rich in nitrogen；
Step S102: forming the masking material bed of material for covering the semiconductor substrate and the hard exposure mask of the dummy grid, wherein
The material of the masking material bed of material is the silicon nitride rich in nitrogen；
Step S103: the masking material bed of material is performed etching to form the germanium silicon shielding layer of covering NMOS area and be located at
The interim side wall of germanium silicon of the dummy grid two sides of PMOS；
Step S104: it is formed in the semiconductor substrate positioned at the dummy grid two sides of PMOS for accommodating germanium silicon layer
Groove；
Step S105: germanium silicon layer is formed in the groove.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that the described method includes:
Step S101: semiconductor substrate is provided, is respectively formed in the NMOS area of the semiconductor substrate and the area PMOS including pseudo- grid
The dummy gate structure of pole and the hard exposure mask of dummy grid, wherein the material of the hard exposure mask of the dummy grid is the silicon nitride rich in nitrogen；
Step S102: forming the masking material bed of material for covering the semiconductor substrate and the hard exposure mask of the dummy grid, wherein described
The material of the masking material bed of material is the silicon nitride rich in nitrogen；
Step S103: the masking material bed of material is performed etching to form the germanium silicon shielding layer of covering NMOS area and be located at PMOS
Dummy grid two sides the interim side wall of germanium silicon；
Step S104: it is formed in the semiconductor substrate positioned at the dummy grid two sides of PMOS for accommodating the ditch of germanium silicon layer
Slot；
Step S105: in the groove formed germanium silicon layer, wherein the silicon nitride rich in nitrogen as the hard exposure mask of dummy grid with
The masking material bed of material can avoid in germanium silicon technology in the germanium silicon shielding layer and the interim side wall of germanium silicon and the hard exposure mask of dummy grid
Surface on form improper germanium silicon particle.
2. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that the step S101 includes:
Step S1011: providing semiconductor substrate, forms polysilicon layer and hard exposure mask disposed thereon on the semiconductor substrate
Material layer, wherein the hardmask material is the silicon nitride layer rich in nitrogen；
Step S1012: the hardmask material is performed etching to form the hard exposure mask of dummy grid, is covered firmly by the dummy grid
Film performs etching to form dummy grid the polysilicon layer.
3. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that the silicon nitride packet rich in nitrogen
It includes: CVD silicon nitride or PVD silicon nitride, wherein the CVD silicon nitride includes furnace process silicon nitride.
4. the manufacturing method of semiconductor devices as claimed in claim 3, which is characterized in that the silicon nitride rich in nitrogen is logical
Overregulate the silicon nitride that the ratio of the reaction gas of CVD technique is formed.
5. the manufacturing method of semiconductor devices as claimed in claim 3, which is characterized in that the silicon nitride rich in nitrogen is logical
Overregulate the silicon nitride that the target elements ratio of PVD process is formed.
6. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that in the step S104, formed
The method of the groove includes dry etching and wet etching, and the etching liquid that uses of the wet etching include inorganic base or
Organic base.
7. the manufacturing method of semiconductor devices as claimed in claim 6, which is characterized in that the inorganic base include KOH,
NaOH、NH4At least one of OH.
8. the manufacturing method of semiconductor devices as claimed in claim 6, which is characterized in that the organic base include TMAH and
At least one of EDP.
9. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that in the step S104 and the step
Further include step S1045 between rapid S105:
Prerinse is carried out to the groove.
10. the manufacturing method of semiconductor devices as claimed in claim 9, which is characterized in that the cleaning that the prerinse uses
Liquid includes HF.
11. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that in the step S105, in shape
The germanium silicon in situ selection gas used during at the germanium silicon layer includes at least one of HCl and HBr.
12. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that after the step S105 also
Include:
Step S106: forming major side wall, forms source electrode and drain electrode, forms the metal silicide being located above the source and drain electrodes, and
It carries out stress and closes on technical treatment；
Step S107: forming contact hole etching barrier layer and interlayer dielectric layer, removes the hard exposure mask of the dummy grid and the pseudo- grid
Pole simultaneously forms metal gates, forms contact hole.
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| CN2731717Y (en) * | 2003-03-31 | 2005-10-05 | 台湾积体电路制造股份有限公司 | CMOS assembly |
| CN101167165A (en) * | 2005-05-26 | 2008-04-23 | 应用材料股份有限公司 | Method for increasing compressive stress of PECVD silicon nitride film |
| CN101461044A (en) * | 2006-06-05 | 2009-06-17 | 朗姆研究公司 | Residue free hardmask trim |
| CN103681500A (en) * | 2012-09-12 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN103681496A (en) * | 2012-09-04 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Production method for semiconductor device |
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| US20070278541A1 (en) * | 2006-06-05 | 2007-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacer engineering on CMOS devices |
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| CN2731717Y (en) * | 2003-03-31 | 2005-10-05 | 台湾积体电路制造股份有限公司 | CMOS assembly |
| CN101167165A (en) * | 2005-05-26 | 2008-04-23 | 应用材料股份有限公司 | Method for increasing compressive stress of PECVD silicon nitride film |
| CN101461044A (en) * | 2006-06-05 | 2009-06-17 | 朗姆研究公司 | Residue free hardmask trim |
| CN103681496A (en) * | 2012-09-04 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Production method for semiconductor device |
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