CN105097577B - A kind of method that the grid of transistor is identified for LVS verification - Google Patents
A kind of method that the grid of transistor is identified for LVS verification Download PDFInfo
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- CN105097577B CN105097577B CN201410167023.1A CN201410167023A CN105097577B CN 105097577 B CN105097577 B CN 105097577B CN 201410167023 A CN201410167023 A CN 201410167023A CN 105097577 B CN105097577 B CN 105097577B
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Abstract
The present invention provides a kind of method that the grid of transistor is identified for LVS verification, is related to technical field of integrated circuits.This method includes：Step S101：It is FINSD by the region recognition overlapping with fin structure layer but not overlapping with grid layer of the active layer in domain, is GATE0 by the region recognition overlapping with active layer and fin structure layer of grid layer in domain；Step S102：The left and right sides in the GATE0 is identified as GATE1 with the FINSD parts being in contact；Step S103：It is GATEr by the region recognition formed after bearing of trend extension preset distances of the GATE1 along grid layer, wherein the half of spacing of the preset distance between two adjacent fin structure layers.This method can realize the automatic identification to transistor gate, therefore, there is no need to the mark layer that the hand drawn in domain is used to identify transistor gate, can improve design efficiency.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of grid to transistor for LVS verification
The method that pole is identified.
Background technology
In technical field of integrated circuits, due to there is high saturation current and save design area, fin field
Effect transistor (FinFET) becomes to become more and more popular in the design and manufacture of integrated circuit.
During IC design is carried out, generally require to perform design verification to the domain of design, wherein designing
Checking includes design rule verification (DRC), layout than schematic diagram (Layout Versus Schematics, LVS) checking etc..Its
In, it is necessary to which the part such as grid of transistor is identified in domain during LVS verification.
With the development of technology, increasing design limiting factor needs to be considered when carrying out IC design,
And for the IC design using FinFET, having a basic requirement is needed on fin structure (Fin) side
Pseudo- fin structure (dummy Fin) 101 ' is formed outside edge, as shown in Figure 1.Wherein, Fig. 1 is of the prior art a kind of integrated
The domain of circuit, including fin structure (Fin) layer 101, grid layer (GT) 102, active layer (AA) 103, in addition to it is located at fin
The pseudo- fin structure layer 101 ' at the edge of structure (Fin) layer 101.Due to the presence of pseudo- fin structure layer 101 ', will cause entering
During row LVS verification, it is difficult to identify the grid of transistor.And correctly identify that the grid of transistor is most important for LVS verification, because
This, a kind of current way be in IC design, drawn out in domain mark layer (marker layer) for
Identify the grid of transistor.
However, the method for identifying the mark layer of the grid of transistor should be used for by hand drawn in domain, increase is integrated
The complexity of circuit design, and reduce design efficiency.Therefore, it is necessary to propose it is a kind of it is new be used for LVS verification to transistor
The method that is identified of grid.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of grid to transistor for LVS verification and is identified
Method, it is convenient to omit in domain hand drawn be used for identify transistor the mark layer of grid the step of, improve domain set
The efficiency of meter.
The embodiment of the present invention provides a kind of method that the grid of transistor is identified for LVS verification, the side
Method includes：
Step S101：Active layer in domain is overlapping with fin structure layer but region recognition not overlapping with grid layer is
FINSD, it is GATE0 by the region recognition overlapping with active layer and fin structure layer of grid layer in domain；
Step S102：The left and right sides in the GATE0 is identified as GATE1 with the FINSD parts being in contact；
Step S103：The region recognition that will be formed after bearing of trend extension preset distances of the GATE1 along grid layer
For GATEr, wherein the half of spacing of the preset distance between two adjacent fin structure layers.
Alternatively, in the step S101, identify FINSD the step of with identify GATE0 the step of carry out simultaneously.
Alternatively, the step of in the step S101, first carrying out the step of identifying FINSD, then performing identification GATE0.
Alternatively, the step of in the step S101, first carrying out the step of identifying GATE0, then performing identification FINSD.
Alternatively, step S104 is also included after the step S103：
It is grid by the grid layer in domain and the equitant region recognition of active layer.
Alternatively, step S105 is also included after the step S104：
It is GATEd by the region recognition in grid in addition to the GATEr.
Alternatively, in the step S101, in addition to the grid layer in domain and the equitant region of active layer known
Not Wei grid the step of.
Alternatively, the grid to transistor, which is identified in targeted domain, does not include being used to identify the crystal
The mark layer of the grid of pipe.
Alternatively, in the step S103, by bearing of trend extension preset distances of the GATE1 along grid layer by such as
Lower rule is carried out：
When the GATE1 is all covered with active layer in the both sides of the bearing of trend along grid layer, by the GATE1 along grid
The bearing of trend of pole layer respectively extends the preset distance to both sides simultaneously；
When the GATE1 only in the side of the bearing of trend along grid layer covered with active layer when, by the GATE1 along grid
The bearing of trend of pole layer extends the preset distance to the side covered with active layer.
The method that the grid of transistor is identified for LVS verification of the present invention, it is possible to achieve to transistor gate
The automatic identification of pole, therefore, it is no longer necessary to which hand drawn is used for the mark layer for identifying transistor gate in domain, can improve
The design efficiency of integrated circuit.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 is a kind of domain of integrated circuit of the prior art；
Fig. 2 is a kind of domain of integrated circuit of the embodiment of the present invention；
Fig. 3 is a kind of stream of the method that the grid of transistor is identified for LVS verification of the embodiment of the present invention
Cheng Tu.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this
Invention can also have other embodiment.
The present embodiments relate to technical field of integrated circuits, there is provided a kind of grid to transistor for LVS verification
The method being identified, this method are no longer needed by automatically extracting identification of layout (layout) realization to the grid of transistor
To be used for the mark layer for identifying transistor gate by hand drawn in domain, therefore the design efficiency of integrated circuit can be improved.
Below, reference picture 2 and Fig. 3 are carried out to describe the grid to transistor for being used for LVS verification of the embodiment of the present invention
Know method for distinguishing.Wherein, Fig. 2 is a kind of domain of integrated circuit of the present embodiment；Fig. 3 is used for LVS for the embodiment of the present invention
A kind of flow chart of the method that the grid of transistor is identified of checking.
As shown in Figure 2, the domain of the integrated circuit includes：It is fin structure layer (Fin) 101, grid layer (GT) 102, active
Layer (AA) 103, wherein, grid layer (GT) 102 includes the grid (GATEr) 1021 and other grids (GATEd) of transistor
1022。
Exemplarily, the method that the grid of transistor is identified for LVS verification of the embodiment of the present invention, by such as
Lower rule is carried out：
A. FINSD is determined, wherein, FINSD is that active layer 103 and fin structure layer 101 overlap folded region in domain
In the not region overlapping with grid layer 102.
That is, by active layer in domain 103 and 101 equitant region of fin structure layer not with grid layer 102
Overlapping region recognition is FINSD.
Wherein, FINSD logical expression is as follows:
FINSD=(AA and FIN) NOT GT.
B. GATE0 is determined, wherein, GATE0 is grid layer 102, active layer 103, the three's phase of fin structure layer 101 in domain
Overlapping region.
That is, grid layer in domain 102, active layer 103, the equitant region of the three of fin structure layer 101 are known
Wei not GATE0.
Wherein, GATE0 logical expression is as follows:
GATE0=(GT and AA) and FIN.
C. GATE1 is determined, wherein, GATE1 is the GATE0 that the left and right sides is in contact with FINSD in domain.
That is, the GATE0 that the left and right sides is in contact with FINSD in domain is identified as GATE1.
It can be seen that GATE1 is the part for having in GATE0 ad-hoc location requirement.
D. the grid (GATEr) 1021 of transistor is determined, wherein, the grid (GATEr) 1021 of transistor is in domain
What the region that GATE1 is formed after bearing of trend (that is, the longitudinal direction in Fig. 2) the extension preset distance along grid layer 102 was formed
Region, wherein the half of spacing of the preset distance between two adjacent fin structure layers.
That is, it is by the region recognition formed after bearing of trend extension preset distances of the GATE1 along grid layer
GATEr, wherein, the half of spacing of the preset distance between two adjacent fin structure layers.
Specifically, in the present embodiment, when the GATE1 be all covered with the both sides of the bearing of trend along grid layer it is active
During layer, bearing of trends of the GATE1 along grid layer is respectively extended in Fig. 2 not up and down to both sides () simultaneously described predetermined
Distance；When the GATE1 only in the side of the bearing of trend along grid layer covered with active layer when, by the GATE1 along grid
The bearing of trend of layer extends the preset distance to the side covered with active layer.
E. other grids (GATEd) 1022 are determined, wherein, other grids (GATEd) 1022 are the grid in domain
(GATE) region in addition to the grid (GATEr) 1021 of transistor, and grid (GATE) is grid layer 102 and active layer
103 equitant regions.
That is, it is grid (GATE) by grid layer 102 and 103 equitant region recognition of active layer, by grid
(GATE) region recognition in addition to the grid (GATEr) 1021 of transistor is GATEd.
Wherein, GATEd logical expression is as follows:
GATEd=GATE NOT GATEr.
The grid of transistor is identified by the method for the present embodiment, the requirement of LVS verification can be fully met.
In above-mentioned rule, A and B can be carried out simultaneously, can also one in front and one in back be carried out, specific sequencing is not defined.
It can be seen that the method that the grid of transistor is identified for LVS verification of the present embodiment, can be by automatic
Extraction layout (layout) realizes the identification to transistor gate, it is no longer necessary to which hand drawn is used to identify transistor in domain
The mark layer of grid, therefore the design efficiency of integrated circuit can be improved.Certainly, for the domain of mark layer, this implementation be present
The method of example the grid of transistor can also be identified automatically according to above-mentioned rule, for LVS verification.
Wherein, Fig. 3 illustrates the one of the method that the grid of transistor is identified for LVS verification of the present embodiment
Kind typical process, including：
Step S101：Active layer in domain is overlapping with fin structure layer but region recognition not overlapping with grid layer is
FINSD, it is GATE0 by the region recognition overlapping with active layer and fin structure layer of grid layer in domain；
Step S102：The left and right sides in the GATE0 is identified as GATE1 with the FINSD parts being in contact；
Step S103：The region recognition that will be formed after bearing of trend extension preset distances of the GATE1 along grid layer
For GATEr, wherein the half of spacing of the preset distance between two adjacent fin structure layers.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (8)
- A kind of 1. method that the grid of transistor is identified for LVS verification, it is characterised in that methods described includes：Step S101：Active layer in domain is overlapping with fin structure layer but region recognition not overlapping with grid layer is FINSD, it is GATE0 by the region recognition overlapping with active layer and fin structure layer of grid layer in domain；Step S102：The left and right sides in the GATE0 is identified as GATE1 with the FINSD parts being in contact；Step S103：It is crystalline substance by the region recognition formed after bearing of trend extension preset distances of the GATE1 along grid layer The grid G ATEr of body pipe, wherein the half of spacing of the preset distance between two adjacent fin structure layers, its In, when the GATE1 is all covered with active layer in the both sides of the bearing of trend along grid layer, by the GATE1 along grid layer Bearing of trend simultaneously respectively extend the preset distance to both sides；When the GATE1 is only one of the bearing of trend along grid layer It is when side is covered with active layer, bearing of trends of the GATE1 along grid layer is described pre- to the side extension covered with active layer Set a distance.
- 2. it is used for the method that the grid of transistor is identified of LVS verification as claimed in claim 1, it is characterised in that In the step S101, identify FINSD the step of with identify GATE0 the step of carry out simultaneously.
- 3. it is used for the method that the grid of transistor is identified of LVS verification as claimed in claim 1, it is characterised in that The step of in the step S101, first carrying out the step of identifying FINSD, then performing identification GATE0.
- 4. it is used for the method that the grid of transistor is identified of LVS verification as claimed in claim 1, it is characterised in that The step of in the step S101, first carrying out the step of identifying GATE0, then performing identification FINSD.
- 5. it is used for the method that the grid of transistor is identified of LVS verification as claimed in claim 1, it is characterised in that Also include step S104 after the step S103：It is grid by the grid layer in domain and the equitant region recognition of active layer.
- 6. it is used for the method that the grid of transistor is identified of LVS verification as claimed in claim 5, it is characterised in that Also include step S105 after the step S104：It is GATEd by the region recognition in grid in addition to the GATEr.
- 7. it is used for the method that the grid of transistor is identified of LVS verification as claimed in claim 1, it is characterised in that In the step S101, in addition to the step of be grid by the grid layer in domain and the equitant region recognition of active layer.
- 8. it is used for the method that the grid of transistor is identified of LVS verification as claimed in claim 1, it is characterised in that The mark for not including being used to identify the grid of the transistor in targeted domain is identified in the grid to transistor Layer.
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| CN111008511A (en) * | 2019-11-25 | 2020-04-14 | 上海华力微电子有限公司 | Fin type transistor layout parameter extraction calculation method and extraction calculation system thereof |
| WO2022110114A1 (en) * | 2020-11-30 | 2022-06-02 | 华为技术有限公司 | Circuit layout identification method and identification device |
| CN114692561B (en) * | 2020-12-30 | 2025-07-25 | 杭州广立微电子股份有限公司 | Method for discriminating devices in current leakage loop |
| CN113283291B (en) * | 2021-04-13 | 2022-09-06 | 杭州广立微电子股份有限公司 | Recognition method of Finger transistors in layout |
| CN113286444A (en) * | 2021-05-20 | 2021-08-20 | 浪潮电子信息产业股份有限公司 | PCB impedance control method, device, equipment and readable storage medium |
| CN113392617B (en) * | 2021-07-12 | 2022-04-19 | 长鑫存储技术有限公司 | Semiconductor integrated circuit design method and device |
| CN116207153A (en) * | 2023-02-27 | 2023-06-02 | 上海华力集成电路制造有限公司 | Metal oxide semiconductor field effect transistor layout structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7139990B2 (en) * | 2004-03-23 | 2006-11-21 | International Business Machines Corporation | Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction |
| CN103310030A (en) * | 2012-03-08 | 2013-09-18 | 台湾积体电路制造股份有限公司 | Lvs implementation for finfet design |
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| US7175942B2 (en) * | 2004-02-05 | 2007-02-13 | International Business Machines Corporation | Method of conflict avoidance in fabrication of gate-shrink alternating phase shifting masks |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7139990B2 (en) * | 2004-03-23 | 2006-11-21 | International Business Machines Corporation | Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction |
| CN103310030A (en) * | 2012-03-08 | 2013-09-18 | 台湾积体电路制造股份有限公司 | Lvs implementation for finfet design |
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