CN105097656B - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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Abstract
The present invention provides a kind of production method of semiconductor devices, the described method includes：Semiconductor substrate is provided, formed with the first metal interconnecting layer in the Semiconductor substrate, in the semiconductor substrate surface formed with interlayer dielectric layer；The opening for being used for forming the second metal interconnecting layer is formed in the interlayer dielectric layer, the open bottom is located on first metal interconnecting layer；Side wall and bottom deposit in the interlayer dielectric layer surface and the opening form amorphous si-layer；The amorphous si-layer is heat-treated, to form the metal silicide layer on the surface that first metal interconnecting layer exposes；The amorphous si-layer and the metal silicide layer are handled using nitrogen or ammonia, to form dielectric liner layer and metal cap layer；In the opening and the interlayer dielectric layer forming metal layer on surface.The method according to the invention provides relatively low line resistance and good electric migration performance for device, improves the reliability of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technology
Since semiconductor integrated circuit comes out, integrated circuit technique development is swift and violent, integrates first device on the same chip
Number of packages amount has increased millions of till now from initial tens, hundreds of.In order to reach complexity and current densities
It is required that the manufacture craft of semiconductor integrated circuit chip utilizes batch processing technology, various types of complexity are formed on substrate
Device, and interconnected with complete electric function, to use the dielectric layer between low k layer between the conductors mostly at present
As the dielectric material for isolating each metal interconnecting, interconnection structure is used to provide between device on the ic chip and whole encapsulation
Wiring.In the art, the device of such as field-effect transistor (FET), Ran Hou are initially formed in semiconductor substrate surface
Interconnection structure is formed in BEOL (IC manufacturing back-end process).Reduce the RC retardation ratio of interconnection line, improve the side such as electromigration
Face, metallic copper has low-resistance coefficient, high-melting-point and excellent electromigration immunity compared with metallic aluminium, in higher current density
It can also be used with conditions of low-power.At present, the interconnection structure being made of dielectric layer between metallic copper and low k layer has metal
Interconnection line layer number is few, the advantage such as chip speed is high, low in energy consumption, manufacture low, highly resistance electric migration performance of cost.
With the development of large scale integrated circuit technology, the diminution of characteristic size, packaging density and working frequency it is continuous
Improve, the sectional area of interconnection line and line spacing continue to decline on chip, cause the increase of interconnection resistance, and then influence RC retardation ratio
Performance.The previous relatively effective method of line resistance that reduces of mesh is to reduce the thickness of diffusion impervious layer, and if diffusion impervious layer
The effective blocking capability to a certain extent, just lost to copper diffusion is thinned, therefore is highly desirable to study a kind of with high
The material of Step Coverage ability and high diffusivity blocking capability, to stop diffusion of the copper into dielectric layer.
Therefore, in order to solve the above-mentioned technical problem, it is necessary to propose a kind of new production method.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features, do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problem of presently, there are, the embodiment of the present invention one proposes a kind of production method of semiconductor devices, including：
Semiconductor substrate is provided, formed with the first metal interconnecting layer in the Semiconductor substrate, is served as a contrast in the semiconductor
Basal surface is formed with interlayer dielectric layer；The opening for being used for forming the second metal interconnecting layer, institute are formed in the interlayer dielectric layer
Open bottom is stated to be located on first metal interconnecting layer；Side wall in the interlayer dielectric layer surface and the opening and
Bottom deposit forms amorphous si-layer；The amorphous si-layer is heat-treated, is interconnected with being formed positioned at first metal
The metal silicide layer on surface that layer exposes；The amorphous si-layer and the metal silication are handled using nitrogen or ammonia
Nitride layer, to form dielectric liner layer and metal cap layer；In the opening and the interlayer dielectric layer surface forms metal
Layer.
Further, the surface that first metal interconnecting layer exposes has depression.
Further, the metal silicide is CuSi.
Further, the metal cap layer is CuSiN.
Further, the material of the dielectric liner layer is SiN.
Further, the heat treatment temperature is 300~400 DEG C.
Further, the thickness of the amorphous si-layer is 30~60 angstroms, is formed using atomic layer deposition method described amorphous
Silicon layer.
Further, the material of first metal interconnecting layer and the metal layer is metallic copper, using the side of electrochemical plating
Method forms the metal layer.
Further, the dual-damascene structure shape that the through hole and groove that the opening is formed for dual damascene process form
Opening.
Further, it is additionally included in before the metal layer is formed on the dielectric liner layer and metal cap layer and forms gold
The step of belonging to barrier layer.
Further, after the metal layer is formed, the step of performing chemical mechanical grinding is further included, to form described second
Metal interconnecting layer.
The embodiment of the present invention two provides a kind of semiconductor devices, including：Semiconductor substrate；In the Semiconductor substrate
The first metal interconnecting layer；Interlayer dielectric layer on the semiconductor substrate surface；In the interlayer dielectric layer
Second metal interconnecting layer；The dielectric liner layer being formed between the interlayer dielectric layer and second metal interconnecting layer；Formed
Metal cap layer between second metal interconnecting layer and first metal interconnecting layer.
Further, the bottom of second metal interconnecting layer is embedded in first metal interconnecting layer.
Further, the material of the dielectric liner layer is SiN.
Further, the metal cap layer is CuSiN.
Further, it is also formed with metal barrier on the dielectric liner layer and the metal cap layer.
The embodiment of the present invention three provides a kind of electronic device, it includes the semiconductor devices described in embodiment two.
In conclusion production method provides relatively low line resistance and good electromigration for device according to the present invention
Can, and then improve the reliability and yield of device.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A -1F by implemented successively according to the step of embodiment of the present invention one acquisition device diagrammatic cross-section；
Fig. 2 is the flow chart according to the step of method is implemented successively in the embodiment of the present invention one；
Fig. 3 is the schematic cross sectional view according to semiconductor devices in the embodiment of the present invention two；
Fig. 4 is the schematic cross sectional view according to three electronic device of the embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then there is no element or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part are described with term first, second, third, etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to further include to make
With the different orientation with the device in operation.For example, if the device upset in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions
Outside, the present invention can also have other embodiment.
Embodiment one
Below in conjunction with the accompanying drawings to the present invention one specifically embodiment be described further.
First, as shown in Figure 1A, there is provided Semiconductor substrate 100, the Semiconductor substrate is interior to be interconnected formed with the first metal
Layer 101, etching stop layer 102 and interlayer dielectric layer 103 are sequentially formed with 100 surface of Semiconductor substrate.Described
The opening 104 for being used for forming the second metal interconnecting layer is formed in interlayer dielectric layer 103, the open bottom is located at first gold medal
Belong on interconnection layer 101.
Semiconductor substrate 100 may include any semi-conducting material, this semi-conducting material may include but be not limited to：Si、SiC、
SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V or group Ⅱ-Ⅵ compound semiconductor.Semiconductor substrate
100 include various isolation structures, such as shallow trench isolation.Semiconductor substrate 100 can also include organic semiconductor or such as Si/
The layered semiconductor of SiGe (SGOI) on SiGe, silicon-on-insulator (SOI) or insulator.Semiconductor substrate 100 has further included
First metal interconnecting layer 101.Metal interconnecting layer can be to have one layer or multilayer in the Semiconductor substrate 100, for simplicity,
The first metal interconnecting layer 101 is merely illustrated herein.As an example, first metal interconnecting layer is copper metal interconnection layer.
Deposition forms etching stop layer 102 on a semiconductor substrate 100, the material of etching stop layer 102 may be selected from SiCN,
SiC or SiN, while its etching stop layer as subsequent etching interlayer dielectric layer 103, can prevent in metal interconnecting layer
Metal is diffused into the interlayer dielectric layer where front-end devices.
Then, deposition forms interlayer dielectric layer 103 on etching stop layer 102, wherein, the interlayer dielectric layer 103
Material, can be low k dielectric (formation for low k dielectric), or ultra low k dielectric materials (formation for ultralow k
Dielectric layer).In general, low k dielectric refers to the dielectric material that dielectric constant (k values) is less than 4, ultra low k dielectric materials are
Refer to the dielectric material that dielectric constant (k values) is less than 2.Generally use chemical gaseous phase spin coating proceeding (SOG), whirl coating technology or chemical gas
Prepared by phase deposition technique, its material can be silica glass (FSG), silica (silicon oxide), carbonaceous material, hole
Material (porous-like material) or homologue.As an example, interlayer dielectric layer 103 is ultralow-k material film.
The opening 104 for being used for forming the second metal interconnecting layer, the opening 104 are formed in the interlayer dielectric layer 103
Bottom is located on first metal interconnecting layer 101, that is, the surface for 104 exposure first metal interconnecting layers that are open.Alternatively,
The surface that first metal interconnecting layer exposes has depression.As an example, the opening 104 is dual damascene process
The opening of the dual-damascene structure shape of through hole and the groove composition of formation.The step of forming the opening 104 includes：It is situated between in interlayer
Cushion and hard mask layer are sequentially formed in electric layer 103, the effect of cushion is the second metal interconnection formed in follow-up grinding
Mechanical stress is avoided to cause to damage to the porous structure of interlayer dielectric layer 103 during layer；The first opening is formed in hard mask layer,
To expose the cushion of lower section, first opening is used as the pattern of the groove in second metal interconnection structure；Buffering
The second opening is formed in layer and interlayer dielectric layer 103, second opening is used as the through hole in second metal interconnection structure
Pattern；Using hard mask layer as mask, synchronous etch buffer layers and interlayer dielectric layer 103, to be formed in interlayer dielectric layer 103
For forming the opening 104 of the second metal interconnection structure, i.e., the synchronous groove formed in second metal interconnection structure and lead to
Hole, described be etched in when exposing etching stop layer 102 terminate；The etching stop layer 102 exposed by the opening 104 is removed,
So that the second metal interconnection structure is connected with the first metal interconnecting layer, while it can ensure that the bottom of opening 104 is located at the first metal
On interconnection layer 101.In the present embodiment, the removal of etching stop layer 102 is implemented using dry method etch technology.Alternatively, may be used also
Further to be performed etching to the first metal interconnecting layer 101, depression is formed on the surface of the first metal interconnecting layer, so that described open
The bottom of mouth 104 is embedded in first metal interconnecting layer 101.It is noted that the bottom of opening 104 can be embedded in
It in first metal interconnecting layer 101, can also be only located on 101 surface of the first metal interconnecting layer, but must assure that and first
Metal interconnecting layer 101 is in contact.
The technical process of the above-mentioned formation copper interconnection structure is only one kind in dual damascene process, art technology
Personnel should know, the copper-connection knot can be equally formed using the other embodiment in dual damascene process
Structure, such as be initially formed the throughhole portions of the copper interconnection structure and re-form the trench portions of the copper interconnection structure, herein no longer
Repeat its detailed implementation steps.
Then, as shown in Figure 1B, sink in the side wall and bottom of 103 surface of interlayer dielectric layer and the opening 104
Product forms amorphous si-layer 105.
The formation process of the amorphous si-layer 105 can use any technology well known to those skilled in the art, such as
Atomic layer deposition, low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition technique.As one
Example, the amorphous si-layer 105 is formed using atomic layer deposition method.Alternatively, the thickness of the amorphous si-layer 105 is 30
~60 angstroms.
Then, as shown in Figure 1 C, the amorphous si-layer 105 is heat-treated, so that mutual positioned at first metal
The even copper metal reaction in amorphous si-layer the first metal interconnecting layer in contact in layer 101, generates metal silicide
106.The metal silicide is CuSi.As an example, heat treatment temperature is 300~400 DEG C.
Then, as shown in figure iD, the amorphous si-layer 105 and the metal silicide are handled using nitrogen or ammonia
Layer 106, to form dielectric liner layer 108 and metal cap layer 107.
The material of the dielectric liner layer 108 is silicon nitride, and 107 material of metal cap layer is CuSiN.Use nitrogen
Either the corona treatment amorphous si-layer 105 of ammonia and 106 nitrogen of metal silicide layer or ammonia pass through plasma
Decompose, nitrogen-atoms and the amorphous silicon and CuSi reactions generation silicon nitride and CuSiN of generation.As an example, ammonia is passed through
Flow be 50 cc/mins (sccm)~150 cc/min (sccm), used by the plasma decomposition
Power is 100W~200W.Silicon atom in CuSiN metal cap layers 107 can make device have longer electromigration lifetime,
Be conducive to improve electromigration characteristic, and resistivity is maintained in preferable scope.
Next, in 104 interior and described 103 forming metal layer on surface 109 of interlayer dielectric layer that are open.The metal
Layer material be copper metal, formed metal layer 109 method can use those skilled in the art be familiar with it is various suitably
Technology, such as physical gas-phase deposition or electrochemical plating technique.As an example, electrochemical plating technique shape is selected
Into metal copper layer.
Formed before metal layer 109, gold need to be sequentially formed on the dielectric liner layer 108 and metal cap layer 107
Belong to barrier layer and copper metal Seed Layer, to put it more simply, being not shown in figure.Metal barrier can be prevented in copper metal interconnection layer
Diffusion of the copper into interlayer dielectric layer, copper metal Seed Layer can strengthen attached between copper metal interconnection layer and metal barrier
The property.Formation metal barrier and copper metal Seed Layer can use the various suitable techniques that those skilled in the art be familiar with
Technology, for example, forming metal barrier using physical gas-phase deposition or chemical vapor deposition, alternatively, selects chemistry
Vapour deposition process deposits to form the relatively thin metal barrier of thickness ratio.In addition, sputtering technology or chemical vapor deposition can be used
Technique forms copper metal Seed Layer.One or more of the material of metal barrier in the metals such as Ta or Ti.Due to
Dielectric liner layer 108 has been formd in before the step of, therefore has formed relatively thin metal barrier herein.Dielectric liner layer
Effective barrier effect can be played to copper diffusion jointly with metal barrier.
Then, chemical mechanical milling tech is performed, until exposing interlayer dielectric layer 103.In the process, hard mask layer and
Cushion is removed, while the dielectric liner layer on 103 surface of interlayer dielectric layer is also removed, and only retains the second metal
Dielectric in interconnection structure sinks laying.It can be come in this step using flattening method conventional in field of semiconductor manufacture
Realize the planarization on surface.The non-limiting examples of the flattening method include mechanical planarization method and chemically mechanical polishing is flat
Smoothization method.Chemically mechanical polishing flattening method is more often used.
The above method forms metal cap layer between adjacent metal interconnection layer, while forms in metal interconnection structure
Dielectric liner layer and metal barrier composition composite diffusion barrier layer, this composite diffusion barrier layer to copper diffusion has played
The barrier effect of effect, relatively low line resistance and good electric migration performance are provided for device, and then improve the reliable of device
Property and yield.
With reference to Fig. 2, the process flow chart for making copper interconnection structure according to one embodiment of the present invention is shown, for letter
The flow of whole manufacturing process is shown.
In step 201, there is provided Semiconductor substrate, formed with the first metal interconnecting layer in Semiconductor substrate, is partly leading
Body substrate surface is formed with interlayer dielectric layer；
In step 202, the opening for being used for forming the second metal interconnecting layer, the open bottom are formed in interlayer dielectric layer
Portion is located on the first metal interconnecting layer；
In step 203, the side wall in interlayer dielectric layer surface and opening and bottom deposit form amorphous si-layer；
In step 204, amorphous si-layer is heat-treated, to be formed positioned at the surface that the first metal interconnecting layer exposes
On metal silicide layer；
In step 205, using nitrogen or ammonia processing amorphous si-layer and metal silicide layer, to form dielectric lining
Bed course and metal cap layer；
In step 206, metal barrier is formed on dielectric liner layer and metal cap layer；
In step 207, in opening and interlayer dielectric layer forming metal layer on surface；
In a step 208, the step of performing chemical mechanical grinding, to form the second metal interconnecting layer.
Embodiment two
The embodiment of the present invention provides a kind of semiconductor devices, its structure is as shown in figure 3, including Semiconductor substrate 300；It is located at
The first metal interconnecting layer 301 in the Semiconductor substrate 300.
The etching stop layer 302 and interlayer dielectric layer 303 being sequentially located on the semiconductor substrate surface are further included, its
In, the material of the interlayer dielectric layer 303, can be low k dielectric (formation for low k dielectric), or ultralow k
Dielectric material (formation for ultra-low-k dielectric layer).
The second metal interconnecting layer 306 in the etching stop layer 302 and interlayer dielectric layer 303 is further included, it is optional
Ground, the bottom of second metal interconnecting layer 306 are embedded in first metal interconnecting layer 301.It is described as an example
The material of first metal interconnecting layer and second metal interconnecting layer is metallic copper.
Further include and be formed in the etching stop layer 302, the interlayer dielectric layer 303 and second metal interconnecting layer
Dielectric liner layer 305 between 306, alternatively, the material of the dielectric liner layer 305 is SiN.
Further include the metal cover being formed between second metal interconnecting layer 306 and first metal interconnecting layer 301
Cap layers 304.As an example, second metal interconnecting layer is embedded in bottom in first metal interconnecting layer by metal
Cap 304 is wrapped up.Alternatively, the material of the metal cap layer 304 is CuSiN.
In addition, being also formed with metal barrier on the dielectric liner layer 305 and the metal cap layer 304, it is
Simplification, not shown in figure.One or more of the material of metal barrier in the metals such as Ta or Ti.
In conclusion device architecture according to embodiments of the present invention, the metal nut cap between adjacent metal interconnection layer
Layer, and dielectric liner layer and the composite diffusion barrier layer structure of metal barrier composition in metal interconnection structure, it is this multiple
Close diffusion impervious layer and effective barrier effect is played to copper diffusion, relatively low line resistance and good electromigration are provided for device
Performance, and then improve the reliability and yield of device.
Embodiment three
The embodiment of the present invention provides a kind of electronic device 400, it includes：Semiconductor devices 401 described in embodiment two.
Due to including semiconductor devices have higher yield and reliability, the electronic device equally have it is above-mentioned excellent
Point.
The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment or have
The intermediate products of above-mentioned semiconductor device, such as：Cell phone mainboard with the integrated circuit etc..
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (17)
1. a kind of production method of semiconductor devices, the described method includes：
Semiconductor substrate is provided, formed with the first metal interconnecting layer in the Semiconductor substrate, in the Semiconductor substrate table
Face is formed with interlayer dielectric layer；
The opening for being used for forming the second metal interconnecting layer is formed in the interlayer dielectric layer, the open bottom is positioned at described the
On one metal interconnecting layer；
Side wall and bottom deposit in the interlayer dielectric layer surface and the opening form amorphous si-layer；
The amorphous si-layer is heat-treated, to form the metal on the surface that first metal interconnecting layer exposes
Silicide layer；
The amorphous si-layer and the metal silicide layer are handled using nitrogen or ammonia, to form dielectric liner layer and gold
Belong to cap；
In the opening and the interlayer dielectric layer forming metal layer on surface.
2. according to the method described in claim 1, it is characterized in that, the surface exposed of first metal interconnecting layer have it is recessed
Fall into.
3. according to the method described in claim 1, it is characterized in that, the metal silicide is CuSi.
4. according to the method described in claim 1, it is characterized in that, the metal cap layer is CuSiN.
5. according to the method described in claim 1, it is characterized in that, the material of the dielectric liner layer is SiN.
6. according to the method described in claim 1, it is characterized in that, the heat treatment temperature is 300~400 DEG C.
7. according to the method described in claim 1, it is characterized in that, the thickness of the amorphous si-layer be 30~60 angstroms, use
Atomic layer deposition method forms the amorphous si-layer.
8. the according to the method described in claim 1, it is characterized in that, material of first metal interconnecting layer and the metal layer
For metallic copper, the metal layer is formed using the method for electrochemical plating.
9. according to the method described in claim 1, it is characterized in that, it is described opening for dual damascene process formed through hole and
The opening of the dual-damascene structure shape of groove composition.
10. according to the method described in claim 1, it is characterized in that, it is additionally included in the dielectric before the metal layer is formed
The step of metal barrier is formed on laying and metal cap layer.
11. according to the method described in claim 1, it is characterized in that, after the metal layer is formed, the chemical machine of execution is further included
The step of tool is ground, to form second metal interconnecting layer.
12. the semiconductor devices that a kind of method using described in one of 1 to 11 prepares, including：
Semiconductor substrate；The first metal interconnecting layer in the Semiconductor substrate；On the semiconductor substrate surface
Interlayer dielectric layer；The second metal interconnecting layer in the interlayer dielectric layer；It is formed in the interlayer dielectric layer and described
Dielectric liner layer between second metal interconnecting layer；Be formed in second metal interconnecting layer and first metal interconnecting layer it
Between metal cap layer.
13. device according to claim 12, it is characterised in that the bottom of second metal interconnecting layer is embedded in described
In first metal interconnecting layer.
14. device according to claim 12, it is characterised in that the material of the dielectric liner layer is SiN.
15. device according to claim 12, it is characterised in that the metal cap layer is CuSiN.
16. device according to claim 12, it is characterised in that the dielectric liner layer and the metal cap layer it
On be also formed with metal barrier.
17. a kind of electronic device, it includes the semiconductor devices any one of claim 12-16.
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| CN1575515A (en) * | 2001-03-27 | 2005-02-02 | 先进微装置公司 | Damascene processing using dielectric barrier films |
| CN101427361A (en) * | 2006-02-28 | 2009-05-06 | St微电子(克偌林斯2)股份有限公司 | Metal interconnects in a dielectric material |
| CN101483172A (en) * | 2008-01-07 | 2009-07-15 | 国际商业机器公司 | Semiconductor structure and its production method |
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