CN105187037A - Pulse width modulation system control method and its error action preventing circuit - Google Patents

Abstract

The invention discloses a control method of a pulse width modulation system and a false action preventing circuit thereof, the pulse width modulation system comprises a microprocessor, a buffer circuit and a false action preventing circuit, the false action preventing circuit is connected between a first output end of the microprocessor and a starting end of the buffer circuit by a power supply, the buffer circuit is provided with an output control end, and the control method comprises the following steps: sequentially providing a first working voltage and a second working voltage to the microprocessor; (b) the microprocessor receives a second working voltage, and in the process that the second working voltage rises to a required voltage quasi-position from zero, an output voltage is established at the first output end corresponding to the establishment of the second working voltage; (c) the malfunction preventing circuit replaces the output voltage with the enabling level voltage and outputs the enabling level voltage to the starting end; and (d) making the output control terminal be high impedance output according to the enabling level voltage of the starting terminal.

Description

Pulse Width Modulation System Control Method and Malfunction Prevention Circuit

technical field

The present invention relates to a control method of a pulse width modulation system, especially a control method of a pulse width modulation system capable of preventing the abnormality of the subsequent circuit in the voltage stage required by the microprocessor to establish its own internal modules and its malfunction prevention circuit.

Background technique

The Pulse Width Modulation (PWM) system has been widely used in various electronic devices, such as motors, to control the operation of the electronic devices. When the traditional pulse width modulation system controls the operation of the subsequent circuit, it must first establish the corresponding working voltage for the corresponding modules inside the microprocessor when the microprocessor establishes the voltage stage required by each module in the microprocessor, and establishes During the process, the output terminals of the pulse width modulation system must maintain the enable level voltage (high level voltage) to protect the subsequent circuit from malfunctioning. When the received voltage of each module has been established , the pulse width modulation system can output the disable level voltage (low level voltage) to drive the subsequent stage circuit to start to operate.

Referring to FIG. 1 , it is a schematic diagram of a circuit architecture of a traditional pulse width modulation system. As shown in FIG. 1 , a conventional pulse width modulation system 1 includes a microprocessor 11 and a buffer circuit 12, wherein the microprocessor 11 includes a plurality of input terminals 111, a plurality of output terminals 112, a first module 113 and a second module 114 . The multiple input terminals 111 of the microprocessor 11 respectively receive different working voltages, such as the first working voltage V ₁ and the second working voltage V ₂ , which are respectively supplied to the first module 113 and the second module 114 inside the microprocessor 11. Use, wherein the first working voltage V ₁ is used by the first module 113 such as the analog/digital conversion module, the second working voltage V ₂ is used by the second module 114 such as the input/output status module, and a plurality of output terminals 112 are used in the second The module 114 outputs a voltage ΔV correspondingly when receiving the second working voltage V ₂ . The buffer circuit 12 has an input terminal 121, a starting terminal 122, an output control terminal 123 and a power supply terminal 124, wherein the input terminal 121 and the starting terminal 122 are connected to the corresponding output terminal 112 of the microprocessor 11, and receive the output of the microprocessor 11 The output voltage ΔV outputted from the terminal 112 , the power supply terminal 124 receives the first working voltage V ₁ , so that the buffer circuit 12 can operate with the first working voltage V ₁ . The buffer circuit 12 judges whether the voltage level of the voltage received by the input terminal 121 and the starting terminal 122 is equal to or less than a voltage judgment value set by the buffer circuit 12 to determine the voltage of the voltage received by the input terminal 121 and the starting terminal 122 The magnitude of the level corresponds to the output state of the control output control terminal 123 , such as high level voltage, low level voltage or high impedance output.

Referring to FIG. 1 together with FIG. 2A , FIG. 2B , FIG. 2C and FIG. 2D , wherein FIG. 2A , FIG. 2B , FIG. 2C and FIG. 2D are timing diagrams of various internal voltages of a conventional pulse width modulation system. When the traditional pulse width modulation system 1 starts to operate, the actions of the first module 113 and the second module 114 of the microprocessor 11 actually have timing requirements, that is, the first module 113 and the second module 114 operate sequentially, so The multiple input terminals 111 of the microprocessor 11 receive the first operating voltage V ₁ and the second operating voltage V ₂ in sequence, wherein the first operating voltage V ₁ and the second operating voltage V ₂ are supplied to the microprocessor 11 , respectively rising from 0V to the required voltage level, when the _first operating voltage V1 and the _second operating voltage V2 respectively reach the required voltage level to complete the establishment of the voltage, the first module inside the microprocessor 11 113 and the second module 114 can operate normally respectively.

When the pulse width modulation system 1 starts to operate and the microprocessor 11 is in the stage of establishing the voltage of the first module 113 and the second module 114, first, as shown in FIG. 2A , at the initial time point (t ₀ ), the microprocessor 11 An input terminal 111 of the device 11 starts to receive the first working voltage V ₁ . Then, at the first time point (t ₁ ), the voltage level of the first operating voltage V ₁ climbs from 0V at the initial time point (t ₀ ) to a first specific voltage level V _1s , for example, 4.5V. At this time, another input terminal 111 of the microprocessor 11 starts to receive the second working voltage V ₂ . After that, from the first time point (t ₁ ) to the second time point (t ₂ ), the voltage level of the first working voltage V ₁ has reached the required voltage level and the voltage establishment is completed, for example, 5V, so the first A module 113 starts to operate, and at the same time, the voltage level of the second operating voltage V ₂ climbs from 0V at the first time point (t ₁ ) to a second specific voltage level V _2s , for example, 2V. Finally, at the third time point (t ₃ ), the voltage level of the second operating voltage V ₂ has reached the required voltage level to complete the voltage establishment, such as 3.3V, so the second module 114 also starts to operate.

Since the output voltage ΔV of the multiple output terminals 112 of the microprocessor 11 is established corresponding to the _second operating voltage V2 used as the second module 114 (input/output status module), and the voltage levels of the two are also Correspondence is accompanied by changes, so the output voltage ΔV is actually equal to the voltage value of the _second operating voltage V2, and in the process of receiving the _second operating voltage V2 by the second module 114 of the microprocessor 11, that is, as shown in Figure 2B As shown, when the input terminal 111 of the microprocessor 11 starts to receive the second operating voltage V ₂ at the first time point (t ₁ ), the output voltage ΔV of the output terminal 112 of the microprocessor 11 correspondingly starts to build up, And the output voltage ΔV of the output terminal 112 of the microprocessor 11 changes along with the voltage level of the _second operating voltage V2, that is, the output voltage ΔV of the output terminal 112 of the microprocessor 11 corresponds to the second operating voltage V ₂ climbs from 0V at the first time point (t ₁ ) to the second specific voltage level V _2s at the second time point (t ₂ ), such as 2V, and reaches it at the third time point (t ₃ ). The same voltage level as the second working voltage V ₂ , for example, 3.3V.

In addition, when the second module 114 of the microprocessor 11 receives the _second operating voltage V2, as shown in FIG. The output voltage ΔV is output, so the input voltage of the input terminal 121 and the starting terminal 122 of the buffer circuit 12 corresponds to the output voltage ΔV output by the output terminal 112 of the microprocessor 11, that is, corresponds to the second operating voltage V ₂ .

However, when the second module 114 of the microprocessor 11 receives the _second operating voltage V2 and starts to establish the voltage level of the _second operating voltage V2, and the microprocessor 11 provides the output voltage Δ V (that is, the second working voltage V ₂ ) starts to build up, that is, the microprocessor 11 starts to build up the output voltage ΔV at the first time point (t ₁ ) and climbs from 0V at the first time point (t 1 ) to the first time point (t ₁ ). When the second specific voltage level V _2s at the second time point (t ₁ ) reaches the same voltage level as the second operating voltage V ₂ at the third time point (t ₃ ), the buffer circuit 12 will The output voltage ΔV received by the input terminal 121 and the enabling terminal 122 correspondingly causes the output control terminal 123 to generate an enabling level voltage (high level voltage) or a disabling level voltage (low level voltage). When the output voltage △V of the microprocessor 11 climbs from 0V at the first time point (t ₁ ) to the third time point (t ₃ ) to reach the required voltage level and complete the voltage establishment, the output voltage △ During the rising period of V, since the output voltage ΔV of the microprocessor 11 may be lower than the voltage judgment value set by the buffer circuit 12, for example, as shown in FIG. 2A, when the output voltage ΔV of the microprocessor 11 has not yet reached the second When the specific voltage level V _2s is less than the voltage judgment value set by the buffer circuit 12, the buffer circuit 12 recognizes that its input terminal 121 and the starting terminal 122 are both disabled level voltages (low level voltages), so the buffer circuit 12 is convenient The output control terminal 123 generates a disabling level voltage V _L (low level voltage), that is, the output control terminal 123 of the buffer circuit 12 will generate a disabling level voltage V _L during the first period T ₁ , as shown in FIG. 2D , In this way, the pulse width modulation system 1 will output the disabled level voltage V _L when establishing the required voltage stages of the first module 113 and the second module 114, which will cause the subsequent circuit 14 to operate abnormally, causing the subsequent circuit 14 to have Risk of damage exists.

Contents of the invention

A brief overview of the invention is given below in order to provide a basic understanding of some aspects of the invention. It should be understood that this summary is not an exhaustive overview of the invention. It is not intended to identify key or critical parts of the invention nor to delineate the scope of the invention. Its purpose is merely to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

The invention solves the problem that the output state of the traditional pulse width modulation system is outputting the disabled level voltage (low level voltage) when the microprocessor establishes the voltage stage required by each module, which causes the abnormality of the subsequent stage circuit.

The purpose of the present invention is to provide a pulse width modulation system control method and its malfunction prevention circuit. When the microprocessor is sequentially establishing the voltage required by each internal module, the malfunction prevention circuit of the pulse width modulation system Continuously output the enable level voltage to the start-up end of the buffer circuit, so that the output end of the buffer circuit is a high-impedance output. In this way, it can avoid the need for the subsequent circuit in the microprocessor to sequentially build internal modules. Abnormal action occurs during the voltage process, thereby protecting the subsequent stage circuit, to solve the problem that the traditional pulse width modulation system establishes the required voltage stage of each module, and the output terminal disables the level voltage (low level voltage) to the subsequent stage circuit. Defects that cause abnormal operation of the subsequent stage circuit and are easily damaged.

According to the idea of the present invention, the present invention provides a control method for a pulse width modulation system, wherein the pulse width modulation system is connected to the power supply of the subsequent stage circuit and includes a microprocessor, a buffer circuit and a malfunction prevention circuit, and the malfunction prevention circuit system The power supply is connected between the first output terminal of the microprocessor and the starting terminal of the buffer circuit, and the buffer circuit has an output control terminal power supply connected to the subsequent circuit, and the control method includes the steps of: (a) providing the first operating voltage and The second operating voltage is sent to the microprocessor; (b) the microprocessor receives the second operating voltage, and the second operating voltage rises from zero to the required voltage level during the voltage establishment process, corresponding to the establishment of the second operating voltage at The first output terminal of the microprocessor establishes an output voltage; (c) replaces the output voltage with the enabling level voltage by the malfunction prevention circuit, and outputs it to the starting terminal; and (d) according to the enabling level voltage of the starting terminal Make the output control terminal of the buffer circuit a high-impedance output to prevent malfunction of the subsequent stage circuit.

Further, the malfunction prevention circuit includes:

a first switch, a current input terminal of the first switch receives the second working voltage;

A first resistor, one end of the first resistor is connected to the first output terminal power supply, and receives the output voltage, and the other end of the first resistor is connected to a control terminal power supply of the first switch;

a second resistor, one end of the second resistor is connected to a current output end of the first switch;

a second switch, a control end of the second switch is connected to the other end of the second resistor with a power supply, and a current output end of the second switch is connected to a ground terminal with a power supply; and

A third resistor, one end of the third resistor is connected to a current input end of the second switch, and the other end of the third resistor receives the first working voltage.

Further, in the step (c), the output voltage turns off the first switch and the second switch, so that the first operating voltage is transmitted to the The start terminal is used to form the enable level voltage.

Further, it also includes a step: the buffer circuit judges the voltage level of the input terminal or the starting terminal of the buffer circuit according to whether the voltage level of the input terminal or the starting terminal is equal to or lower than a voltage judgment value Size, to control the output state of the output control terminal correspondingly.

Further, when the microprocessor receives the first operating voltage, the first operating voltage climbs from zero to a required voltage level, and when the first operating voltage reaches the required voltage level, the voltage is completed When established, the voltage level of the first working voltage is equal to the voltage judging value.

Further, when the voltage level of the input terminal or the activation terminal of the buffer circuit is equal to the voltage judgment value, the buffer circuit judges that the voltage level of the input terminal or the activation terminal is the enabling level When the voltage level of the input terminal or the activation terminal of the buffer circuit is lower than the voltage judgment value, the buffer circuit judges that the voltage level of the input terminal or the activation terminal is a disabled level.

Further, when the voltage on the input end of the buffer circuit is an enable level and the voltage on the start end is a disable level, the voltage on the output control end of the buffer circuit is an enable level, When the voltage on the input terminal of the buffer circuit is a disable level and the voltage on the start terminal is a disable level, the voltage on the output control terminal of the buffer circuit is a disable level, when the buffer When the voltage on the input terminal of the circuit is the enabling level or the disabling level and the voltage on the starting terminal is the enabling level, the output control terminal of the buffer circuit is the high-impedance output.

According to the idea of the present invention, the present invention also provides a malfunction prevention circuit, which is applied in a pulse width modulation system and connected between the first output terminal of the microprocessor and the start terminal of the buffer circuit, wherein the microprocessor The device receives the first operating voltage and the second operating voltage in sequence. When the microprocessor receives the second operating voltage, the first output terminal establishes a voltage corresponding to the second operating voltage and climbs from zero to the required voltage level. The output voltage and malfunction prevention circuit system includes: a first switch, the current input terminal of the first switch receives the second working voltage; a first resistor, one end of the first resistor is connected to the power supply of the first output terminal, and receives the output voltage, the second The other end of a resistor is connected to the power supply of the control terminal of the first switch; the second resistor is connected to the power supply of the current output terminal of the first switch; the second switch is connected to the control terminal of the second switch. The other end is connected to the power supply, the current output end of the second switch is connected to the ground end power supply; and the third resistor, one end of the third resistor is connected to the power supply of the current input end of the second switch, and the other end of the third resistor receives the first operating voltage ; Wherein, when the output voltage climbs from zero to the required voltage level, the first switch and the second switch are turned off, so that the first operating voltage is transmitted to the starting terminal through the third resistor and the current input terminal of the second switch, so that The output control terminal of the buffer circuit is a high-impedance output.

Further, the microprocessor has a first module, a second module and a third module, the first module receives the first operating voltage, the second module receives the second operating voltage, and the third module receives a The third working voltage, the microprocessor receives the third working voltage after receiving the second working voltage, the third working voltage climbs from zero to a required voltage level, and the first module, the second modules and the third module are started sequentially.

Further, after the third module starts to operate for a default time, the microprocessor performs a reset action, so that the voltage level of the output voltage of the first output terminal is controlled by the microprocessor.

Compared with prior art, the beneficial effect of the present invention is:

When the microprocessor is in the process of sequentially establishing the voltage required by each internal module, the pulse width modulation system malfunction prevention circuit can continuously output the enable level voltage to the start terminal of the buffer circuit, so that the output of the buffer circuit The terminal is a high-impedance output. In this way, it can prevent the subsequent circuit from abnormal operation during the process of establishing the voltage required by the internal modules in sequence by the microprocessor, thereby protecting the subsequent circuit.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic diagram of a circuit architecture of a conventional pulse width modulation system;

FIG. 2A is a timing diagram of various internal voltages of the first conventional pulse width modulation system shown in FIG. 1;

FIG. 2B is a timing diagram of various internal voltages of the first conventional pulse width modulation system shown in FIG. 1;

FIG. 2C is a timing diagram of various internal voltages of the first conventional pulse width modulation system shown in FIG. 1;

FIG. 2D is a timing diagram of various internal voltages of the first conventional pulse width modulation system shown in FIG. 1;

FIG. 3 is a schematic diagram of a circuit architecture of a pulse width modulation system according to a preferred embodiment of the present invention;

FIG. 4 is a truth table of the actuation relationship between the input terminal, the starting terminal and the output terminal of the buffer circuit shown in FIG. 3;

FIG. 5A is a timing diagram of various internal voltages of the first pulse width modulation system shown in FIG. 3;

FIG. 5B is a timing diagram of various internal voltages of the second pulse width modulation system shown in FIG. 3;

FIG. 5C is a timing diagram of various internal voltages of the third pulse width modulation system shown in FIG. 3;

FIG. 5D is a timing diagram of various internal voltages of the fourth pulse width modulation system shown in FIG. 3 ;

FIG. 6 is a flowchart of a control method of a pulse width modulation system according to a preferred embodiment of the present invention.

Reference signs:

1: Traditional pulse width modulation system;

11: Microprocessor;

111: input terminal;

112: output terminal;

113: the first module;

114: the second module;

12: buffer circuit;

121: input terminal;

122: start terminal;

123: output control terminal;

124: power terminal;

14: Post-stage circuit;

V ₁ : the first working voltage;

V ₂ : the second working voltage;

△V: output voltage;

t ₀ : initial time point;

t ₁ : the first time point;

t ₂ : the second time point;

t ₃ : the third time point;

T ₁ : the first period;

T ₂ : the second period;

V _L : Disable level voltage;

V _1s : the first specific voltage level;

V _2s : the second specific voltage level;

3: Pulse width modulation system;

31: microprocessor;

311: the first input terminal;

312: the second input terminal;

313: the first output terminal;

314: the second output terminal;

315: the third input terminal;

316: the first module;

317: the second module;

318: the third module;

32: buffer circuit;

321: input terminal;

322: start terminal;

323: output control terminal;

324: power terminal;

33: Malfunction prevention circuit;

34: Post-stage circuit;

Q ₁ : the first switch;

Q ₂ : the second switch;

R ₁ : the first resistor;

R ₂ : the second resistor;

R ₃ : the third resistor;

G: ground terminal;

V ₁ ': the first working voltage;

V ₂ ': the second working voltage;

V ₃ ': the third working voltage;

△V': output voltage;

R ₄ : the first pull-up resistor;

R ₅ : the second pull-up resistor;

A, B, C: the respective states of the input terminal, start terminal, and output control terminal of the buffer circuit;

V _1s ': the first specific voltage level;

V _2s ′: the second specific voltage level.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Elements and features described in one drawing or one embodiment of the present invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that representation and description of components and processes that are not related to the present invention and known to those of ordinary skill in the art are omitted from the drawings and descriptions for the purpose of clarity. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Referring to FIG. 3 , it is a schematic diagram of a circuit architecture of a pulse width modulation system according to a preferred embodiment of the present invention. As shown in FIG. 3 , the pulse width modulation system 3 is connected to a power supply of a subsequent circuit 34 to control the operation of the latter circuit 34 . The pulse width modulation system 3 includes a microprocessor 31, a buffer circuit 32 and a malfunction prevention circuit 33, wherein the microprocessor 31 at least includes a first input terminal 311, a second input terminal 312, a first output terminal 313, a second The output terminal 314 , the first module 316 and the second module 317 . The first input terminal 311 and the second input terminal 312 of the microprocessor 31 respectively receive different operating voltages, for example, the first operating voltage V ₁ ′ of 5V and the second operating voltage V ₂ ′ of 3.3V, for respectively It is used by the first module 316 and the second module 317 inside the microprocessor 31, wherein the first working voltage V ₁ ' is used by the first module 316 such as an analog/digital conversion module, and the second working voltage V ₂ ' is used by the second module 317 such as input/output status modules are used. In the above embodiment, when the first operating voltage V ₁ ′ and the second operating voltage V ₂ ′ are supplied to the microprocessor 31, they rise from 0V to required voltage levels, such as 5V and 3.3V, respectively. When the first working voltage V ₁ ′ and the second working voltage V ₂ ′ respectively reach the required voltage level and the voltage establishment is completed, the first module 316 and the second module 317 inside the microprocessor 31 can respectively start to operate.

The first output terminal 313 and the second output terminal 314 are used to output an output voltage ΔV', wherein the output voltage ΔV' rises from 0V to the required voltage level during the establishment of the second operating voltage V ₂ ' , it is established corresponding to the establishment of the second working voltage V ₂ ', that is, when the second working voltage V ₂ ' rises from 0V to the required voltage level, the output voltage △V' also rises synchronously from 0V to the required voltage level In addition, the voltage values of the output voltage ΔV' and the _{second operating voltage V 2 '} are the same as each other during the voltage establishment process. In addition, in this embodiment, there is a startup sequence between the first module 316 and the second module 317 , that is, the first module 316 and the second module 317 are started up sequentially. In addition, in other embodiments, the second output terminal 314 is also connected to a second pull-up resistor R ₅ and receives the second operating voltage V ₂ ′ through the second pull-up resistor R ₅ .

The buffer circuit 32 has an input terminal 321 , a start terminal 322 , an output control terminal 323 and a power supply terminal 324 , wherein the input terminal 321 is electrically connected to the second output terminal 314 of the microprocessor 31 . The output control terminal 323 is connected to the power supply of the subsequent circuit 34 and a first pull-up resistor R ₄ , and receives the first operating voltage V ₁ ′ through the first pull-up resistor R ₄ . The power terminal 324 receives the first operating voltage V ₁ ′, and the buffer circuit 32 starts to operate when the first operating voltage V ₁ ′ is established.

Referring to FIG. 4 together with FIG. 3 , FIG. 4 is a truth table of the actuation relationship between the input terminal, the start terminal and the output terminal of the buffer circuit shown in FIG. 3 . In this embodiment, the buffer circuit 32 controls the output state of the output control terminal 323 according to the voltage levels of the voltages received by the input terminal 321 and the enabling terminal 322 . It is further explained that the buffer circuit 32 judges whether the voltage level of the voltage received by the input terminal 321 or the starting terminal 322 is equal to or less than a voltage judgment value set by the buffer circuit 32 to determine whether the voltage received by the input terminal 321 or the starting terminal 322 The voltage level of the voltage, and correspondingly control the output state of the output control terminal 323 according to the judgment result of the input terminal 321 or the starting terminal 322, wherein when the voltage level of the voltage received by the input terminal 321 or the starting terminal 322 is equal to the buffer circuit When a voltage judgment value is set by 32, the buffer circuit 32 judges that the voltage level of the voltage received by the input terminal 321 or the starting terminal 322 is the enabling level voltage (high level voltage), otherwise, when the input terminal 321 Or when the voltage level of the voltage received by the starting terminal 322 is less than a voltage judgment value set by the buffer circuit 32, the buffer circuit 32 judges that the voltage level of the voltage received by the input terminal 321 or the starting terminal 322 is a disabled level voltage (low level voltage). In addition, when the buffer circuit 32 determines that the input terminal 321 receives the enable level voltage (high level voltage) and the enable terminal 322 receives the disable level voltage (low level voltage), the output control terminal 323 of the buffer circuit 32 The enabling level voltage is generated, that is, the state A shown in FIG. 4 . When the buffer circuit 32 judges that the input terminal 321 receives the disabling level voltage (low level voltage) and the enabling terminal 322 receives the disabling level voltage (low level voltage), the output control terminal 323 of the buffering circuit 32 generates a disabling voltage. Enable level voltage (low level voltage), such as state B. When the buffer circuit 32 judges that the enabling terminal 322 receives the enabling level voltage (high level voltage), no matter whether the input terminal 321 is the enabling level voltage or the disabling level voltage, the output control terminal 323 of the buffering circuit 32 is all High impedance output, such as state C, the voltage on the output control terminal 323 of the buffer circuit 32 will be the first working voltage V ₁ ′ due to the first working voltage V ₁ ′ received by the first pull-up resistor R ₄ . In the above-mentioned embodiment, when the first working voltage V ₁ ′ has reached the required voltage level (5V) and the voltage establishment is completed, the voltage level of the first working voltage V ₁ ′ is equal to the set voltage level of the buffer circuit 32 A voltage judgment value.

The malfunction prevention circuit 33 power supply is connected between the first output terminal 313 of the microprocessor 31 and the starting terminal 322 of the buffer circuit 32, for when the second module 317 starts to receive the second working voltage V ₂ ', and the second working The voltage V ₂ ' begins to rise from 0V to the voltage establishment process of the required voltage level, that is, the output voltage ΔV' output by the first output terminal 313 is in the voltage establishment process of rising from 0V to the required voltage level, Outputting an enabling level voltage (high level voltage) to the start terminal 322 of the buffer circuit 32 makes the output control terminal 323 of the buffer circuit 32 a high-impedance output.

Referring to FIG. 3 , in this embodiment, the malfunction prevention circuit 33 includes a first switch Q ₁ , a second switch Q ₂ , a first resistor R ₁ , a second resistor R ₂ and a third resistor R ₃ . Wherein, _one end of the first resistor R1 is connected to the power supply of the first output terminal 313 and receives the output voltage ΔV', and the other end of the _first resistor R1 is connected to the control terminal of the _first switch Q1. The current input terminal of the first switch Q ₁ receives the second working voltage V ₂ ′, and the current output terminal of the first switch Q ₁ is connected to a power source of one terminal of the second resistor R ₂ . The other end of the _second resistor R2 is connected to the control end of the second switch _Q2 for power supply. The current input end of the second switch _Q2 is connected to the start-up end 322 of the buffer circuit 32 and one end of the third resistor _R3 for power supply, and the current output end of the second switch _Q2 is connected to a ground terminal G for power supply. The other end of the third resistor R ₃ receives the first working voltage V ₁ ′.

In some embodiments, the _first switch Q1 can be a PNP bipolar junction transistor or a P-type metal-oxide-semiconductor field-effect transistor, and the second switch _Q2 can be an NPN. Bipolar junction transistor or N-type metal oxide semiconductor field effect transistor, but not limited thereto.

Referring to Fig. 5A, Fig. 5B, Fig. 5C and Fig. 5D together with Fig. 3 and Fig. 4, Fig. 5A, Fig. 5B, Fig. 5C and Fig. 5D are timing diagrams of the internal voltages of the pulse width modulation system shown in Fig. 3 . As shown in Fig. 3 to Fig. 5D, when the pulse width modulation system 3 starts to operate and the microprocessor 31 starts to establish the voltage stages required by the first module 316 and the second module 317, the microprocessor 31 is activated by the first module 316 There is a start-up sequence between the second module 317, so the first input terminal 311 and the second input terminal 312 of the microprocessor 31 receive the first operating voltage V ₁ ' and the second operating voltage V ₂ ' in sequence, so as shown in As shown in 5A, at the initial time point (t ₀ ), the first input terminal 311 of the microprocessor 31 starts to receive the first operating voltage V ₁ ′. Next, at the first time point (t ₁ ), the voltage level of the first operating voltage V ₁ ' climbs from 0V at the initial time point (t ₀ ) to a first specific voltage level V _1s ', for example 4.5V . At this moment, the second input terminal 312 of the microprocessor 31 starts to receive the second working voltage V ₂ ′. After that, from the first time point (t ₁ ) to the second time point (t ₂ ), the voltage level of the first operating voltage V ₁ ′ has reached the required voltage level, for example, 5V, so the first module 316 At the same time, the voltage level of the second working voltage V ₂ ′ climbs from 0V at the first time point (t ₁ ) to a second specific voltage level V _2s ′, for example, 2V. Finally, at the third time point (t ₃ ), the voltage level of the second operating voltage V ₂ ′ has reached the required voltage level, eg 3.3V, so the second module 317 starts to operate.

In addition, when the first input terminal 311 of the microprocessor 31 starts to receive the first working voltage V ₁ ′, the power supply terminal 324 of the buffer circuit 32 also starts to receive the first working voltage V ₁ ′, as shown in FIG. 5B . Next, at the first time point (t ₁ ), the voltage level of the first operating voltage V ₁ ' climbs from 0V at the initial time point (t ₀ ) to a first specific voltage level V _1s ', for example 4.5V . In this way, the voltage level of the first working voltage V ₁ ′ of the start-up terminal 322 of the buffer circuit 32 can be equal to a voltage judgment value set by the buffer circuit 32 .

Since the output voltage ΔV' of the first output terminal 313 and the second output terminal 314 of the microprocessor 31 corresponds to the second operating voltage V ₂ ' used as the second module 317 (input/output status module), and The voltage levels of the two also change correspondingly, so the output voltage ΔV' is actually equal to the voltage value of the second working voltage V ₂ ', and the second module 317 of the microprocessor 31 receives the second working voltage V ₂ ', as shown in Figure 5C, when the second input terminal 312 of the microprocessor 31 starts to receive the second operating voltage V ₂ ' at the first time point (t ₁ ), the current of the first switch Q ₁ At this time, the input terminal correspondingly receives the second working voltage V ₂ ′, and the output voltage ΔV’ of the first output terminal 313 and the second output terminal 314 of the microprocessor 31 also starts to build correspondingly, and the first output terminal 313 of the microprocessor 31 The output voltage ΔV' of the first output terminal 313 and the second output terminal also changes with the voltage level of the second operating voltage V ₂ ', that is, the output of the first output terminal 313 and the second output terminal 314 of the microprocessor 31 The voltage ΔV' also rises from 0V at the first time point (t ₁ ) to the second specific voltage level V _2s ' at the second time point (t ₁ ), such as 2V, and at the third time point (t3) At this time, the same voltage level as the second working voltage V ₂ ′, for example, 3.3V, is reached.

And when the microprocessor 31 starts to build the output voltage ΔV' at the first time point (t ₁ ) and climbs from 0V at the first time point (t ₁ ) to the second specific voltage at the second time point (t ₁ ). level V _2s ', and in the process of reaching the same voltage level as the second operating voltage V ₂ ' at the third time point (t3), due to the output voltage Δ output from the first output terminal 313 of the microprocessor 31 V' is the second operating voltage V ₂ ', and the current input end of the first switch Q ₁ of the malfunction prevention circuit 33 receives the second operating voltage V ₂ ', so the first output end 313 of the microprocessor 31 is connected to the first The voltage changes at the current input ends of the switch Q1 are equal, so that the _first switch Q1 is in _an off state, and the second switch _Q2 is correspondingly in an off state. At this time, the current input end of the second switch _Q2 will pass through the third resistor R ₃ receives the first operating voltage V ₁ ′, and guides the first operating voltage V ₁ ′ to the start-up terminal 322 of the buffer circuit 32. In this way, the buffer circuit 32 will receive the completed voltage establishment and the start-up terminal 322 Equal to the first operating voltage V ₁ ' of the voltage judgment value of the buffer circuit 32, and the start terminal 322 is determined to be the enabling level voltage (high level voltage), so the output control terminal 323 of the buffer circuit 32 will be a high-impedance output. The voltage on the output control terminal 323 of the buffer circuit 32 will form a consistent enable level voltage because the power supply is connected to the first pull _- up resistor R4 and the first pull _- up resistor R4 receives the _first operating voltage V1', as shown in the figure 5D.

Compared with the traditional pulse width modulation system, since the pulse width modulation system 3 of the present invention has a power supply connected between the first output terminal 313 of the microprocessor 31 and the start terminal 322 of the buffer circuit 32, the malfunction prevention circuit 33, During the process of the output voltage ΔV' output by the first output terminal 313 of the microprocessor 31 rising from 0V to the required voltage level (from the first time point (t ₁ ) to the third time point shown in FIG. 5A time point (t ₃ )), the malfunction prevention circuit 33 replaces the output voltage ΔV' with the first working voltage V ₁ ' of the enable level voltage, and outputs it to the start terminal 322 of the buffer circuit 32 (as shown in 5B), so that the output control terminal 323 of the buffer circuit 32 is a high-impedance output when the output voltage ΔV' output by the first output terminal 313 of the microprocessor 31 rises from 0V to the required voltage level, And the first working voltage V1' received by the first pull _- up resistor R4 is pulled up to the enabling level voltage (from the first time point (t ₁ ) to the third time point (t ) as shown in FIG. 5D ₃ )), so that the subsequent circuit 34 can be prevented from malfunctioning, thereby protecting the subsequent circuit 34.

FIG. 6 is a flowchart of a control method of a pulse width modulation system according to a preferred embodiment of the present invention. As shown in Fig. 3 to Fig. 6, in order to prevent the post-stage circuit 34 from generating abnormal actions at the voltage stage required by the pulse width modulation system 3 to establish each module, the pulse width modulation system 3 of the present invention executes the following control method: first , sequentially provide a first operating voltage V ₁ ′ and a second operating voltage V ₂ ′ to the microprocessor 31, so as to be provided to the first module 316 and the second module 317 respectively (step S1). Next, in the second module 317 of the microprocessor 31 receives the second operating voltage V ₂ ′, and during the voltage establishment process in which the second operating voltage V ₂ ′ rises from 0V to the required voltage level, the microprocessor 31 corresponds to The establishment of the second working voltage V ₂ ' establishes an output voltage ΔV' (step S2). Next, the malfunction prevention circuit 33 receives the output voltage △V', turns off the _first switch Q1, and drives the second switch _Q2 to turn off, so that the same enable level voltage, that is, the _first operating voltage V1' is output to the buffer The activation terminal 322 of the circuit 32 (step S3). Finally, the output control terminal 323 of the buffer circuit 32 is a high-impedance output according to the enabling level voltage of the enabling terminal 322 to protect subsequent circuits (step S4 ).

Referring to FIG. 3, FIG. 5A, FIG. 5B, FIG. 5C and FIG. 5D, in some embodiments, the microprocessor 31 can also receive a third operating voltage V ₃ ′ such as 1.5V, and has a third input terminal 315 and The third module 318 . The third input terminal 315 receives the third operating voltage V ₃ ′ for use by the third module 318 such as the core computing module. In addition, there is also a startup sequence among the first module 316 , the second module 317 and the third module 318 , that is, the first module 316 , the second module 317 and the third module 318 are started up sequentially. In addition, as shown in FIG. 5A, when the second working voltage V ₂ ′ received by the second module 317 completes voltage establishment, that is, at the third time point (t ₃ ), the third working voltage V ₃ ′ starts to be provided to The third module 318, and rises from 0V to the required voltage level, such as 1.5V, and when the third operating voltage V ₃ ′ reaches the required voltage level to complete the establishment of the voltage, the third module inside the microprocessor 31 318 to start operation.

Also in some embodiments, when the third module 318 inside the microprocessor 31 starts to operate for a default time due to the establishment of the third working voltage V ₃ ′, the microprocessor 31 will perform a reset action, so that The first output terminal 313 of the microprocessor 31 and the voltage level of the output voltage ΔV' output by the second output terminal 314 are controlled by the microprocessor 31, and when the voltage level of the output voltage ΔV' is less than When the current input terminal of the _first switch Q1 receives the _second operating voltage V2', the first switch Q1 is turned on, and the _second switch _Q2 is turned on correspondingly, so that the starting terminal 322 of the buffer circuit 32 is turned on The second switch Q ₂ of the second switch Q2 is connected to the ground terminal G power supply, so the voltage on the start terminal 322 of the buffer circuit 32 will be connected to the ground terminal G power supply as a disabled level voltage to drive the subsequent stage circuit 34 to start operation.

To sum up, the present invention provides a control method of a PWM system and its malfunction prevention circuit. When the microprocessor is in the process of sequentially establishing the voltage required by each internal module, the pulse width modulation system The malfunction prevention circuit can continuously output the enable level voltage to the start-up terminal of the buffer circuit, so that the output terminal of the buffer circuit is a high-impedance output. In this way, it can prevent the subsequent stage circuit from being sequentially established by the microprocessor. Abnormal operation occurs during the voltage required by the module, thereby protecting the subsequent circuit.

Finally, it should be noted that although the present invention and its advantages have been described in detail above, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the present invention defined by the appended claims. transform. Moreover, the scope of the present invention is not limited to the specific embodiments of the procedures, devices, means, methods and steps described in the specification. Those of ordinary skill in the art will readily appreciate from the disclosure of the present invention that existing and future devices that perform substantially the same function or obtain substantially the same results as the corresponding embodiments described herein can be used in accordance with the present invention. The developed process, device, means, method or steps. Accordingly, the appended claims are intended to include within their scope such processes, means, means, methods or steps.

Claims (10)

1. a pulse width modulation system control method, it is characterized in that, this pulse width modulation system is connected with a late-class circuit power supply and comprises a microprocessor, a buffer circuit and a misoperation and prevents circuit, this misoperation prevents circuit from being that power supply is connected between one first output of this microprocessor and a start end of this buffer circuit, and this buffer circuit has an output control terminal power supply is connected to this late-class circuit, this control method comprises step:

A () sequentially provides one first operating voltage and one second operating voltage to this microprocessor;

B () receives this second operating voltage in this microprocessor, and this second operating voltage rises in the Voltage Establishment process of a required voltage level by above freezing, to this first output building on this microprocessor of the second operating voltage setting up an output voltage;

C () prevents circuit that this output voltage is replaced into an activation level voltage by this misoperation, and export this start end to; And

D () makes this output control terminal of this buffer circuit be a high impedance output according to this activation level voltage of this start end, produce misoperation to prevent this late-class circuit.

2. pulse width modulation system control method as claimed in claim 1, it is characterized in that, this misoperation prevents circuit from comprising:

One first switch, a current input terminal of this first switch receives this second operating voltage;

One first resistance, one end of this first resistance is connected with this first output end power, and receives this output voltage, and the other end of this first resistance is connected with a control end power supply of this first switch;

One second resistance, one end of this second resistance is connected with a current output terminal power supply of this first switch;

One second switch, a control end of this second switch is connected with the other end power supply of this second resistance, and a current output terminal of this second switch is connected with an earth terminal power supply; And

One the 3rd resistance, one end of the 3rd resistance is connected with a current input terminal power supply of this second switch, and the other end of the 3rd resistance receives this first operating voltage.

3. the pulse width modulation system control method as described in claim the 2nd, it is characterized in that, in this step (c), this output voltage makes this first switch and the cut-off of this second switch, this first operating voltage is made to be sent to this start end, to form this activation level voltage via this current input terminal of the 3rd resistance and this second switch.

4. pulse width modulation system control method as claimed in claim 1, it is characterized in that, also comprise step: whether this buffer circuit is equal to or less than a voltage judgment value according to the level of the voltage on an input or this start end and judges the voltage quasi position size in this input of this buffer circuit or this start end, controls the output state of this output control terminal with correspondence.

5. pulse width modulation system control method as claimed in claim 4, it is characterized in that, when this microprocessor receives this first operating voltage, this the first operating voltage system rises to a required voltage level by zero, and when this first operating voltage reaches this required voltage level and completes Voltage Establishment, the voltage quasi position of this first operating voltage equals this voltage judgment value.

6. pulse width modulation system control method as claimed in claim 4, it is characterized in that, when the level of the voltage on this input or this start end of this buffer circuit equals this voltage judgment value, the level of the voltage that this buffer circuit judges in this input or this start end is activation level, when the level of the voltage on this input or this start end of this buffer circuit is less than this voltage judgment value, the level of the voltage that this buffer circuit judges in this input or this start end is forbidden energy level.

7. pulse width modulation system control method as claimed in claim 6, it is characterized in that, voltage on this input of this buffer circuit be activation level and voltage in this start end is forbidden energy level time, voltage on this output control terminal of this buffer circuit is activation level, voltage on this input of this buffer circuit be forbidden energy level and voltage in this start end is forbidden energy level time, voltage on this output control terminal of this buffer circuit is forbidden energy level, voltage on this input of this buffer circuit be activation level or forbidden energy level and voltage in this start end is activation level time, this output control terminal of this buffer circuit is this high impedance output.

8. a misoperation prevents circuit, it is characterized in that, be applied in a pulse width modulation system, and be connected between one first output of a microprocessor and a start end of a buffer circuit, wherein this microprocessor received in sequence one first operating voltage and one second operating voltage, when this microprocessor receives this second operating voltage, this the first output system sets up corresponding with this second operating voltage and rises to an output voltage of required voltage level by zero, and this misoperation prevents circuit from comprising:

One first switch, a current input terminal of this first switch receives this second operating voltage;

One first resistance, one end of this first resistance is connected with this first output end power, and receives this output voltage, and the other end of this first resistance is connected with a control end power supply of this first switch;

One second resistance, one end of this second resistance is connected with a current output terminal power supply of this first switch;

One second switch, a control end of this second switch is connected with the other end power supply of this second resistance, and a current output terminal of this second switch is connected with an earth terminal power supply; And

One the 3rd resistance, one end of the 3rd resistance is connected with a current input terminal power supply of this second switch, and the other end of the 3rd resistance receives this first operating voltage;

Wherein, when this output voltage rises to required voltage level by zero, this first switch and the cut-off of this second switch, make this first operating voltage be sent to this start end via this current input terminal of the 3rd resistance and this second switch, make an output control terminal of this buffer circuit be a high impedance output.

9. misoperation as claimed in claim 8 prevents circuit, it is characterized in that, this microprocessor has one first module, one second module and one the 3rd module, this first module receives this first operating voltage, this second module receives this second operating voltage, 3rd module receives one the 3rd operating voltage, this microprocessor receives the 3rd operating voltage after this second operating voltage of reception, 3rd operating voltage system rises to a required voltage level by zero, and this first module, this second module and the 3rd module sequential start.

10. misoperation as claimed in claim 9 prevents circuit, and it is characterized in that, after the 3rd module comes into operation a default time, this microprocessor carries out a replacement action, makes the voltage quasi position of this output voltage of this first output by this Microprocessor S3C44B0X.