CN105207661A - Multi-point low-voltage differential signal transmitter - Google Patents

Abstract

The present invention provides a multi-point low-voltage differential signal transmitter, comprising: a transmitter body, the transmitter body is a dual current mode transmitter structure, including: first and second PMOS current mirror tubes, first and second An NMOS current mirror tube, and a complementary bridge switch tube composed of the first and second PMOS switch tubes and the first and second NMOS switch tubes; wherein, the source terminal of the first PMOS current source tube is connected to the power supply voltage, and the second The source terminal of an NMOS current source tube is grounded, the complementary bridge switch tube is connected to the drain terminals of the first PMOS current source tube and the first NMOS current source tube, and the source terminal and drain terminal of the second PMOS current mirror tube are respectively connected to the power supply voltage and the first current source, the source terminal and the drain terminal of the second NMOS current mirror tube are respectively connected to the ground and the second current source; the leakage smoothing circuit is composed of the first diode, the second diode and the first switch in series , connected in parallel with the complementary bridge switch tube. The invention solves the problem of output overshoot and improves circuit performance by introducing a current discharge path to compensate the impedance of the drain end of the current source.

Description

A Multipoint Low Voltage Differential Signal Transmitter

technical field

The invention relates to the technical field of IC design, in particular to a structural design of an MLVDS transmitter.

Background technique

With the advent of the era of big data, the rapid processing and high-speed transmission of data has become a focus of attention. In this context, the interface has become a bottleneck restricting high-speed data transmission. As an upgrade of RS482 in speed and function, MLVDS (Multi-point Low-Voltage Differential Signaling, multi-point low-voltage differential signal) technology proposed by TI company came into being. MLVDS technology has many advantages such as high transmission speed of LVDS technology, strong anti-noise ability, low power consumption, low electromagnetic radiation, etc., and can be applied to multi-point bus system to complete the mutual communication between multiple drivers and multiple receivers. Because it is mainly used in multi-point bus systems, in order to reduce the reflection caused by impedance discontinuity, the conversion time of the signal should be as long as possible. The conversion time required by the TIA/EIA-899 protocol must be greater than 1ns.

The traditional MLVDS transmitter structure is shown in Figure 1. This structure includes a dual-current-mode transmitter structure composed of M1~M8. The complementary input signals Vinp and Vinn with relatively large switching times (generally greater than 2ns) are respectively loaded into the complementary bridge The gate of the switch tube. When the Vinp transitions from low level to high level and Vinn transitions from high level to low level, since the input signal changes very slowly, the first NMOS switch (M3) and the second PMOS switch The gate voltage of the tube (M2) slowly changes from low level to high level, and the gate voltages of the second NMOS switch tube (M4) and the first PMOS switch tube (M1) slowly change from high level to low level. The overdrive capabilities of the second PMOS switch tube (M2) and the second NMOS switch tube (M4) gradually decrease, so the current that can flow through them gradually becomes smaller, and instead flows through the first PMOS switch tube (M1 ) and the current of the first NMOS switch tube (M3) gradually increase.

Since the speed of current switching is relatively slow, the voltage at both ends of the terminal resistor also changes slowly, and finally achieves a relatively long switching time. However, the slowly changing gate signal will weaken the effect of the bridge switch tube, and it is easy to cause inconsistency in the turn-on and cut-off steps of the bridge switch tube. The direct result of this phenomenon is overshoot.

As shown in Figure 1, when the Vinp transitions from low level to high level and Vinn transitions from high level to low level, the NMOS switch (M3) will be turned on and M4 will be cut off, but it cannot be guaranteed When M3 is turned on, M4 is just turned off; conversely, it cannot be guaranteed that M4 is just turned on when M3 is turned off. Similarly, it cannot be guaranteed that M2 is just turned off when the PMOS switch tube M1 is turned on; conversely, it cannot be guaranteed that M2 is just turned on when M1 is turned off. Therefore, there are 16 possibilities for the working state of the bridge switch tube during this period. These 16 states will make the impedance of the drain end of the upper and lower current mirrors larger, because the switch tube has the minimum impedance when it works in the deep linear region, and the direct effect is that the drain of the first PMOS current mirror tube (M5) will be A peak voltage appears, and at the same time, a valley voltage appears on the drain of the first NMOS current mirror tube (M7), and the peak and valley are transmitted to the output terminal through the gate-source parasitic capacitance of the switch tube, thereby affecting the quality of the output signal.

Contents of the invention

Therefore, the present invention proposes a multi-point low-voltage differential signal transmitter with a leakage smoothing circuit to solve the overshoot problem of the output signal caused by increasing the output conversion time in the existing structure, including:

The main body of the transmitter, the main body of the transmitter is a dual current mode transmitter structure, including: first and second PMOS current mirror tubes, first and second NMOS current mirror tubes, and the first and second PMOS switch tubes and A complementary bridge switch tube composed of first and second NMOS switch tubes; wherein, the source terminal of the first PMOS current source tube is connected to the power supply voltage, the source terminal of the first NMOS current source tube is grounded, and the complementary bridge switch tube is connected to the At the drain end of a PMOS current drain tube and the first NMOS current source tube, the source end and the drain end of the second PMOS current mirror tube are connected to the power supply voltage and the first current source respectively, and the source end and the drain end of the second NMOS current mirror tube Terminals are respectively connected to the ground and the second current source;

The discharge smoothing circuit is composed of a first diode, a second diode and a first switch in series, and is connected in parallel with the complementary bridge switch tube.

Wherein, the first switch is controlled by an enabling signal, and when the enabling signal is valid, the first switch is closed, and the leakage smoothing circuit works normally; when the enabling signal is invalid, the first switch is turned off, and the The leakage smoothing circuit described above stops working.

Wherein, the connection mode of the complementary bridge switch tube is:

The drain end of the first PMOS switch tube is connected to the drain end of the first NMOS switch tube, the source end of the first PMOS switch tube is connected to the power supply voltage, and the source end of the first NMOS switch tube is grounded;

The drain terminal of the second PMOS switch tube is connected to the drain terminal of the second NMOS switch tube, the source terminal of the second PMOS switch tube is connected to the power supply voltage, and the source terminal of the second NMOS switch tube is grounded.

Wherein, the complementary bridge switch tube further includes a load resistor connected to the drain terminals of the first and second PMOS switch tubes and the first and second NMOS switch tubes.

Wherein, the input signals of the multi-point low-voltage differential signal transmitter are two complementary input signals, which are respectively input to the gates of the first NMOS, the first PMOS switch and the second NMOS, the second PMOS switch.

The present invention introduces a current discharge path, connected in parallel with the resistance between the drain terminals of the upper and lower current sources, thereby compensating the impedance of the drain terminals of the upper and lower current sources when the input signal is slowly reversed, and stabilizing the drain terminal voltage of the upper and lower current mirrors at this stage. At the same time, the discharge path does not affect the impedance of the drain end of the upper and lower current mirrors when the input signal is a level signal, so as to avoid affecting the normal steady-state differential output. The circuit of the invention can well solve the output overshoot problem of the traditional MLVDS driver, and improves the overall performance of the circuit.

Description of drawings

Other characteristics, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

FIG. 1 is a schematic structural diagram of a traditional MLVDS transmitter;

FIG. 2 is a schematic structural diagram of a specific implementation of an MLVDS transmitter capable of reducing overshoot provided by an embodiment of the present invention;

FIG. 3 is a comparison simulation diagram of a differential output waveform of a traditional transmitter and a differential output waveform of a transmitter provided by an embodiment of the present invention;

The same or similar reference numerals in the drawings represent the same or similar components.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention.

The multi-point low-voltage differential signal transmitter provided by the present invention with a flow-discharging smoothing circuit is shown in Figure 2, including:

The main body of the transmitter, the main body of the transmitter is a dual current mode transmitter structure, including: first and second PMOS current mirror tubes M5 and M6, first and second NMOS current mirror tubes M7 and M8, and the first and second NMOS current mirror tubes M7 and M8. The complementary bridge switch tube 201 composed of the second PMOS switch tube M1, M2 and the first and second NMOS switch tubes M3, M4; wherein, the source terminal of the first PMOS current source tube M5 is connected to the power supply voltage, and the first NMOS switch tube M5 The source terminal of the current source tube M7 is grounded, the complementary bridge switch tube 201 is connected to the drain terminals of the first PMOS current source tube M5 and the first NMOS current source tube M7, and the source terminal and the drain terminal of the second PMOS current mirror tube M6 are respectively Connected to the power supply voltage and the first current source 206, the source terminal and the drain terminal of the second NMOS current mirror tube M8 are respectively connected to the ground and the second current source 207;

The discharge smoothing circuit 205 is composed of a first diode 214 , a second diode 215 and a first switch 216 connected in parallel with the complementary bridge switch 201 . Specifically, the anode of the first diode 214 is connected to the drain of the first PMOS switch M1, the cathode of the first diode 214 is connected to the anode of the second diode 215, the second two The other end of the transistor 215 is connected to one end of the first switch 216, and the other end of the first switch 216 is connected to the drain of the first NMOS switch M3.

Wherein, the first switch 216 is controlled by an enable signal, and when the enable signal is valid, the first switch 216 is closed, and the described discharge smoothing circuit 201 works normally; when the enable signal is invalid, the first switch 216 disconnected, the leakage smoothing circuit 201 stops working.

Wherein, the connection mode of the complementary bridge switch tube 201 is:

The drain terminal of the first PMOS switch tube M1 is connected to the drain terminal of the first NMOS switch tube M4, the source terminal of the first PMOS switch tube M1 is connected to the power supply voltage, and the source terminal of the first NMOS switch tube M1 is grounded;

The drain of the second PMOS switch M2 is connected to the drain of the second NMOS switch M3 , the source of the second PMOS switch M2 is connected to the power supply voltage, and the source of the second NMOS switch M3 is grounded.

Wherein, the complementary bridge switch tube 201 further includes a load resistor R _load connected to the drain terminals of the first and second PMOS switch tubes M1 and M2 and the first and second NMOS switch tubes M3 and M4 .

Wherein, the input signal of the multi-point low-voltage differential signal transmitter is two complementary input signals Vinn and Vinp, which are respectively input into the first NMOS, the first PMOS switch tube M4, M1 and the second NMOS, the second PMOS switch tube M3 , The gate of M2.

Wherein, the complementary input signals Vinp signal and Vinn signal are a pair of TTL differential mode signals with a longer switching time, generally 2 ns.

The first bias current 206 and the second bias current 207 have the same current value.

Compared with the existing MLVDS technology, the beneficial effects produced by the technical solution of the present invention are as follows:

1. The MLVDS transmitter that can reduce the overshoot provided by the embodiment of the present invention uses two diodes to discharge the large current in the current source during the signal conversion process, and clamps the first PMOS current mirror M5 and the first NMOS current The drain voltage difference of the mirror M7 reduces the peak-to-valley voltage, thereby reducing overshoot.

2. The MLVDS transmitter that can reduce the overshoot provided by the embodiment of the present invention discharges most of the current in the current source M5 during the conversion process of the differential input signal through the discharge smoothing circuit 205, reducing the flow through the terminal The current component of the resistor increases the conversion time of the differential output and improves the system index.

3. The embodiment of the present invention provides an MLVDS transmitter capable of reducing overshoot. By enabling the switch 216, the leakage current from the PMOS current source M5 to the NMOS current source M7 is reduced when the circuit is disabled, so as to avoid increasing the total power consumption of the system.

In order to make those skilled in the art better understand the present invention, the specific working process of the MLVDS transmitter provided by an embodiment of the present invention will be described in detail below.

As shown in FIG. 2, when the Vinp is at a low level and Vinn is at a high level, the gate voltages of the first NMOS switch M3 and the second PMOS switch M2 are at a low level, and the second NMOS The gate voltages of the switch transistor M4 and the first PMOS switch transistor M1 are at a high level. At this time, the second PMOS switch M2 and the second NMOS switch M4 are turned on, and the first PMOS switch M1 and the first NMOS switch M3 are turned off. The power supply 201 will form a path to the ground 202 through the first PMOS current mirror tube M5, the second PMOS switch tube M2, the terminal load 50Ω, the second NMOS switch tube M4 and the first NMOS current mirror tube M7, and the operating current will flow about 11mA. Since the turned-on switch tubes all work in the deep linear region, the resistance value is very small. Therefore, the voltage applied to both ends of the current-discharging and smoothing circuit 205 is slightly lower than the threshold voltage of the first diode 214 by about 750mv, so the current flowing through the current-discharging and smoothing circuit 205 is extremely small and can be ignored.

When the Vinp transitions from low level to high level and Vinn transitions from high level to low level, the gate voltages of the first NMOS switch M3 and the second PMOS switch M2 slowly change from low to low. level becomes high level, and the gate voltages of the second NMOS switch M4 and the first PMOS switch M1 slowly change from high level to low level. The overdrive capabilities of the second PMOS switch M2 and the second NMOS switch M4 gradually decrease, so the current that can flow through them gradually decreases, and conversely flows through the first PMOS switch M1 and the first NMOS switch The current of the tube M3 becomes larger gradually, so that the voltage at both ends of the terminal resistor also changes slowly, thereby realizing a larger switching time.

However, the slowly changing gate signal will weaken the effect of the bridge switch tube, making the on-off pace of the bridge switch tube inconsistent with the normal steady state. However, in the process of signal inversion, no matter what state the bridge switches are in, the impedance between the drain terminal of the upper PMOS current mirror M5 and the drain terminal of the lower NMOS current mirror is higher than that under normal TTL level driving. big. This is because the impedance under TTL level driving is the parallel connection of the deeply linearly operated switch tube and the cut-off switch tube, and the impedance is the lowest. Due to the increase of impedance, the voltage divided in the current mode circuit also becomes larger, so that a peak voltage will appear in the drain of the first PMOS current mirror tube M5, and at the same time, the drain of the first NMOS current mirror tube M7 There will be a valley voltage in the pole, and the peak and valley voltage will be transmitted to the output terminal through the gate-source capacitance of the switch tube, thereby affecting the quality of the output signal. And the slower the signal flips, the longer it will affect the output signal.

The current leakage smoothing circuit proposed by the embodiment of the present invention can well reduce the peak voltage and valley voltage, so that the output steady-state level is relatively gentle. Through the conduction and low-resistance characteristics of the first diode 214 and the second diode 215, the drain voltage difference between the first PMOS current mirror M5 and the first NMOS current mirror M7 is clamped at a fixed value of about 1.5v, balanced peak and valley voltage, thereby reducing the overshoot of the output signal. At the same time, during the inversion of the input signal, the large leakage capacity of the diode reduces the current component of the total operating current flowing through the terminal resistance R _load , thereby reducing the charge and discharge speed of the load impedance and increasing the conversion time of the output signal. Improved system metrics.

When the Vinp is at a high level and Vinn is at a low level, the gate voltages of the first NMOS switch M3 and the second PMOS switch M2 are at a high level, and the second NMOS switch M4 and the first The gate voltage of the PMOS switch M1 is at a low level. At this time, the second PMOS switch M2 and the second NMOS switch M4 are turned off, and the first PMOS switch M1 and the first NMOS switch M3 are turned on. The power supply 201 will form a path to the ground 202 through the first PMOS current mirror tube M5, the first PMOS switch tube M1, the terminal load 50Ω, the first NMOS switch tube M3 and the first NMOS current mirror tube M7, and the operating current will flow about 11mA. Since the turned-on switch tubes all work in the deep linear region, the resistance value is very small. Therefore, the voltage applied to both ends of the current-discharging smoothing circuit 205 is slightly lower than the threshold voltage of the first diode 214 by about 750mv, so the current flowing through the current-discharging and smoothing circuit 205 is extremely small and can be ignored.

When the Vinp transitions from high level to low level and Vinn transitions from low level to high level, the gate voltages of the first NMOS switch M3 and the second PMOS switch M2 slowly change from high level to becomes low level, the gate voltages of the second NMOS switch M4 and the first PMOS switch M1 slowly change from low level to high level. The overdrive capabilities of the first PMOS switch M2 and the first NMOS switch M4 gradually decrease, so the current that can flow through them gradually decreases, and conversely flows through the second PMOS switch M1 and the second NMOS switch The current of the tube M3 becomes larger gradually, so that the voltage at both ends of the terminal resistor also changes slowly, thereby realizing a larger switching time.

However, the slowly changing gate signal will weaken the effect of the bridge switch tube, making the on-off pace of the bridge switch tube inconsistent with the normal steady state. However, in the process of signal inversion, no matter what state the bridge switches are in, the impedance between the drain terminal of the upper PMOS current mirror M5 and the drain terminal of the lower NMOS current mirror is higher than that under normal TTL level driving. big. This is because the impedance under TTL level driving is the parallel connection of the deeply linearly operated switch tube and the cut-off switch tube, and the impedance is the lowest. Due to the increase of impedance, the voltage divided in the current mode circuit also becomes larger, so that a peak voltage will appear in the drain of the first PMOS current mirror tube M5, and at the same time, the drain of the first NMOS current mirror tube M7 There will be a valley voltage in the pole, and the peak and valley voltage will be transmitted to the output terminal through the gate-source capacitance of the switch tube, thereby affecting the quality of the output signal. And the slower the signal flips, the longer it will affect the output signal.

The current leakage smoothing circuit proposed by the embodiment of the present invention can well reduce the peak voltage and valley voltage, so that the output steady-state level is relatively gentle. Through the conduction and low-resistance characteristics of the first diode 214 and the second diode 215, the drain voltage difference between the first PMOS current mirror M5 and the first NMOS current mirror M7 is clamped at a fixed value of about 1.5v, balanced peak and valley voltage, thereby reducing the overshoot of the output signal. At the same time, during the inversion of the input signal, the large leakage capacity of the diode reduces the current component of the total operating current flowing through the terminal resistance R _load , thereby reducing the charge and discharge speed of the load impedance and increasing the conversion time of the output signal. Improved system metrics.

FIG. 3 is a comparison simulation diagram of the differential output waveform Vod of the traditional transmitter and the differential output waveform Vod2 of the transmitter provided by the embodiment of the present invention. It can be seen from the figure that the MLVDS transmitter with reduced overshoot provided by the present invention can indeed achieve the beneficial effects of reducing the overshoot of the differential output and increasing the conversion time.

The above-mentioned embodiment is a preferred embodiment of the present invention, but the embodiment of the present invention is not limited by the above-mentioned embodiment, and any other changes, modifications, substitutions, combinations, Simplifications should be equivalent replacement methods, and all are included in the protection scope of the present invention.

Claims (5)

1. a multiple spot Low Voltage Differential Signal transmitter, comprising:

Transmitter main body, described transmitter main body is double-current mould transmitter architecture, comprise: first, second PMOS current mirror pipe (M5, M6), first, second NMOS current mirror pipe (M7, M8), and the complementary bridge switch pipe (201) be made up of first, second PMOS switch pipe (M1, M2) and first, second nmos switch pipe (M3, M4); Wherein, the source of a described PMOS electric current source capsule (M5) connects supply voltage, the source ground connection of the one NMOS electric current source capsule (M7), complementary bridge switch pipe (201) is connected on the drain terminal of a PMOS electric current source capsule (M5) and a NMOS electric current source capsule (M7), the source of the 2nd PMOS current mirror pipe (M6) and drain terminal connect supply voltage and the first current source (206) respectively, source and the drain terminal of the 2nd NMOS current mirror pipe (M8) be connected respectively with the second current source (207);

Earial drainage flat wave circuit (205) is composed in series by the first diode (214), the second diode (215) and the first switch (216), in parallel with described complementary bridge switch pipe (201).

2. multiple spot Low Voltage Differential Signal transmitter according to claim 1, it is characterized in that, described first switch (216) is controlled by enable signal, when enable signal is effective, first switch (216) closes, and described earial drainage flat wave circuit (201) normally works; When enable signal is invalid, the first switch (216) disconnects, and described earial drainage flat wave circuit (201) quits work.

3. multiple spot Low Voltage Differential Signal transmitter according to claim 1, is characterized in that, the connected mode of described complementary bridge switch pipe (201) is:

The drain terminal of the first PMOS switch pipe (M1) is connected with the drain terminal of the first nmos switch pipe (M4), and the source of the first PMOS switch pipe (M1) connects supply voltage, the source ground connection of the first nmos switch pipe (M1);

The drain terminal of the second PMOS switch pipe (M2) is connected with the drain terminal of the second nmos switch pipe (M3), and the source of the second PMOS switch pipe (M2) connects supply voltage, the source ground connection of the second nmos switch pipe (M3).

4. multiple spot Low Voltage Differential Signal transmitter according to claim 3, it is characterized in that, described complementary bridge switch pipe (201) also comprises the load resistance (R be connected to by first, second PMOS switch pipe (M1, M2) and first, second nmos switch pipe (M3, M4) drain terminal _load).

5. multiple spot Low Voltage Differential Signal transmitter according to claim 3, it is characterized in that, the input signal of described multiple spot Low Voltage Differential Signal transmitter is two complementary input signals (Vinn, Vinp), inputs the grid of a NMOS, the first PMOS switch pipe (M4, M1) and the 2nd NMOS, the second PMOS switch pipe (M3, M2) respectively.