CN105208792A - PCB manufacturing method for preventing tombstoning effect - Google Patents
PCB manufacturing method for preventing tombstoning effect Download PDFInfo
- Publication number
- CN105208792A CN105208792A CN201510483707.7A CN201510483707A CN105208792A CN 105208792 A CN105208792 A CN 105208792A CN 201510483707 A CN201510483707 A CN 201510483707A CN 105208792 A CN105208792 A CN 105208792A
- Authority
- CN
- China
- Prior art keywords
- pcb
- phenomenon
- monument
- size
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 230000000694 effects Effects 0.000 title abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 29
- 229910000679 solder Inorganic materials 0.000 claims abstract description 18
- 238000005457 optimization Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 14
- 238000006073 displacement reaction Methods 0.000 abstract description 8
- 238000005476 soldering Methods 0.000 abstract description 6
- 238000002844 melting Methods 0.000 abstract description 4
- 230000008018 melting Effects 0.000 abstract description 4
- 239000007788 liquid Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 5
- 239000006071 cream Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09427—Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention discloses a PCB manufacturing method for preventing the tombstoning effect. The method comprises the following steps that S1) two pads which are symmetrical by taking a center line of a component as the center are prepared on a PCB; S2) soldering paste layers are prepared at the surfaces of the pads respectively, and the size of the soldering paste layers is lower than that of the pads; and S3) the wiring manner of the PCB is optimized. The symmetry of the pads is accurately controlled to ensure that the surface tension of molten soldering tin at the two ends of the component is balanced; and the soldering paste layers are properly reduced to reduce displacement space of a device in the molten tin liquid, further to reduce displacement of the device, and to effectively reduce the possibility of tombstoning, displacement and tin connection phenomena of the component. The wiring manner is optimized, so that heat conduction channels at the two ends of the device are consistent in size and shape, the heat conduction effects are also the same, the difference of melting speed of the solder paste at the two ends of the device is reduced, the tombstoning phenomenon is further prevented, and the production cost is reduced.
Description
Technical field
The present invention relates to a kind of manufacture method of printed circuit board, relate in particular to a kind of element that improves and to set up a monument the manufacture method of printed circuit board of phenomenon.
Background technology
Also known as printed circuit board (PCB), adopt electron printing to be made, be a kind of important electronic unit to printed circuit board (PrintedCircuitBoard is called for short PCB), is the supporter of electronic component and the carrier of electronic device electrical connection.Along with the made rapid progress of science and technology, electronic product is constantly to miniaturized and multifunction development, the short and small frivolous mainstream development trend becoming electronic product gradually, printed circuit board thereupon in electronic product also develops towards high accuracy, high density and high reliability, continuous reduced volume, raising performance.
Along with element weight is more and more lighter; when it is welded on PCB by the solder reflow process of surface mount process; bond pad surface is left in the one end that often there will be surface mount elements; element is inclination or upright; if its shape stone tablet; be called stone tablet phenomenon, also claim suspension bridge phenomenon or Manhattan phenomenon, it with float, be considered to defect common in solder reflow process together with displacement.Phenomenon of setting up a monument generally occurs in chip component (as patch capacitor and Chip-R), and component size is more little more easily occurs.The main cause that phenomenon of setting up a monument occurs is that soldering paste on the pad of element two ends is when refluxing fusing, the surface tension of element two welding ends is uneven, one end that tension force is larger hauls element and causes the other end to leave bond pad surface along rotating bottom it, mainly element two ends temperature is uneven for the reason of element two ends tension imbalance, and the soldering paste at element two ends is not melted simultaneously.
The main method improving phenomenon of setting up a monument in prior art is normally controlled in surface mounting technology (SurfaceMountTechnology, be called for short SMT) paster process: change furnace with mutiple temperature regions, control furnace temperature, change hot air reflux mode in stove, change thermal conductivity and the good substrate of thickness evenness, change the good tin cream etc. of uniformity.But these control methods exist following shortcoming: (1) cost is high, often need to change more advanced and that value is expensive equipment and just can make moderate progress; (2) control flow is complicated; (3) manpower and materials expend seriously, finally also need manually could finally complete leaving over device maintenance of setting up a monument.
Summary of the invention
For this reason, technical problem to be solved by this invention is that the existing element that improves sets up a monument that the PCB manufacture method cost of phenomenon is high, flow process is complicated, manpower and materials expend seriously, thus propose that a kind of production cost is low, automaticity is high, flow process simply improves element and to set up a monument the manufacture method of PCB of phenomenon.
For solving the problems of the technologies described above, technical scheme of the present invention is:
The invention provides a kind of element that improves to set up a monument the PCB manufacture method of phenomenon, it comprises the following steps:
S1, on PCB, make two pads at counter element two ends, two described pads are symmetrical arranged along the center line of described element;
S2, make layer of solder paste in described bond pad surface, described layer of solder paste size is less than described pad size;
The wire laying mode of S3, optimization PCB.
As preferably, described step S3 comprises the following steps:
A. the magnitude of current of the interconnected cabling by described element is determined;
B. described interconnected routing interconnect form is determined.
As preferably, the interconnection form of described interconnected cabling is cross or yi word pattern.
As preferably, the interconnect traces consistent size of described two pad both sides.
As preferably, the little 1-2mil of described layer of solder paste single side size more described pad single side size.
As preferably, two described pad sizes at described element two ends are consistent.
Technique scheme of the present invention has the following advantages compared to existing technology:
(1) element that improves provided by the invention is set up a monument the PCB manufacture method of phenomenon, and it comprises the following steps: S1, on PCB, make the pad of the center line symmetry along element; S2, bond pad surface make layer of solder paste, layer of solder paste size is less than pad size; The wire laying mode of S3, optimization PCB.First, the application, by accurately controlling the symmetry of pad, ensure that element two ends fusion weld tin surfaces equalization of strain.Secondly, in in existing PCB pad manufacture craft, the size of layer of solder paste and pad is etc. large, and the size of pad layer of solder paste determines the size of brush tin cream, in the process of welding, the tin of post liquefaction can to perimeter under the effect of device stress, even overflow body device context, make easily to occur displacement in device bonding pad tin liquor after being melted down, rotate, cause setting up a monument, open circuit, connect the phenomenons such as tin, in this programme, layer of solder paste is suitably reduced, reduce the space of device displacement in the tin liquor of melting postwelding, reduce device displacement, thus effectively reduce element and set up a monument, displacement, connect the occurrence probability of tin phenomenon.
(2) element that improves provided by the invention is set up a monument the PCB manufacture method of phenomenon, routing interconnect form also by improveing pad optimizes the wire laying mode of PCB, in prior art, in PCB pad design, the direct auxiliary copper connection handling in both sides, accurately cannot control the size of pad both sides copper, usually because the copper device both sides radiating effect that causes not of uniform size of device connection is inconsistent, cause the melting speed of tin cream on pad inconsistent, finally produce phenomenon of setting up a monument; The cabling of pad is then designed to cross or yi word pattern by the application, the cabling quantity of pad both sides, size and dimension are consistent, make device two ends thermal conduction path size, shape consistent, heat-transfer effect is identical, thus decrease the difference of device two ends tin cream melting speed, effectively reduce device further to set up a monument the generation of phenomenon, reduce production cost.
Accompanying drawing explanation
In order to make content of the present invention be more likely to be clearly understood, below according to a particular embodiment of the invention and by reference to the accompanying drawings, the present invention is further detailed explanation, wherein
Fig. 1 be of the present invention improve element set up a monument phenomenon PCB manufacture method in the structural representation of pad and tin paste layer;
Fig. 2 be the present invention improve element set up a monument phenomenon PCB manufacture method in cross interconnected cabling form schematic diagram;
Fig. 3 be the present invention improve element set up a monument phenomenon PCB manufacture method in yi word pattern interconnected cabling form schematic diagram
In figure, Reference numeral is expressed as: 1-pad; 2-layer of solder paste; 3-interconnect traces.
Embodiment
Embodiment
Present embodiments provide a kind of element that improves to set up a monument the PCB manufacture method of phenomenon, it comprises the following steps:
S1, on PCB, make two pads 1 at counter element two ends, for welding described element, two described pads 1 are symmetrical arranged along the center line of described element, and two described pads 1 is measure-alike;
S2, as shown in Figure 1, make layer of solder paste 2 on described pad 1 surface, described layer of solder paste 2 size is less than described pad 1 size 1-2mil, the little 1.5mil of size more described pad 1 size of layer of solder paste 2 described in the present embodiment;
The wire laying mode of S3, optimization PCB:
A. the magnitude of current of the interconnected cabling 3 determined by described element is measured;
B. determine the interconnection form of described interconnected cabling 3, as Figure 2-3, the interconnection form of described interconnect traces 3 can be at all identical cross or yi word pattern of two pad 1 both sides size and dimensions.
Obviously, above-described embodiment is only for clearly example being described, and the restriction not to execution mode.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here exhaustive without the need to also giving all execution modes.And thus the apparent change of extending out or variation be still among the protection range of the invention.
Claims (6)
1. improve element to set up a monument the PCB manufacture method of phenomenon, it is characterized in that, comprise the following steps:
S1, on PCB, make two pads at counter element two ends, two described pads are symmetrical arranged along the center line of described element;
S2, make layer of solder paste in described bond pad surface, described layer of solder paste size is less than described pad size;
The wire laying mode of S3, optimization PCB.
2. the element that improves according to claim 1 is set up a monument the PCB manufacture method of phenomenon, and it is characterized in that, described step S3 comprises the following steps:
A. the magnitude of current of the interconnected cabling by described element is determined;
B. the interconnection form of described interconnected cabling is determined.
3. the element that improves according to claim 2 is set up a monument the PCB manufacture method of phenomenon, and it is characterized in that, the interconnection form of described interconnected cabling is cross or yi word pattern.
4. the element that improves according to claim 3 is set up a monument the PCB manufacture method of phenomenon, it is characterized in that, two described pad both sides interconnect traces consistent size.
5. the improvement element according to any one of claim 1-4 is set up a monument the PCB manufacture method of phenomenon, it is characterized in that, the little 1-2mil of described layer of solder paste single side size more described pad single side size.
6. the element that improves according to claim 5 is set up a monument the PCB manufacture method of phenomenon, and it is characterized in that, two described pad sizes at described element two ends are consistent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510483707.7A CN105208792A (en) | 2015-08-07 | 2015-08-07 | PCB manufacturing method for preventing tombstoning effect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510483707.7A CN105208792A (en) | 2015-08-07 | 2015-08-07 | PCB manufacturing method for preventing tombstoning effect |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105208792A true CN105208792A (en) | 2015-12-30 |
Family
ID=54956116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510483707.7A Pending CN105208792A (en) | 2015-08-07 | 2015-08-07 | PCB manufacturing method for preventing tombstoning effect |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105208792A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019024351A1 (en) * | 2017-07-31 | 2019-02-07 | 郑州云海信息技术有限公司 | Pcb board design method for avoiding surface element tombstoning, and packaging method and pcb board |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005347541A (en) * | 2004-06-03 | 2005-12-15 | Denso Corp | Structure for mounting chip component on circuit board |
| CN101145416A (en) * | 2006-09-15 | 2008-03-19 | 富葵精密组件(深圳)有限公司 | Surface Mount Electronic Components |
| US20080316724A1 (en) * | 2007-06-22 | 2008-12-25 | Delta Electronics, Inc. | Universal solder pad |
| CN101795533A (en) * | 2009-12-11 | 2010-08-04 | 福建星网锐捷网络有限公司 | Circuit board and copper-spreading method thereof |
| CN204102892U (en) * | 2014-06-30 | 2015-01-14 | 广东美的集团芜湖制冷设备有限公司 | The pad structure of SMT component and wiring board |
-
2015
- 2015-08-07 CN CN201510483707.7A patent/CN105208792A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005347541A (en) * | 2004-06-03 | 2005-12-15 | Denso Corp | Structure for mounting chip component on circuit board |
| CN101145416A (en) * | 2006-09-15 | 2008-03-19 | 富葵精密组件(深圳)有限公司 | Surface Mount Electronic Components |
| US20080316724A1 (en) * | 2007-06-22 | 2008-12-25 | Delta Electronics, Inc. | Universal solder pad |
| CN101795533A (en) * | 2009-12-11 | 2010-08-04 | 福建星网锐捷网络有限公司 | Circuit board and copper-spreading method thereof |
| CN204102892U (en) * | 2014-06-30 | 2015-01-14 | 广东美的集团芜湖制冷设备有限公司 | The pad structure of SMT component and wiring board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019024351A1 (en) * | 2017-07-31 | 2019-02-07 | 郑州云海信息技术有限公司 | Pcb board design method for avoiding surface element tombstoning, and packaging method and pcb board |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151230 |
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| RJ01 | Rejection of invention patent application after publication |