CN105224485A - A kind of method of reseptance of pervasive serial data and device - Google Patents

Abstract

Method provided by the invention and device, the serial data not adding the reception any physical layer protocol of differentiation that can be pervasive, comprise synchronous serial data and asynchronous serial data, only need the serial data signal limited range enlargement received and postpone, do not have complicated mimic channel, circuit structure is simple and reliable and be easy to realize, and the maximum clock frequency of flip-flop circuit is exactly the maximum data transfer rate, low cost, high-performance, universality, make it can be used to high speed transmission data widely.

Description

A kind of method of reseptance of pervasive serial data and device

Technical field

The present invention relates generally to method of reseptance and the device of serial data (0000), such as synchronous serial data (0001) method of reseptance and device, asynchronous serial data (0002) method of reseptance and device etc., comprise method and the device of the data receiver of the memory interface of computer system, external bus interface, external apparatus interface, wired network interface, fiber optic network interface etc.Specifically, the method that the serial data (0000) that the present invention relates to a kind of high speed receives and device, based on the method and device, the interface arrangement of the synchronous of low cost, high-performance, single channel or hyperchannel, single-ended drive or differential driving etc. or asynchronous serial data communication can be realized, the pervasive demand meeting high-speed data transfer.

Background technology

Serial data communication is one of basic means reducing data transmission cost, early stage serial data communication communicates based on the asynchronous serial data of low speed (0002), the impact of the difference on the frequency of tranmitting data register and receive clock is less, for improving message transmission rate, transmission clock communicates with the synchronous serial data (0001) of data and is used simultaneously, add the data transfer demands that cost is also difficult to meet higher rate, clock embeds and recovery technology makes synchronous serial communication no longer need transfer clock, also make the message transmission rate of serial data communication higher, but needing to continue to transmit data keeps clock recovery circuitry in running order, many bit moduli converter of high sampling rate is adopted also to be one of method receiving serial data at present.

The invention provides method of reseptance and the device of a kind of serial data (0000), both can realize synchronous serial data (0001) to receive, the asynchronous serial data (0002) of the same high message transmission rate that also can realize communicating with synchronous serial data (0001) communicates.

Accompanying drawing explanation

Below first the accompanying drawing of instructions of the present invention is simply introduced, and then in conjunction with these accompanying drawings, each enforcement example of the present invention is introduced, principle of the present invention and feature are described.

In figures in the following:

Fig. 1 is preferred embodiment measured signal (0010) SI and frequency divider (0110) circuit of inhibit signal (0070) SD and the schematic diagram of sequential that realize according to method of the present invention;

Fig. 2 is synchronized sampling (0220) circuit of preferred embodiment trigger (0200) to measured signal (0010) SI and inhibit signal (0070) SD and the schematic diagram of sequential that realize according to method of the present invention;

Fig. 3 is the time diagram of the output es1x (esMxP, es1xN) of preferred embodiment 3 bit SI PO shift register (0210) realized according to method of the present invention;

Fig. 4 is the schematic diagram of the judging circuit (0240) of output es1x (es1xP, es1xN) relative timing (0230) of the preferred embodiment synchronized sampling (0220) realized according to method of the present invention.

Fig. 5 is the schematic diagram of a kind of general central processing unit (CPU) of preferred embodiment realized according to method of the present invention.

Fig. 6 is the schematic diagram of a kind of asynchronous serial data interface memory chip of preferred embodiment realized according to method of the present invention.

Fig. 7 is the schematic diagram of the storeies such as preferred embodiment a kind of DRAM/SDRAM or SRAM or FLASH realized according to method of the present invention and module controller.

Fig. 8 is the preferred embodiment that realizes according to the method for the present invention schematic diagram based on the interface controller of the computer peripheral of UART Physical layer.

Fig. 9 is that the preferred embodiment realized according to method of the present invention adopts the data of USRT or UART Physical layer to transmit the schematic diagram of relay.

Figure 10 is the preferred embodiment that realizes according to the method for the present invention schematic diagram based on the system area network switch of USRT or UART physical layer protocol.

Figure 11 is the network switch for computer of preferred embodiment based on USRT or UART physical layer protocol and/or the schematic diagram of router that realize according to method of the present invention.

Figure 12 is the communication network switch of preferred embodiment based on USRT or UART physical layer protocol and/or the schematic diagram of router that realize according to method of the present invention.

Embodiment

First method of the present invention and device are described below, then the preferred embodiment of application the inventive method and device is described.

In the following description, serial data (0000) signal of arranging to receive is measured signal (0010), represents measured signal with SI (SIP, SIN).

In the following description:

1, signal upset (0020, transition) be that a digital signal is from low level (L) to high level (H) or from high level (H) to the Rapid Variable Design of low level (L), overturning from low level (L) to the signal of high level (H) is upset (0026 of rising, risetransition), overturning from high level (H) to the signal of low level (L) is the upset (0028, falltransition) that declines;

2, the deration of signal (0030) refers to that a digital signal is in low level (L) or is in the duration of high level (H);

3, the signal period (0040) refers to that adjacent twice rising of a digital signal overturns the time interval between (0026) or adjacent twice decline upset (0028);

4, the signal mentioned in the present invention can be all single-ended signal or both-end differential signal, is not all distinguished in whole supporting paper;

5, in the initial title representing a specific meanings with boldface type (label) of each paragraph, in same paragraph, the title of this specific meanings is only represented subsequently with boldface type.

One, the method for reseptance of pervasive serial data and device

This section illustrates method of reseptance and the device of pervasive serial data (0000) of the present invention.

Method of the present invention described below and device are applicable to the serial data (0000) that arbitrary form sends, and therefore repeat no more sending method and the device of the serial data that it relates to.

The tranmitting data register cycle (0050) is represented with TXT, the receive clock cycle (0060) is represented with RXT, receive clock is four clock AK (AKP, AKN), BK (BKP, BKN), CK (CKP, CKN), DK (DKP, DKN), their cycle is all RXT, the time delay time difference of AK and BK, BK and CK, CK and DK, DK and AK is all RXT/4, TXT and RXT approximately equal, TXT dynamic changes, and during TXT change, RXT also must change thereupon.

Measured signal (0010) both can be the electric signal after directly receiving and processing, also can be opto-electronic conversion and the electric signal after processing, measured signal is processed into serial data signal SI (SIP, and inhibit signal (0070) SD (SDP SIN), SDN), SD has an appointment relative to SI the delay of RXT/8, with latch (0100, latch) frequency divider (0110) formed is respectively by SI and SD frequency division, must ensure that frequency division output (0120) of SI and SD has and stablize the constant time delay time difference (0130) about RXT/8, use trigger (0200 respectively again, flip-flop) the 3 bit SI PO shift register (0210 formed, shift-register) synchronized sampling (0220) is carried out to the frequency division output of SI and SD, export with each frequency division of four phase clocks to SI and SD respectively and carry out synchronized sampling, the selection of divide ratio (0140) must ensure that four phase clocks all can overturn (0020) by each signal of exporting to frequency division of synchronized sampling, generally divide ratio is 2 namely can to meet the demands, but then need divide ratio to be 4 when signal distortion is serious, larger divide ratio has larger realizing cost and realize difficulty, introducing SD signal is obtain to adopt four phase clocks to carry out synchronized sampling the equivalent result that employing eight phase clock carries out synchronized sampling.

Fig. 1 carries out except frequency divider (0110) circuit of 2 frequency divisions and the schematic diagram of sequential for what realized by four latchs (0100) to SI and SD, this circuit carries out 2 frequency divisions to SI and SD respectively, ensure that the output of two frequency dividers has simultaneously and stablize the constant time delay time difference (0130) RXT/8, signal RI (the RIP of rising upset (0026) of corresponding measured signal (0010), RIN), signal FI (the FIP of decline upset (0028) of corresponding measured signal, FIN), signal RD (the RDP of the rising upset of corresponding inhibit signal (0070), RDN), signal FD (the FDP of the decline upset of corresponding inhibit signal, FDN), for concise description, measured signal SI is painted as has the equal deration of signal (0030) and signal period (0040), in fact the deration of signal of measured signal SI and signal period often unequal and random variation, the situation of inhibit signal SD is identical.

Fig. 2 is trigger (0200 of the present invention, flip-flop) SI and SD is carried out to circuit and the time diagram of synchronized sampling (0220), xK (xKP, xKN) AK is represented, BK, CK, one of DK etc. four phase clock, x is A, B, C, D represents that the clock carrying out sampling is AK respectively, BK, CK, DK, es (esP, esN) be RI, FI, RD, one of signals such as FD, e is R, F represents that input signal is Rs respectively, Fs etc., s is I, D represents that input signal is eI respectively, eD etc., trigger (0200/0:2) forms 3 bit SI PO shift register (0210), its parallel output signal is esMx (esMxP respectively, esMxN), M is 0, 1, 23 outputs representing shift register respectively.

Fig. 3 is the time diagram of the output es1x (esMxP, es1xN) of 3 bit SI PO shift register (0210), the output es0x (es0xP, es0xN) of shift register is unstable, the output es2x (es2xP, es2xN) of shift register postpones 1 receive clock cycle RXT relative to es1x (es1xP, es1xN) respectively, be used to latch and export data, the figure place of shift register increases by 1 or 2 can more reliable synchronized sampling.

Fig. 4 is the output es1x (es1xP of synchronized sampling of the present invention (0220), es1xN) schematic diagram of the judging circuit (0240) of relative timing (0230), es1A and es1C is mutually respectively in rising edge and negative edge sampling, es1B and es1D is mutually respectively in rising edge and negative edge sampling, table 1 is mutual sample states table, wherein L/H and H/L represents that the positive terminal/end of oppisite phase of esUx and esDx exports respectively, esUA and esUC, esUB and esUD, esDA and esDC, the level of esDB and esDD etc. is always different, 0, 1, 2, other state outside 3 states is error condition.Also es2x (es2xP, es2xN) can be selected to carry out relative timing differentiation.

The mutual sample states table of table 1, es1x (es1xP, es1xN) signal

Because eD signal is about RXT/8 relative to the eI signal delay of correspondence, advanced about RXT/8 is equivalent to the synchronized sampling of eI signal, therefore RIUx and RDUx to the synchronized sampling (0220) of eD signal, FIUx and FDUx, RIDx and RDDx, FIDx and FDDx etc. form RI rising edge respectively, FI rising edge, RI negative edge, the equivalence eight phase clock synchronized sampling of FI negative edge, with A, B, C, D represents RIUx, FIUx, RIDx, the four phase clock relative timings (0230) of FIDx, with a, b, c, d represents RDUx, FDUx, RDDx, the four phase clock relative timings of FDDx, then the change of eight phase clock relative timings is aAbBcCdD, AbBcCdDa, bBcCdDaA, BcCdDaAb, cCdDaAbB, CdDaAbBc, dDaAbBcC, DaAbBcCd etc., table 2 gives the present invention and selects to stablize the list of sampling clock according to eight phase clock relative timings, because the time delay time difference (0130) is an approximate value and unstable, with A in list, B, C, in D, the person of mediating is as stable sampling clock, if SD signal is left in the basket, time-sequencing then based on eIUx/eIDx is selected to stablize sampling clock, can one of the two phase clock that mediates of Stochastic choice, also can increase shift register Time Created (settime) St and retention time (holdtime) Ht as alternative condition, St >=Ht then selects the position of two phase clock the latter, and St < Ht then selects the position of two phase clock at the former.

Table 2, based on eight phase clock relative timings select stablize sampling clock list

Four free counters are set, respectively to four phase clock countings, respectively with the counting of the rising edge of eI1x/eI2x signal and free counter corresponding to negative edge sampling, the rising edge of eI1x/eI2x signal and the counting of negative edge acquisition is represented respectively with eNUx and eNDx, also independently counter can be adopted, the bit number of counter must ensure that counting overflows does not affect count results, obtain the clock count between adjacent eI1x/eI2x signal upset respectively, every phase clock is at each eI (eIP, eIN) there are 4 clock counts (0260) signal period (0250), with FNDx, RNUx, FNUx, RNDx is the order of 4 countings of each signal period, the sequence number of signal period is represented with k, table 3 gives the list selecting bit count (0270) to export based on stable sampling clock, each signal period exports 4 bit counts, the low level of the serial data (0000) received respectively, high level, low level, the lasting bit number of high level, bit count is exactly that method of the present invention and device receive and the serial data exported (0000), follow-up process is done based on serial data communication agreement for system.

Es2x (es2xP, es2xN) relative timing (0230) and the clock count (0260) of synchronous latch (0280) four phase clock is used to, esUT=es2A|es2B|es2C|es2D is that rising edge synch latches, esUx is synchronously latched output at the rising edge of esUT, eNUx is synchronously latched output at the rising edge of eIUT, esDT=es2A & es2B & es2C & es2D is that negative edge synchronously latches, esDx is synchronously latched output at the negative edge of esDT, eNDx is synchronously latched output at the negative edge of eDT.

If be there are not being the abnormal conditions of one of one of four states in table 1 in esUx and esDx that synchronously latch, may be then that SI and SD signal distortion is serious, improving input signal can make abnormal conditions disappear, also may be that judging circuit (0240) breaks down, improve input signal and abnormal conditions can not be made to disappear.

The introducing of above-mentioned inhibit signal (0070) is in order to system works works more reliably when maximum operation frequency, and when system works is in lower frequency, the importance of inhibit signal reduces and even can be left in the basket.

Table 3, the list selecting bit count to export based on stable sampling clock

Based on above-mentioned explanation, the method for reseptance of pervasive serial data (0000) of the present invention has following feature:

1, for arbitrary serial data communication agreement provides Physical layer to connect, comprise synchronous serial data communication and asynchronous serial data communication, multiple passage can be combined into hyperchannel and connect;

2, provide the cycle to be four phase clock AK, BK, CK, DK of RXT, AK, BK, CK, DK have the time delay time difference of RXT/4 successively, RXT and serial data tranmitting data register cycle T XT approximately equal, and TXT dynamic changes, and during TXT change, RXT also must change thereupon;

3, single-ended or difference measured signal both can be the electric signal after directly receiving and processing, also can be opto-electronic conversion and the electric signal after processing, measured signal is processed into serial data signal SI and inhibit signal SD thereof, SD and SI waveform is identical but postpone about RXT/8, the effect of SD is that system is worked more reliably near most I work RXT value, can be ignored when working under larger RXT value;

4, with latch respectively by SI and SD signal 2 frequency division or 4 frequency divisions, obtain signal FI and FD of signal RI and RD of 1 or 2 corresponding SI and SD rising upset, 1 or 2 corresponding SI and SD decline upset respectively, the upset of the signal such as RI with RD, FI with FD must keep have an appointment RXT/8 the same as SI and SD to postpone, and the effect of frequency division guarantees that AK, BK, CK, DK etc. all can collect the upset each time of the signals such as RI, RD, FI, FD;

5, by SI PO shift register respectively to RI, RD, FI, the signals such as FD carry out four phase clock synchronized samplings respectively, choose the 2nd or 3 or 4 RIx of the parallel output of four phase clock sample shift register of same signal, RDx, FIx, FDx carries out time-sequencing respectively, and x is A, B, C, one of D expression corresponds respectively to AK, BK, CK, the synchronized sampling of one of DK clock, selects to stablize sampling clock, with A based on time-sequencing, B, C, D represents RI, the time-sequencing of FI signal synchronized sampling, with a, b, c, d represents RD, the time-sequencing of FD signal synchronized sampling, to RD, the synchronized sampling of FD signal be equivalent in advance the about RXT/8 time to RI, the synchronized sampling of FI signal, is namely equivalent to RI, FI signal carries out eight phase clock synchronized samplings, and the time-sequencing of eight phase clock synchronized samplings has aAbBcCdD, AbBcCdDa, bBcCdDaA, BcCdDaAb, cCdDaAbB, CdDaAbBc, dDaAbBcC, DaAbBcCd etc. eight kinds sequence, corresponding stable sampling clock is BK, CK, CK, DK, DK, AK, AK, when BK etc., SD signal is left in the basket, the time-sequencing of four phase clock synchronized samplings has ABCD, BCDA, CDAB, DABC etc. four kinds sequence, can one of the two phase clock that mediates of Stochastic choice as stablizing sampling clock, i.e. BK/CK, CK/DK, DK/AK, AK/BK etc., also can increase Time Created of shift register and retention time as alternative condition, when Time Created is more than or equal to the retention time, and corresponding selection CK respectively, DK, AK, BK, when Time Created is less than the retention time, corresponding selection BK respectively, CK, DK, AK, each RI, the upset of FI signal has a corresponding stable sampling clock,

6, obtain respectively RIx upset and FIx following closely overturn between in-phase clock count value RNx, FIx overturn and RIx following closely overturn between in-phase clock count value FNx, corresponding stable sampling clock xK is overturn respectively based on RI upset and FI, select corresponding RNx and FNx as output RNQ and FNQ respectively, RNQ and FNQ is exported according to chronological order sequence alternate, the permanent High level bit number of the serial data that RNQ correspondence receives, the lasting low level bit number of the serial data that FNQ correspondence receives.

Based on method and the device of the invention described above, the serial data (0000) of any agreement of the reception not adding differentiation that can be pervasive, comprise synchronous serial data (0001) and asynchronous serial data (0002), only need the serial data signal limited range enlargement received and postpone, there is no complicated mimic channel, circuit structure simple and reliable and be easy to realize, the maximum clock frequency of trigger (0200) circuit is exactly the maximum data transfer rate, low cost, high-performance, universality etc., make it can be used to high speed transmission data widely.

Two, the sending method of asynchronous serial data and device

This section illustrates sending method and the device of asynchronous serial data of the present invention (0002).

Transmission channel (2000) with transmission frame (2010) for unit sends data, the idle bit (2020) of any amount that can be zero can be inserted between adjacent transmission frame, transmission frame is by 1 initial bits (2022), N number of content bits (2024) of following by variable amounts, bit (2026) is stopped to terminate by 1, the useful signal level of initial bits and stopping bit is different, idle bit is identical with stopping the useful signal level of bit, if initial bits is that high level is effective, then bit and idle bit is stopped to be Low level effectives, if initial bits is Low level effective, then bit and idle bit is stopped to be that high level is effective, the signal of transmission channel can be single-ended signal or both-end differential signal.

In transmission frame (2010), the intension of N number of content bits (2024) is any, can be market bit (2030), data bit (2032), Command field bit (2034), check bit (2036), alignment bit (2038), exchange bit (2040) etc. multiple, if define the market bit of 1 bit, then transmission frame (2010) is divided into the command frame (2014) not having the Frame of Command field bit (2012) and do not have data bit, the bit number of other kind content bits can be 0 or 1 or multiple, content bits can be original data or order, also can be that scrambling is carried out to original data or order, encryption, the result of coding etc. process, check bit makes data receiver can find error of transmission in real time, alignment bit is the alignment sequence number (2050) that periodic cycle adds a change, be used for alignment assembling combined frames (2016) by data receiver, exchange bit is the destination address (2060) in particular range, the realization that switch can be simple and direct is made to exchange transmission (2070), destination address can be subdivided into multiple hierarchical address (2062), be applicable to multistage exchange (2072) transmission.

Multiple transmission channel (2000) can form combination passage (2100), there is delay variance (2110) time that the transmission frame (2010) that the multiple transmission channels combining passage send simultaneously arrives receiving end, therefore need alignment measure (2120) ensure combination passage whole transmission frames can be correct be combined into a combined frames (2120), several alternative preferred alignment measure of the present invention is as follows:

1, each transmission channel (2000) being combination passage (2100) at data sending terminal arranges a transmission lag (2112), with the transmission lag that the cycle of tranmitting data register or semiperiod are each transmission channel in chronomere's control and adjustment combination passage, make delay variance (2110) little as far as possible, data receiver needs transfer delay difference and informs data receiver, and data receiver also needs to take measures to guarantee that delay variance does not affect the correct combination of combination bag.

2, to determine or the uncertain time interval, data sending terminal sends the alignment command frame (2014) that comprises alignment bit (2038), and data receiver receives after alignment command frame (2014) according to the transmission frame (2010) in alignment bit again align data buffer zone.

3, the transmission channel (2000) that the method for item 1 is applicable to combine passage (2100) concentrates situation on a single chip, and the transmission channel that the method for item 2 is applicable to combine passage is distributed in the situation on multiple chip.

When transmitting data continuously at set intervals, the idle bit (2020) of some is inserted between transmission frame (2010), perform the equipment that relaying transmits, as repeater (repeater), switch (switch) etc., can by increasing or reduce the quantity of idle bit, with the frequency difference of the tranmitting data register and datum target receive clock that adapt to Data Source, the data buffer of the receiving equipment making clock frequency lower avoids overflowing.

Three, the method for reseptance of asynchronous serial data and device

This section illustrates method of reseptance and the device of asynchronous serial data of the present invention (0002).

In this instructions " sending method of asynchronous serial data and device " part, describe and start with initial bits (2022), content bits (2024) is placed in the middle, stop bit (2026) to bring up the rear and form transmission frame (2010), between transmission frame, insertion can be the sending method of the asynchronous serial data (0002) of the idle bit (2020) of any amount of zero, can with the method receiving asynchronous serial data described in this instructions " method of reseptance of pervasive serial data and device " part, provide method and the device of special receiving asynchronous serial data of the present invention here again.

In this section the following description, agreement initial bits (2022) significant level is low level L, stop that bit (2026) and idle bit (2020) significant level are high level H, content bits (2024) number is variable Integer N, content bits transmits from bit 0, by initial bits, stop the significant level of bit and idle bit to exchange, method of the present invention can not change thereupon.

The same with this instructions " method of reseptance of pervasive serial data and device " part, the tranmitting data register cycle (0050) is represented with TXT, the receive clock cycle (0060) is represented with RXT, receive clock is four clock AK (AKP, AKN), BK (BKP, BKN), CK (CKP, CKN), DK (DKP, DKN), their cycle is all RXT, the time delay time difference of AK and BK, BK and CK, CK and DK, DK and AK is all RXT/4, TXT and RXT approximately equal, TXT dynamic changes, and during TXT change, RXT also must change thereupon.

Measured signal (0010) both can be the electric signal after directly receiving and processing, also can be opto-electronic conversion and the electric signal after processing, measured signal is processed into serial data (0000) signal SI (SIP, SIN) and inhibit signal (0070) SD (SDP, SDN) thereof, SD and SI waveform is identical but postpone about RXT/8.

Different from the method that this instructions " method of reseptance of pervasive serial data and device " part illustrates, the method of frequency division is not adopted to produce by the signal of synchronized sampling, but start M signal (3000) rxTask and middle time delay (3010) dxTask with the initial bits (2022) of the asynchronous serial data received (0002) signal SI and inhibit signal (0070) SD thereof, the forward position of dxTask postpones about RXT/8 relative to the forward position of rxTask, the receiving course of the initial transmission frame (2010) in forward position of rxTask, the significant level of rxTask with dxTask is identical with stopping the significant level of bit (0226) with initial bits respectively with inactive level, rxStop signal effectively makes rxTask and dxTask get back to inactive level, be ready to receive next transmission frame, the significant level of rxStop is identical with the significant level of initial bits with stopping bit respectively with inactive level.

Table 4 produces by the Verilog coded description of synchronized sampling (0220) signal rxTask and dxTask when being asynchronous serial data (0002) receptions.

The Verilog coded description of table 4, generation rxTask and dxTask signal

Use trigger (0200 respectively, flip-flop) SI PO shift register (0210) formed carries out four phase clock synchronized samplings (0220) to rxTask and dxTask respectively, XK (XKP, XKN) AK is represented, BK, CK, one of DK etc. four phase clock, X is A, B, C, D represents that the clock carrying out synchronized sampling is AK respectively, BK, CK, DK, rxTaskX [3:0] and dxTaskX [1:0] is the output of the synchronized sampling shift register of one of corresponding four phase clocks respectively, the progression of shift register increases by 1 or 2 can more reliable synchronized sampling.Verilog coded description to rxTask and dxTask synchronized sampling (0220) when table 5 is asynchronous serial data (0002) receptions.

The Verilog coded description of synchronized sampling when table 5, asynchronous serial data receive

The Verilog coded description that the sampling time sequence carrying out four phase clock synchronized samplings (0220) to rxTask and dxTask signal when table 6 is asynchronous serial data (0002) receptions differentiates, based on sampling time ranking results, choose sampling clock corresponding to the sampling that mediates as stable sampling clock, the input data of this phase sampler clock acquisition are exactly the asynchronous serial data received.

Because dxTask signal is about RXT/8 relative to rxTask signal delay, advanced about RXT/8 is equivalent to the synchronized sampling of rxTask signal to the synchronized sampling (0220) of dxTask signal, therefore rxTaskX and dxTaskX forms the equivalence eight phase clock synchronized sampling to the forward position of rxTask, with A, B, C, D represents the four phase clock relative timings (0230) in rxTask forward position, with a, b, c, d represents the four phase clock relative timings in dxTask forward position, then the change of eight phase clock relative timings is aAbBcCdD, AbBcCdDa, bBcCdDaA, BcCdDaAb, cCdDaAbB, CdDaAbBc, dDaAbBcC, DaAbBcCd etc.

Table 6 gives eight phase clock relative timing (0230) sequences of the present invention and selects to stablize the Verilog coded description of sampling clock, because the time delay time difference (0130) is an approximate value and unstable, with A in list, B, C, in D, the person of mediating is as stable sampling clock, if SD signal is left in the basket, time-sequencing then based on rxTadkX is selected to stablize sampling clock, can one of the two phase clock that mediates of Stochastic choice, also can increase shift register Time Created (settime) St and retention time (holdtime) Ht as alternative condition, St >=Ht then selects the position of two phase clock the latter, St < Ht then selects the position of two phase clock at the former.

In table 6, rxOrder is the result that relative timing (0230) sorts, and rxClock is the selection result of stable sampling clock, and when rxClock is respectively 0,1,2,3, corresponding stable sampling clock is AK, BK, CK, DK respectively.

The Verilog coded description that sampling clock differentiates is stablized in when table 6, asynchronous serial data receive

The Verilog coded description of data sampling (3020) when table 7 is asynchronous serial data (0002) receptions, parameter rxBits is wherein exactly the bit number N of content bits (2024), parameter rxBnum is the bit number of content bits counter, rxShiftX is N+2 position SI PO shift register (0210) of the data sampling of asynchronous serial data SI, the figure place of this shift register increases by 1 or 2 and can obtain more reliable data sampling, rxBcntX is data sampling counter, rxTcntX is data sampling count end signal, rxStopX is that transmission frame (2010) receives end signal, rxTrigX is asynchronous serial data latch signal, the time interval between the rear edge of rxTrigX and the forward position of the 2nd of the parallel output of synchronized sampling rxTask signal shift register is N+2 receive clock cycle, this time interval also corresponding increase when the number of shift register position increases, asynchronous serial data is latched on the rear edge of rxTrigX, rxData is the content bits latched, rxDssX is the stopping bit (2026) and initial bits (2022) that latch, X is respectively A, B, C, D etc. represent and AK, BK, CK, the data sampling that DK isochronon is corresponding.

RxStop is the end signal that a transmission frame (2010) finishes receiving, it makes rxTask and dxTask reset, be ready to receive next transmission frame, the rxDataX corresponding with stable receive clock XK is exactly content bits (2024) rxData of the asynchronous serial data (0002) received, stablizing rxDssX corresponding to receive clock XK should be 2 ' b10, then represent that reception synchronously makes mistakes if not 2 ' b10, sending direction take over party sends the idle bit (2020) more than rxBits+2 continuously, namely take over party can be made to recover normal synchronized state, take over party loses synchronous method for optimizing and has two kinds: one to be the idle bit (2020) that receive direction transmit leg sends continuously more than rxBits+2 to allow transmit leg learn, two is that receive direction transmit leg sends status frames (3030) reporting errors.

The Verilog coded description of data sampling when table 7, asynchronous serial data receive

Based on above-mentioned explanation, asynchronous serial data of the present invention (0002) method of reseptance has following feature:

1, multiple passage can be combined into hyperchannel and connect, each passage transmits data in units of transmission frame, transmission frame starts with 1 initial bits, N number of content bits of dynamically changeable is placed in the middle, 1 stops bit bringing up the rear formation, between transmission frame, insertion can be the idle bit of any amount of zero, the significant level of initial bits is different with the significant level of stopping bit, the significant level of idle bit is identical with stopping the significant level of bit, the implication of content bits is any, initial bits is interchangeable with the significant level of stopping bit and idle bit, continuous transmission can make take over party regain synchronously more than N+2 idle bit, when transmitting data continuously at set intervals, the idle bit of some is inserted between transmission frame, perform the equipment that relaying transmits, as repeater, switch etc., can by increasing or reduce the quantity of idle bit, with the frequency difference of the tranmitting data register and datum target receive clock that adapt to Data Source, the data buffer of the receiving equipment making clock frequency lower avoids overflowing,

2, provide the cycle to be four phase clock AK, BK, CK, DK of RXT, AK, BK, CK, DK have the time delay time difference of RXT/4 successively, RXT and serial data tranmitting data register cycle FXT approximately equal, and TXT dynamic changes, and during TXT change, RXT also must change thereupon;

3, measured signal that is single-ended or difference both can be the electric signal after directly receiving and processing, also can be opto-electronic conversion and the electric signal after processing, measured signal is processed into serial data signal SI (SIP, SIN) and inhibit signal SD (SDP, SDN) thereof, SD and SI waveform is identical but postpone about RXT/8, the effect of SD is that system is worked more reliably near most I work RXT value, can be ignored when working under larger RXT value;

4, M signal rxTask and dxTask is produced based on SI and SD signal, rxTask and dxTask respectively in the forward position of the initial bits of SI and SD signal by stopping bit significant level to be turned to initial bits significant level, rxTask and dxTask is turned to by initial bits significant level when the stopping bit of SI signal arrives simultaneously and stops bit significant level, the forward position upset of rxTask with dxTask must keep have an appointment RXT/8 the same as SI and SD to postpone, rear being in after its upset of upset palpus guarantee of rxTask and dxTask stops bit significant level until stop bit terminating and do not affect its forward position of following initial bits overturning next time,

5, respectively four phase clock synchronized samplings are carried out respectively to rxTask and dxTask signal by SI PO shift register, choose the parallel output of four phase clock sample shift register of same signal the 2nd or 3 or 4 carry out time-sequencing as rxTaskX and dxTaskX, X is A, B, C, one of D expression corresponds respectively to AK, BK, CK, the synchronized sampling of one of DK clock, selects to stablize sampling clock, with A based on time-sequencing, B, C, D represents the time-sequencing to rxTask signal synchronized sampling, with a, b, c, d represents the time-sequencing to dxTask signal synchronized sampling, to the synchronized sampling of dxTask signal be equivalent in advance the about RXT/8 time to the synchronized sampling of rxTask signal, namely be equivalent to and carry out eight phase clock synchronized samplings to rxTask signal, the time-sequencing of eight phase clock synchronized samplings has aAbBcCdD, AbBcCdDa, bBcCdDaA, BcCdDaAb, cCdDaAbB, CdDaAbBc, dDaAbBcC, DaAbBcCd etc. eight kinds sequence, corresponding stable sampling clock is BK, CK, CK, DK, DK, AK, AK, when BK etc., SD signal is left in the basket, the time-sequencing of four phase clock synchronized samplings has ABCD, BCDA, CDAB, DABC etc. four kinds sequence, can one of the two phase clock that mediates of Stochastic choice as stablizing sampling clock, i.e. BK/CK, CK/DK, DK/AK, AK/BK etc., also can increase Time Created of shift register and retention time as alternative condition, when Time Created is more than or equal to the retention time, and corresponding selection CK respectively, DK, AK, BK, when Time Created is less than the retention time, corresponding selection BK respectively, CK, DK, the forward position upset of AK, each rxTask has a corresponding stable sampling clock,

6, with N+2 bit SI PO shift register rxShiftX, four phase clock synchronized samplings are carried out respectively to SI signal, the minimum N+2 bit of the parallel output of this shift register and N+2, the upset interval, forward position of the 2nd the receive clock cycle place of parallel output of shift register of synchronized sampling rxTask be latched as rxDataX, the figure place of this shift register increases by 1 or 2 and can obtain more reliable data sampling, when the figure place of shift register increases, latch the time interval also corresponding increase of rxDataX, based on the stable sampling clock XK that rxTask forward position upset synchronized sampling time-sequencing is determined, corresponding rxDataX is selected to export as the asynchronous serial data rxData received, minimum and the highest-order bit of rxData is initial bits respectively and stops bit, data in rxData between minimum and the highest-order bit are content bits.

Based on method and the device of the invention described above, can the asynchronous serial data (0002) of any agreement of reception of minimum cost, also synchronous serial data (0001) communication of any agreement can be realized in an asynchronous manner, only need the serial data signal limited range enlargement received and postpone, there is no complicated mimic channel, circuit structure simple and reliable and be easy to realize, the maximum clock frequency of trigger (0200) circuit is exactly the maximum data transfer rate, low cost, high-performance, the features such as universality, make it can be used to high speed transmission data widely.

Four, the application of Serial data receiving method and device

This section illustrates the application of serial data (0000) transceiver realized based on method of the present invention and device.

In explanation above, The present invention gives method of reseptance and the device of two kinds of serial datas (0000), method and the device of serial data transmission are relatively simple, the method of Serial data receiving then more complicated and be difficult to realize, method provided by the invention and device, simplify the structure of Serial data receiving device to greatest extent, make it with low cost and be easy to realize, and not only can meet high performance application demand, also can meet the application demand of low cost and low-power consumption.

For concise description, with the serial data communication device that the method that USRT (UniversalSerialReceievr/Transmitter) calls this instructions " method of reseptance of pervasive serial data and device " part realizes, the serial data communication device realized by the method that UART (UniversalAsynchronousReceiever/Transmitter) calls this instructions " method of reseptance of asynchronous serial data and device " part.

Merogenesis is illustrated the application of the inventive method below.

(1) the synchronous serial data communication on asynchronous serial data communication Physical layer

The method adopting this instructions " method of reseptance of asynchronous serial data and device " part to describe and device, the asynchronous serial data (0002) of same high data rate of can realizing communicating with synchronous serial data (0001) communicates, therefore can on the Physical layer of asynchronous serial data communication, realize data link layer and the layer protocols of synchronous serial data communication, reduce power consumption and the cost of interface, the feature of this method is as follows:

1, as the method for this instructions " method of reseptance of asynchronous serial data and device " part description and the physical layer protocol of device realization reception and transmission asynchronous serial data;

2, the synchronous serial data of data link layer and protocol layer sends as the content bits of the asynchronous serial data of Physical layer;

The content bits of the asynchronous serial data of the Physical layer 3, received submits to data link layer and the protocol layer of synchronous serial data communication;

4, each port is made up of one or one group of asynchronous serial data passage.

(2) a kind of multi-purpose computer central processing unit

Current multi-purpose computer central processing unit (4200, CPU), there is multiple external interface, the method adopting this instructions " method of reseptance of pervasive serial data and device " and/or the part such as " method of reseptance of asynchronous serial data and device " and/or " the synchronous serial data communication on asynchronous serial data communication Physical layer " to describe and device, can realize only having two kinds of (USRT and UART) Physical layers even to only have the universal cpu of one (UART) Physical layer external interface, Fig. 5 gives the schematic diagram of the universal cpu adopting USRT and/or UART interface, at whole new definition or when adopting existing data link layer and layer protocols, the physical layer protocol of CPU external interface defines based on USRT or UART, physical layer protocol is only then better based on UART definition, the feature of this general central processor is as follows:

1, the inside structure of central processing unit is any, whole new definition framework or adopt existing framework;

2, the method described as this instructions " method of reseptance of pervasive serial data and device " and/or the part such as " method of reseptance of asynchronous serial data and device " and/or " the synchronous serial data communication on asynchronous serial data communication Physical layer " and device realize the reception of its unidirectional or two-way external interface and send the physical layer protocol of serial data;

3, whole new definition or adopt data link layer and the layer protocols of existing external interface;

4, operational order, write data, status data, the shared port of sense data of one way ports, operational order and the write data of bidirectional port are exported by output port by input port input, status data and sense data;

5, each port is made up of one or one group of pervasive serial data channel or asynchronous serial data passage.

(3) a kind of storer of asynchronous serial data interface

Current general external memory storage mainly contains DRAM/SDRAM (4300), SRAM (4310), FLASH (4320) etc., all adopt data that are parallel or serial and control interface, the method adopting this instructions " method of reseptance of asynchronous serial data and device " part to describe and device, the single port of UART physical layer interface or the DRAM/SDRAM of multiport can be realized, SRAM, FLASH etc., one or more universal cpus that can directly describe with this instructions " a kind of general central processing unit (CPU) " part are directly connected, Fig. 6 gives the DRAM/SDRAM adopting UART interface, SRAM, the schematic diagram of FLASH etc., the feature of this storer is as follows:

1, the framework of the inside of the storer such as DRAM/SDRAM or SRAM or FLASH is any, whole new definition framework or adopt existing framework;

2, the method described as this instructions " method of reseptance of asynchronous serial data and device " part and device realize the unidirectional or two-way reception of single port or multiport and send the physical layer protocol of asynchronous serial data;

3, whole new definition or adopt existing operational order and status information;

4, operational order, write data, status information, the shared port of sense data of one way ports, operational order and the write data of bidirectional port are exported by output port by input port input, status information and sense data;

5, each port is made up of one or one group of asynchronous serial data passage.

(4) a kind of Memory Controller of asynchronous serial data interface

Current general external memory storage mainly contains DRAM/SDRAM (4300), SRAM (4310), FLASH (4320) etc., all adopt data that are parallel or serial and control interface, the method adopting this instructions " method of reseptance of asynchronous serial data and device " part to describe and device, the single port of UART physical layer interface or the DRAM/SDRAM of multiport can be realized, SRAM, the controller of the storeies such as FLASH, one or more universal cpus that can directly describe with this instructions " a kind of general central processing unit (CPU) " part are directly connected, Fig. 7 gives the DRAM/SDRAM adopting UART interface, SRAM, the schematic diagram of the memory modules such as FLASH and controller, Memory Controller connects the storer such as DRAM/SDRAM and/or SRAM and/or FLASH in inside modules, external-connected port is the UART interface of single port or multiport, the feature of the controller of this storer is as follows:

1, any with the interface architecture of the storer such as DRAM/SDRAM or SRAM or FLASH, whole new definition framework or adopt existing framework;

2, the method described as this instructions " method of reseptance of asynchronous serial data and device " part and device realize the unidirectional or two-way reception of single port or multiport and send the physical layer protocol of asynchronous serial data;

3, whole new definition or adopt existing operational order and status information;

4, operational order, write data, status information, the shared port of sense data of one way ports, operational order and the write data of bidirectional port are exported by output port by input port input, status information and sense data;

5, each port is made up of one or one group of asynchronous serial data passage.

(5) a kind of interface controller of computer peripheral

Current general external apparatus interface mainly contains synchronous serial, run simultaneously, asynchronous parallel, asynchronous serial etc., the method adopting this instructions " method of reseptance of pervasive serial data and device " and/or " method of reseptance of asynchronous serial data and device " and/or " the synchronous serial data communication on asynchronous serial data communication Physical layer " part to describe and device, the external apparatus interface based on UART physical layer protocol can be realized, one or more universal cpus that can directly describe with this instructions " a kind of general central processing unit (CPU) " part are directly connected, Fig. 8 gives the schematic diagram of the interface controller of the computer peripheral based on UART Physical layer, the feature of this computing machine external interface is as follows:

1, the inside structure of external apparatus interface controller is any, whole new definition framework or adopt existing framework;

2, the method described as this instructions " method of reseptance of pervasive serial data and device " and/or the part such as " method of reseptance of asynchronous serial data and device " and/or " the synchronous serial data communication on asynchronous serial data communication Physical layer " and device realizes device controller and computer system is unidirectional or the reception that is bi-directionally connected and the physical layer protocol sending serial data;

3, whole new definition or adopt existing data link layer and layer protocols;

4, operational order, write data, status information, the shared port of sense data of one way ports, operational order and the write data of bidirectional port are exported by output port by input port input, status information and sense data;

5, each port is made up of one or one group of pervasive serial data channel or asynchronous serial data passage.

(6) a kind of relay of data transmission

Any one transmits the method for data, the ultimate range of its transmission is all restricted, if transmit farther distance, then need trunking refile data, the method adopting this instructions " method of reseptance of pervasive serial data and device " and/or the part such as " method of reseptance of asynchronous serial data and device " and/or " the synchronous serial data communication on asynchronous serial data communication Physical layer " to describe and device, can realize based on USRT or UART physical layer repeater, Fig. 9 gives the schematic diagram adopting the data of USRT or UART Physical layer to transmit relay, by trunk interface when keeping original data link layer and layer protocols, original Physical layer is replaced by USRT or UART, only replaced better by UART, the relay feature of this data transmission is as follows:

1, any by the framework of the data transfer interface of relaying, whole new definition framework or adopt existing framework;

2, the method described as this instructions " method of reseptance of pervasive serial data and device " and/or the part such as " method of reseptance of asynchronous serial data and device " and/or " the synchronous serial data communication on asynchronous serial data communication Physical layer " and device realize data and transmit the physical layer protocol of relaying;

3, keep by the data link layer of trunk interface and layer protocols constant;

4, data transmit relaying and are made up of one or one group of pervasive serial data channel or asynchronous serial data passage.

(7) a kind of switch of system area network

System area network is the data transport network of high-performance computer system inside, its performance and power consumption are all higher, the data transport network of the small server inside of small scale to uniprocessor, scale greatly to has the data transport network of the supercomputer inside of tens thousand of processors, in the computer system of multiprocessor, the core component that system area network switch is indispensable often, the method adopting this instructions " method of reseptance of pervasive serial data and device " and/or the part such as " method of reseptance of asynchronous serial data and device " and/or " the synchronous serial data communication on asynchronous serial data communication Physical layer " to describe and device, the system area network switch based on USRT or UART Physical layer can be realized, Figure 10 gives the schematic diagram of the system area network switch based on USRT or UART physical layer protocol, the feature of this system area network switch is as follows:

1, the inside structure of switch is any, whole new definition framework or adopt existing framework;

2, the method described as this instructions " method of reseptance of pervasive serial data and device " and/or the part such as " method of reseptance of asynchronous serial data and device " and/or " the synchronous serial data communication on asynchronous serial data communication Physical layer " and device realize the physical layer protocol of system domain exchange network;

3, whole new definition or adopt existing data link layer and layer protocols;

4, each port is made up of one or one group of pervasive serial data channel or asynchronous serial data passage.

(8) a kind of switch of computer network and/or router

Computer network is the data transport network between computing machine, small scale is to the data transport network of one family inside, there is the data transport network of tens thousand of computing machines scale greatly to university inside, Internet is then the computer network of a global area, switch and router are the necessary equipments of computer network, the method adopting this instructions " method of reseptance of pervasive serial data and device " and/or the part such as " method of reseptance of asynchronous serial data and device " and/or " the synchronous serial data communication on asynchronous serial data communication Physical layer " to describe and device, the network switch for computer based on USRT or UART Physical layer and/or router can be realized, Figure 11 gives the schematic diagram of network switch for computer based on USRT or UART physical layer protocol and/or router, the feature of this network switch for computer and/or router is as follows:

1, the inside structure of switch and/or router is any, whole new definition framework or adopt existing framework;

2, the method described as this instructions " method of reseptance of pervasive serial data and device " and/or the part such as " method of reseptance of asynchronous serial data and device " and/or " the synchronous serial data communication on asynchronous serial data communication Physical layer " and device realize the physical layer protocol of network exchange and/or route;

3, whole new definition or adopt existing data link layer and layer protocols;

4, each port is made up of one or one group of pervasive serial data channel or asynchronous serial data passage.

(9) a kind of switch of communication network or router

Communication network is the data transport network of global area, switch and router are the indispensable parts of communication network, the method adopting this instructions " method of reseptance of pervasive serial data and device " and/or the part such as " method of reseptance of asynchronous serial data and device " and/or " the synchronous serial data communication on asynchronous serial data communication Physical layer " to describe and device, the communication network switch based on USRT or UART Physical layer and/or router can be realized, Figure 12 gives the schematic diagram of communication network switch based on USRT or UART physical layer protocol and/or router, the feature of this communication network switch and/or router is as follows:

1, the inside structure of switch and/or router is any, whole new definition framework or adopt existing framework;

2, the method described as this instructions " method of reseptance of pervasive serial data and device " and/or the part such as " method of reseptance of asynchronous serial data and device " and/or " the synchronous serial data communication on asynchronous serial data communication Physical layer " and device realize the physical layer protocol of network exchange and/or route;

3, whole new definition or adopt existing data link layer and layer protocols;

4, each port is made up of one or one group of pervasive serial data channel or asynchronous serial data passage.

Claims (11)

1. the method for reseptance of pervasive serial data and a device, comprising:

A) for arbitrary serial data communication agreement provides Physical layer to connect, comprise synchronous serial data communication and asynchronous serial data communication, multiple passage can be combined into hyperchannel and connect;

B) provide the cycle to be four phase clock AK, BK, CK, DK of RXT, AK, BK, CK, DK have the time delay time difference of RXT/4 successively, RXT and serial data tranmitting data register cycle T XT approximately equal, and TXT dynamic changes, and during TXT change, RXT also must change thereupon;

C) single-ended or difference measured signal both can be the electric signal after directly receiving and processing, also can be opto-electronic conversion and the electric signal after processing, measured signal is processed into serial data signal SI and inhibit signal SD thereof, SD and SI waveform is identical but postpone about RXT/8, the effect of SD is that system is worked more reliably near most I work RXT value, can be ignored when working under larger RXT value;

D) with latch respectively by SI and SD signal 2 frequency division or 4 frequency divisions, obtain signal FI and FD of signal RI and RD of 1 or 2 corresponding SI and SD rising upset, 1 or 2 corresponding SI and SD decline upset respectively, the upset of the signal such as RI with RD, FI with FD must keep have an appointment RXT/8 the same as SI and SD to postpone, and the effect of frequency division guarantees that AK, BK, CK, DK etc. all can collect the upset each time of the signals such as RI, RD, FI, FD;

E) by SI PO shift register respectively to RI, RD, FI, the signals such as FD carry out four phase clock synchronized samplings respectively, choose the 2nd or 3 or 4 RIx of the parallel output of four phase clock sample shift register of same signal, RDx, FIx, FDx carries out time-sequencing respectively, and x is A, B, C, one of D expression corresponds respectively to AK, BK, CK, the synchronized sampling of one of DK clock, selects to stablize sampling clock, with A based on time-sequencing, B, C, D represents RI, the time-sequencing of FI signal synchronized sampling, with a, b, c, d represents RD, the time-sequencing of FD signal synchronized sampling, to RD, the synchronized sampling of FD signal be equivalent in advance the about RXT/8 time to RI, the synchronized sampling of FI signal, is namely equivalent to RI, FI signal carries out eight phase clock synchronized samplings, and the time-sequencing of eight phase clock synchronized samplings has aAbBcCdD, AbBcCdDa, bBcCdDaA, BcCdDaAb, cCdDaAbB, CdDaAbBc, dDaAbBcC, DaAbBcCd etc. eight kinds sequence, corresponding stable sampling clock is BK, CK, CK, DK, DK, AK, AK, when BK etc., SD signal is left in the basket, the time-sequencing of four phase clock synchronized samplings has ABCD, BCDA, CDAB, DABC etc. four kinds sequence, can one of the two phase clock that mediates of Stochastic choice as stablizing sampling clock, i.e. BK/CK, CK/DK, DK/AK, AK/BK etc., also can increase Time Created of shift register and retention time as alternative condition, when Time Created is more than or equal to the retention time, and corresponding selection CK respectively, DK, AK, BK, when Time Created is less than the retention time, corresponding selection BK respectively, CK, DK, AK, each RI, the upset of FI signal has a corresponding stable sampling clock,

F) obtain respectively RIx upset and FIx following closely overturn between in-phase clock count value RNx, FIx overturn and RIx following closely overturn between in-phase clock count value FNx, corresponding stable sampling clock xK is overturn respectively based on RI upset and FI, select corresponding RNx and FNx as output RNQ and FNQ respectively, RNQ and FNQ is exported according to chronological order sequence alternate, the permanent High level bit number of the serial data that RNQ correspondence receives, the lasting low level bit number of the serial data that FNQ correspondence receives.

2. the method for reseptance of asynchronous serial data and a device, comprising:

A) multiple passage can be combined into hyperchannel connection, each passage transmits data in units of transmission frame, transmission frame starts with 1 initial bits, N number of content bits of dynamically changeable is placed in the middle, 1 stops bit bringing up the rear formation, between transmission frame, insertion can be the idle bit of any amount of zero, the significant level of initial bits is different with the significant level of stopping bit, the significant level of idle bit is identical with stopping the significant level of bit, the implication of content bits is any, initial bits is interchangeable with the significant level of stopping bit and idle bit, continuous transmission can make take over party regain synchronously more than N+2 idle bit, when transmitting data continuously at set intervals, the idle bit of some is inserted between transmission frame, perform the equipment that relaying transmits, as repeater, switch etc., can by increasing or reduce the quantity of idle bit, with the frequency difference of the tranmitting data register and datum target receive clock that adapt to Data Source, the data buffer of the receiving equipment making clock frequency lower avoids overflowing,

B) provide the cycle to be four phase clock AK, BK, CK, DK of RXT, AK, BK, CK, DK have the time delay time difference of RXT/4 successively, RXT and serial data tranmitting data register cycle T XT approximately equal, and TXT dynamic changes, and during TXT change, RXT also must change thereupon;

C) single-ended or difference measured signal both can be the electric signal after directly receiving and processing, also can be opto-electronic conversion and the electric signal after processing, measured signal is processed into serial data signal SI (SIP, SIN) and inhibit signal SD (SDP, SDN) thereof, SD and SI waveform is identical but postpone about RXT/8, the effect of SD is that system is worked more reliably near most I work RXT value, can be ignored when working under larger RXT value;

D) M signal rxTask and dxTask is produced based on SI and SD signal, rxTask and dxTask respectively in the forward position of the initial bits of SI and SD signal by stopping bit significant level to be turned to initial bits significant level, rxTask and dxTask is turned to by initial bits significant level when the stopping bit of SI signal arrives simultaneously and stops bit significant level, the forward position upset of rxTask with dxTask must keep have an appointment RXT/8 the same as SI and SD to postpone, rear being in after its upset of upset palpus guarantee of rxTask and dxTask stops bit significant level until stop bit terminating and do not affect its forward position of following initial bits overturning next time,

E) respectively four phase clock synchronized samplings are carried out respectively to rxTask and dxTask signal by SI PO shift register, choose the parallel output of four phase clock sample shift register of same signal the 2nd or 3 or 4 carry out time-sequencing as rxTaskX and dxTaskX, X is A, B, C, one of D expression corresponds respectively to AK, BK, CK, the synchronized sampling of one of DK clock, selects to stablize sampling clock, with A based on time-sequencing, B, C, D represents the time-sequencing to rxTask signal synchronized sampling, with a, b, c, d represents the time-sequencing to dxTask signal synchronized sampling, to the synchronized sampling of dxTask signal be equivalent in advance the about RXT/8 time to the synchronized sampling of rxTask signal, namely be equivalent to and carry out eight phase clock synchronized samplings to rxTask signal, the time-sequencing of eight phase clock synchronized samplings has aAbBcCdD, AbBcCdDa, bBcCdDaA, BcCdDaAb, cCdDaAbB, CdDaAbBc, dDaAbBcC, DaAbBcCd etc. eight kinds sequence, corresponding stable sampling clock is BK, CK, CK, DK, DK, AK, AK, when BK etc., SD signal is left in the basket, the time-sequencing of four phase clock synchronized samplings has ABCD, BCDA, CDAB, DABC etc. four kinds sequence, can one of the two phase clock that mediates of Stochastic choice as stablizing sampling clock, i.e. BK/CK, CK/DK, DK/AK, AK/BK etc., also can increase Time Created of shift register and retention time as alternative condition, when Time Created is more than or equal to the retention time, and corresponding selection CK respectively, DK, AK, BK, when Time Created is less than the retention time, corresponding selection BK respectively, CK, DK, the forward position upset of AK, each rxTask has a corresponding stable sampling clock,

F) with N+2 bit SI PO shift register rxShiftX, four phase clock synchronized samplings are carried out respectively to SI signal, the minimum N+2 bit of the parallel output of this shift register and N+2, the upset interval, forward position of the 2nd the receive clock cycle place of parallel output of shift register of synchronized sampling rxTask be latched as rxDataX, the figure place of this shift register increases by 1 or 2 and can obtain more reliable data sampling, when the figure place of shift register increases, latch the time interval also corresponding increase of rxDataX, based on the stable sampling clock XK that rxTask forward position upset synchronized sampling time-sequencing is determined, corresponding rxDataX is selected to export as the asynchronous serial data rxData received, minimum and the highest-order bit of rxData is initial bits respectively and stops bit, data in rxData between minimum and the highest-order bit are content bits.

3. the method for the synchronous serial data communication on asynchronous serial data communication Physical layer and a device, comprising:

A) method as claimed in claim 2 and device realize the physical layer protocol receiving and send asynchronous serial data;

B) synchronous serial data of data link layer and protocol layer sends as the content bits of the asynchronous serial data of Physical layer;

C) each port is made up of one or one group of asynchronous serial data passage.

4. a multi-purpose computer central processing unit, comprising:

A) inside structure of central processing unit is any, whole new definition framework or adopt existing framework;

B) realize the reception of its unidirectional or two-way external interface as the method for claim 1 and/or 2 and/or 3 and device and send the physical layer protocol of serial data;

C) whole new definition or adopt data link layer and the layer protocols of existing external interface;

D) operational order, write data, status data, the shared port of sense data of one way ports, operational order and the write data of bidirectional port are exported by output port by input port input, status data and sense data;

E) each port is made up of one or one group of pervasive serial data channel or asynchronous serial data passage.

5. a storer for asynchronous serial data interface, comprising:

A) inside structure of the storer such as DRAM/SDRAM or SRAM or FLASH is any, whole new definition framework or adopt existing framework;

B) method as claimed in claim 2 and device realize the unidirectional or two-way reception of single port or multiport and send the physical layer protocol of asynchronous serial data;

C) whole new definition or adopt existing operational order and status information;

D) operational order, write data, status information, the shared port of sense data of one way ports, operational order and the write data of bidirectional port are exported by output port by input port input, status information and sense data;

E) each port is made up of one or one group of asynchronous serial data passage.

6. a Memory Controller for asynchronous serial data interface, comprising:

A) any with the interface architecture of the storer such as DRAM/SDRAM or SRAM or FLASH, whole new definition framework or adopt existing framework;

B) method as claimed in claim 2 and device realize the unidirectional or two-way reception of single port or multiport and send the physical layer protocol of asynchronous serial data;

C) whole new definition or adopt existing operational order and status information;

D) operational order, write data, status information, the shared port of sense data of one way ports, operational order and the write data of bidirectional port are exported by output port by input port input, status information and sense data;

E) each port is made up of one or one group of asynchronous serial data passage.

7. an interface controller for computer peripheral, comprising:

A) inside structure of the interface controller of external unit is any, whole new definition framework or adopt existing framework;

B) as the method for claim 1 and/or 2 and/or 3 and device realize device controller and computer system is unidirectional or the reception that is bi-directionally connected and the physical layer protocol sending serial data;

C) whole new definition or adopt existing data link layer and layer protocols;

D) operational order, write data, status information, the shared port of sense data of one way ports, operational order and the write data of bidirectional port are exported by output port by input port input, status information and sense data;

E) each port is made up of one or one group of pervasive serial data channel or asynchronous serial data passage.

8. a relay for data transmission, comprising:

A) any by the framework of the data transfer interface of relaying, whole new definition framework or adopt existing framework;

B) as the method for claim 1 and/or 2 and/or 3 and device realize the physical layer protocol that data transmit relaying;

C) keep by the data link layer of trunk interface and layer protocols constant;

D) data transmit relaying and are made up of one or one group of pervasive serial data channel or asynchronous serial data passage.

9. a switch for system area network, comprising:

A) inside structure of switch is any, whole new definition framework or adopt existing framework;

B) as the method for claim 1 and/or 2 and/or 3 and device realize the physical layer protocol of system domain exchange network;

C) whole new definition or adopt existing data link layer and layer protocols;

D) each port is made up of one or one group of pervasive serial data channel or asynchronous serial data passage.

10. the switch of computer network and/or a router, comprising:

A) inside structure of switch and/or router is any, whole new definition framework or adopt existing framework;

B) as the method for claim 1 and/or 2 and/or 3 and device realize the physical layer protocol of network exchange and/or route;

C) whole new definition or adopt existing data link layer and layer protocols;

D) each port is made up of one or one group of pervasive serial data channel or asynchronous serial data passage.

The switch of 11. 1 kinds of communication networks and/or router, comprising:

A) inside structure of switch and/or router is any, whole new definition framework or adopt existing framework;

B) as the method for claim 1 and/or 2 and/or 3 and device realize the physical layer protocol of network exchange and/or route;

C) whole new definition or adopt existing data link layer and layer protocols;

D) each port is made up of one or one group of pervasive serial data channel or asynchronous serial data passage.