CN105226013B - Three-dimensional interconnection device of cellular insulating medium layer and preparation method thereof - Google Patents

Abstract

The invention discloses a three-dimensional interconnection device of a porous insulating medium layer, which comprises: a chip, the chip has an annular deep hole; a conductor, the conductor penetrates through the chip through the annular deep hole; In the hole, it is arranged between the chip and the conductor, wherein the porous insulating medium layer is a mixture of a thermally decomposable first polymer material and a non-thermally decomposable second polymer material according to a preset ratio. After the molecular material is heated to decompose the first polymer material, the porous structure is formed by the second polymer material, so as to reduce the capacitance of the three-dimensional interconnection and relieve the thermal stress caused by the thermal expansion of the conductor. The three-dimensional interconnection device in the embodiment of the present invention can reduce the capacitance of the three-dimensional interconnection, better ensure the reliability of the three-dimensional interconnection, and is simple and convenient. The invention also discloses a preparation method of a three-dimensional interconnection device with a porous insulating medium layer.

Description

Three-dimensional interconnection device with porous insulating dielectric layer and its preparation method

technical field

The invention relates to the field of three-dimensional technology, in particular to a three-dimensional interconnection device of a porous insulating medium layer and a preparation method thereof.

Background technique

With the continuous reduction of the transistor feature size and the continuous increase of the VLSI chip size, the delay of the interconnect line has become the main factor affecting the delay of the circuit system. In addition, the power consumption of interconnect lines is also becoming more and more significant.

In related technologies, the above-mentioned problems are solved through three-dimensional integration technology. Three-dimensional integration refers to distributing circuit functional modules on different chips (which can be chips with different functions and different processes), forming a three-dimensional stacked structure by bonding these chips, and using The three-dimensional interconnection (Through-Silicon-Via, TSV) through the substrate realizes the electrical connection between devices at different chip layers, and jointly completes one or more functions. Three-dimensional integration can greatly reduce the global interconnect length, increase data transmission bandwidth, reduce chip area, reduce power consumption, improve integration, and realize heterogeneous chip integration.

However, in order to realize a 3D integrated circuit, it is necessary to realize the 3D interconnection through the chip, which is the core technology of 3D integration. At present, the mainstream manufacturing technology of three-dimensional interconnection is based on blind holes, that is, deep holes are etched from the front of the chip, and then an insulating dielectric layer, an adhesion layer, a diffusion barrier layer, and a copper seed layer are sequentially deposited, and then copper plating is used to fill the blind holes. The holes are used to realize the conductor copper column, and finally the three-dimensional interconnection through the chip is realized through the thinning of the back. The insulating dielectric layer material used in three-dimensional interconnection is usually silicon dioxide. Its advantages are mature manufacturing technology, stable thermodynamic performance, and sufficient research on electrical characteristics, but the dielectric constant of silicon dioxide is relatively large, resulting in three-dimensional interconnection conductor copper pillars, chip substrates, and insulating dielectric layers sandwiched between them. The capacitance of the formed three-dimensional interconnection is relatively large, which will affect the high-frequency performance of the three-dimensional interconnection and generate large power consumption in high-frequency applications. More importantly, the coefficient of thermal expansion of silicon dioxide (0.5ppm) and silicon (2.5ppm) is much smaller than that of copper (18ppm), resulting in severe deformation and stress caused by the thermal expansion of copper when the three-dimensional interconnection works, Serious reliability problems even cause the cracking of the silicon dioxide dielectric layer and the chip.

In order to solve the above problems, a polymer material with a low elastic modulus and a small dielectric constant can be used instead of silicon dioxide as the insulating dielectric layer for three-dimensional interconnection. The lower dielectric constant of the polymer material is conducive to reducing the capacitance of the three-dimensional interconnection, and its lower elastic modulus makes it easy to deform, which relieves the thermal stress imposed on the substrate by the thermal expansion of the copper pillar. However, the thermal expansion coefficient of the polymer material itself is higher (usually 50-100ppm), so that the problem of thermal stress cannot be well solved. In recent years, some studies have proposed to use air gaps as the dielectric layer of three-dimensional interconnection. The air gap has the lowest dielectric constant and the ability to allow the free expansion of copper pillars to the greatest extent. In theory, it can solve the problems of thermal expansion of copper pillars and three-dimensional interconnection capacitance, but The conductive copper pillars of the three-dimensional interconnection with air gaps can only be supported by the planar dielectric layer on the chip surface, and their ability to withstand vibration and impact is very low, which seriously affects the reliability of the three-dimensional interconnection.

Contents of the invention

The present invention aims at solving one of the technical problems in the related art mentioned above at least to a certain extent.

Therefore, an object of the present invention is to provide a three-dimensional interconnection device with a porous insulating medium layer, which can reduce the capacitance of the three-dimensional interconnection, and is simple and convenient.

Another object of the present invention is to propose a method for preparing a three-dimensional interconnection device with a porous insulating medium layer.

In order to achieve the above object, an embodiment of the present invention proposes a three-dimensional interconnection device of a porous insulating medium layer, including: a chip, the chip has a ring-shaped deep hole; a conductor, the conductor passes through the ring-shaped deep hole A hole runs through the chip; and a porous insulating medium layer, the porous insulating medium layer is arranged in the annular deep hole, and is arranged between the chip and the conductor, wherein the porous insulating medium layer The medium layer is a mixed polymer material obtained by mixing a heat-decomposable first polymer material and a non-heat-decomposable second polymer material according to a preset ratio. After heating to decompose the first polymer material, the second The porous structure generated by the polymer material can reduce the capacitance of the three-dimensional interconnection and relieve the thermal stress caused by the thermal expansion of the conductor.

According to the three-dimensional interconnection device of the porous insulating medium layer proposed by the embodiment of the present invention, by heating the mixed polymer material of the first polymer material that can be thermally decomposed and the second polymer material that cannot be thermally decomposed, the first The polymer material is decomposed, and the porous insulating medium layer is generated from the second polymer material to reduce the capacitance of the three-dimensional interconnection, and the thermal stress caused by the thermal expansion of the conductor can be relieved through the porous insulating medium layer, so as to better ensure the three-dimensional interconnection. The reliability of the connection, and the strength and reliability of the three-dimensional interconnection structure can be guaranteed through the conductor. It has a lower dielectric constant and greater deformation capacity than solid polymer materials, and is simple, convenient, and easy to implement.

In addition, the three-dimensional interconnection device of the porous insulating medium layer according to the above-mentioned embodiments of the present invention may also have the following additional technical features:

Preferably, in an embodiment of the present invention, the first polymer material may be one of polynorbornene, polycarbonate and polypropylene carbonate.

Preferably, in one embodiment of the present invention, the second polymer material may be polyimide, polymethyl methacrylate, benzocyclobutene, and poly(p-phenylene terephthalamide) kind of.

Further, in an embodiment of the present invention, the conductor may be a columnar conductor.

Further, in one embodiment of the present invention, the porous insulating medium layer is a sponge-like polymer material.

Further, in one embodiment of the present invention, the porous insulating medium layer is formed by heating the chip under vacuum conditions.

Another embodiment of the present invention proposes a method for preparing a three-dimensional interconnection device with a porous insulating dielectric layer, including the following steps: mixing a thermally decomposable first polymer material and a non-thermally decomposable second polymer material according to a preset ratio. A polymer material to form a mixed polymer material; an annular deep hole is etched on the front of the chip, and the mixed polymer material is filled in the annular deep hole, and silicon pillars surrounded by the annular deep hole are etched away to obtain A circular deep hole with a mixed polymer material as the sidewall; a diffusion barrier material and a copper seed layer are deposited on the sidewall of the mixed polymer material of the circular deep hole, and a copper filling circle is electroplated in the circular deep hole Deep holes are formed to form conductors, and planar insulating dielectric layers and planar interconnections are fabricated on the chip surface; auxiliary chips are bonded on the front of the chip by temporary bonding methods, and the chip is thinned from the back of the chip until the conductive body, manufacturing a planar insulating dielectric layer and planar interconnection on the back of the chip, and removing the auxiliary chip; and heating the chip under vacuum conditions to decompose the first polymer material in the mixed polymer material, to A porous insulating medium layer made of the second polymer material is generated to realize three-dimensional interconnection of the porous insulating medium layer.

According to the method for preparing a three-dimensional interconnection device with a porous insulating medium layer proposed in an embodiment of the present invention, by heating a mixed polymer material of a first polymer material that can be thermally decomposed and a second polymer material that cannot be thermally decomposed, The first polymer material is decomposed, and the porous insulating medium layer is generated from the second polymer material to reduce the capacitance of the three-dimensional interconnection, and the thermal stress caused by the thermal expansion of the conductor can be relieved through the porous insulating medium layer, which is better The reliability of the three-dimensional interconnection is guaranteed, and the strength and reliability of the three-dimensional interconnection structure can be guaranteed through the conductor. It has a lower dielectric constant and greater deformation capacity than solid polymer materials, and is simple, convenient, and easy to implement.

In addition, the method for preparing a three-dimensional interconnection device with a porous insulating dielectric layer according to the above-mentioned embodiments of the present invention may also have the following additional technical features:

Preferably, in an embodiment of the present invention, the first polymer material may be one of polynorbornene, polycarbonate and polypropylene carbonate.

Preferably, in one embodiment of the present invention, the second polymer material may be polyimide, polymethyl methacrylate, benzocyclobutene, and poly(p-phenylene terephthalamide) kind of.

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and comprehensible from the description of the embodiments in conjunction with the following drawings, wherein:

1 is a schematic structural diagram of a three-dimensional interconnection device with a porous insulating dielectric layer according to an embodiment of the present invention;

2 is a flowchart of a method for preparing a three-dimensional interconnection device with a porous insulating dielectric layer according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a three-dimensional interconnection device with a porous insulating dielectric layer according to an embodiment of the present invention.

Fig. 4 is a schematic structural view of a chip manufactured with an annular deep hole according to an embodiment of the present invention;

5 is a schematic diagram of the chip structure after the polymer mixture is filled in the annular deep hole and the redundancy of the surface polymer mixture is removed according to an embodiment of the present invention;

6 is a schematic diagram of a chip structure after etching and removing silicon pillars surrounded by annular deep holes according to an embodiment of the present invention;

7 is a schematic diagram of the chip structure after electroplating copper in the circular deep hole to fill the circular deep hole to form a conductor copper column according to an embodiment of the present invention;

8 is a schematic diagram of the chip structure after manufacturing an insulating dielectric layer and planar interconnection on the chip surface according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of the chip structure after the auxiliary chip is bonded on the front side of the chip using temporary bonding technology according to an embodiment of the present invention;

10 is a schematic diagram of the chip structure after thinning the chip from the back of the chip and exposing the conductor copper column according to an embodiment of the present invention;

11 is a schematic diagram of the chip structure after manufacturing an insulating dielectric layer and planar interconnection on the back of the chip according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of the chip structure after removing the auxiliary chip according to an embodiment of the present invention;

Fig. 13 is a schematic diagram of a three-dimensional interconnection structure in which a spongy porous insulating medium layer is formed by heating a chip under vacuum conditions according to an embodiment of the present invention;

Fig. 14 is a schematic structural view of a chip manufactured with a circular deep hole according to an embodiment of the present invention;

Fig. 15 is a schematic diagram of the chip structure after the polymer mixture film is coated on the inner wall of the circular deep hole according to one embodiment of the present invention;

16 is a schematic diagram of the chip structure after electroplating copper in the circular deep hole to fill the circular deep hole to form a conductor copper column according to an embodiment of the present invention;

17 is a schematic diagram of the chip structure after manufacturing an insulating dielectric layer and planar interconnection on the chip surface according to an embodiment of the present invention; and

FIG. 18 is a schematic diagram of the chip structure after the auxiliary chip is bonded on the front side of the chip by using the temporary bonding technique according to an embodiment of the present invention.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

In the present invention, unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection" and "fixation" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection , or integrally connected; it may be mechanically connected or electrically connected; it may be directly connected or indirectly connected through an intermediary, and it may be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

In the present invention, unless otherwise clearly specified and limited, a first feature being "on" or "under" a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them. Moreover, "above", "above" and "above" the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature. "Below", "beneath" and "under" the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.

The following describes the three-dimensional interconnection device of the porous insulating medium layer according to the embodiment of the present invention and its preparation method with reference to the accompanying drawings. First, the three-dimensional interconnection device of the porous insulating medium layer according to the embodiment of the present invention will be described with reference to the accompanying drawings . Referring to FIG. 1 , the three-dimensional interconnection device 10 includes: a chip 20 , a conductor 30 and a porous insulating medium layer 40 .

Wherein, the chip 20 has an annular deep hole. The conductor 30 penetrates the chip 20 through the annular deep hole. The porous insulating medium layer 40 is arranged in the annular deep hole, and is arranged between the chip 20 and the conductor 30, wherein the porous insulating medium layer 40 is composed of a thermally decomposable first polymer material and a non-thermally decomposable first polymer material. The mixed polymer material obtained by mixing the two polymer materials according to the preset ratio is heated to decompose the first polymer material to form a porous structure formed by the second polymer material, so as to reduce the capacitance of the three-dimensional interconnection and relieve the electric current generated by the conductor. 30 Thermal stress due to thermal expansion. The embodiment of the present invention can reduce the capacitance of the three-dimensional interconnection, has a lower dielectric constant and greater deformation ability than solid polymer materials, and better ensures the reliability of the three-dimensional interconnection.

It should be understood that the preset ratio can be set by the designer according to the actual situation.

Preferably, in one embodiment of the present invention, the first polymer material may be one of polynorbornene, polycarbonate and polypropylenecarbonate, and the second high Molecular materials can be polyimide, polymethylmethacrylate, benzocyclobutene and poly p-phenylene terephthalamide kind of.

Further, in an embodiment of the present invention, the conductor 30 may be a columnar conductor, and the porous insulating medium layer 40 may be a sponge-like polymer material.

In addition, in one embodiment of the present invention, the chip 20 is heated under vacuum conditions to generate the porous insulating medium layer 40, that is, the porous insulating medium layer 40 is generated by heating the chip 20 under vacuum conditions. After heating, the second The first polymer material is decomposed, and the porous insulating medium layer 40 is generated from the second polymer material.

Specifically, the three-dimensional interconnection device 10 of the embodiment of the present invention may be composed of a columnar conductor that runs through the entire thickness of the chip and an annular sponge-shaped polymer porous insulating medium layer between the chip and the columnar conductor. The sponge-like polymer porous insulating medium layer uses a mixture of thermally decomposable polymer materials and non-decomposable polymer materials to manufacture an annular dielectric layer around the columnar conductor, and then heats the dielectric layer to make the thermally decomposable polymer material Decompose to form a sponge-like polymer porous insulating medium layer composed of non-heatable polymer materials. The porous insulating medium layer of the embodiment of the present invention can reduce the capacitance of the three-dimensional interconnection, and alleviate the impact of the thermal expansion stress of the columnar conductor on the reliability of the three-dimensional interconnection through the porous medium layer, and at the same time fix and support the columnar conductor to ensure the three-dimensional interconnection structure strength and reliability.

Among them, in order to realize that the insulating medium layer between the chip and the columnar conductor is in the shape of an annular sponge, the polymer mixture filled in the annular deep hole or coated in the circular deep hole contains a thermally decomposable polymer material and Heating non-decomposable polymer materials. The thermally decomposable polymer material can be one of polynorbornene, polycarbonate, and polypropylene carbonate, and the thermally non-decomposable polymer material can be polyimide, polymethyl methacrylate, benzocyclo One of butene and poly-p-phenylene terephthalamide. In the embodiment of the present invention, the thermally decomposable polymer material is preferably polypropylene carbonate, and the thermally non-decomposable polymer material is preferably polyimide.

According to the three-dimensional interconnection device of the porous insulating medium layer proposed by the embodiment of the present invention, the mixed polymer material of the first polymer material that can be thermally decomposed and the second polymer material that cannot be thermally decomposed is heated, so that the first A polymer material is decomposed, and a porous insulating medium layer is formed from the second polymer material to reduce the capacitance of the three-dimensional interconnection, and the thermal stress caused by the thermal expansion of the conductor can be relieved through the porous insulating medium layer, so as to better ensure the three-dimensional interconnection. The reliability of the interconnection, and the strength and reliability of the three-dimensional interconnection structure can be guaranteed through the conductor, which has a lower dielectric constant and greater deformation capacity than the solid polymer material, which is simple, convenient, and easy to implement.

Next, a method for preparing a three-dimensional interconnection device with a porous insulating dielectric layer according to an embodiment of the present invention will be described with reference to the accompanying drawings. Referring to Figure 2, the preparation method of the embodiment of the present invention includes the following steps:

S201. Mixing a thermally decomposable first polymer material and a non-thermally decomposable second polymer material according to a preset ratio to form a mixed polymer material.

In short, the thermally decomposable polymer material and the thermally non-decomposable polymer material are mixed in a certain proportion to form a polymer mixture composed of two components.

Preferably, in one embodiment of the present invention, the first polymer material can be one of polynorbornene, polycarbonate and polypropylene carbonate, and the second polymer material can be polyimide, poly One of methyl methacrylate, benzocyclobutene and poly-p-phenylene terephthalamide.

S202, etching an annular deep hole on the front of the chip, filling the annular deep hole with a mixed sponge-like polymer material, and etching and removing the silicon pillars surrounded by the annular deep hole to obtain a circular deep hole with a mixed polymer material as a side wall .

That is to say, etch the annular deep hole on the front of the chip, fill the annular deep hole with a polymer mixture composed of a polymer material that can be decomposed by heating and a polymer material that cannot be decomposed by heating, and etch to remove the surrounding area of the deep annular hole. The silicon pillars form a circular deep hole with a polymer film as the side wall.

S203, depositing a diffusion barrier material and a copper seed layer on the sidewall of the mixed polymer material of the circular deep hole, and electroplating copper in the circular deep hole to fill the circular deep hole to form a conductor, and manufacturing a plane on the chip surface Insulating dielectric layers and planar interconnects.

S204, bonding the auxiliary chip on the front of the chip by a temporary bonding method, thinning the chip from the back of the chip until the conductor is exposed, manufacturing a planar insulating dielectric layer and planar interconnection on the back of the chip, and removing the auxiliary chip.

S205, heating the chip under vacuum conditions to decompose the first polymer material in the mixed polymer material to generate a porous insulating medium layer composed of the second polymer material, so as to realize three-dimensional interconnection of the porous insulating medium layer.

Specifically, the chip is heated under vacuum conditions to decompose the polymer material that can be decomposed by heating, and the remaining polymer material that cannot be decomposed by heating forms a sponge-like porous insulating medium layer, forming a three-dimensional interconnection of the sponge-like porous insulating medium layer .

In addition, in another embodiment of the present invention, the preparation method of the embodiment of the present invention can also etch circular deep holes on the surface of the chip. That is to say, the inner diameter of the etched annular deep hole can be 0, that is, the circular deep hole is etched on the chip surface, and the inner wall of the circular deep hole is coated with a thermally decomposable polymer material and a thermally non-decomposable high polymer material. The polymer mixture thin film formed by mixing molecular materials is similar to the principle of the above-mentioned preparation method, and will not be described in detail here in order to reduce redundancy.

In an embodiment of the present invention, by using a spongy polymer material as a three-dimensional interconnection insulating medium layer, the porous property makes the dielectric constant of the polymer material lower than that of the solid polymer material, which can reduce the capacitance of the three-dimensional interconnection; in addition , the porous structure makes the polymer dielectric layer easier to deform, providing a more free deformation space for the thermal expansion of the copper pillars, so as to reduce the stress caused by the thermal expansion of the copper pillars on the chip; at the same time, the insulating dielectric layer fixes the copper pillars in the deep hole of the chip On the sidewall, the mechanical strength and reliability of the three-dimensional interconnection structure are greatly improved.

In order to enable those skilled in the art to better understand the present invention, the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings.

Example 1:

As shown in FIG. 3 , a schematic diagram of a three-dimensional interconnection structure provided by an example of the present invention. Including chip 200, porous side wall insulating medium layer 201, columnar conductor 202, integrated circuit transistor 203, metal interconnection 204, passivation layer 205, upper surface interconnection line 101, surface insulating medium layer 100 , an insulating dielectric layer 300 on the back of the chip, and an interconnection line 301 on the back of the chip.

As shown in FIG. 4 , photolithography is performed using a mask plate on the front of the chip 200 to define a three-dimensional interconnection structure of the annular insulating dielectric layer pattern, and the passivation layer 205 is etched by reactive ion etching (RIE, Reactive Ion Etching), Then, deep reactive ion etching (DIRE, Deep Reactive Ion Etch) technology is used to etch the ring-shaped deep hole 207 with a depth of 30-100 μm in the region corresponding to the ring-shaped dielectric layer.

As shown in FIG. 5, the mixture of thermally decomposable polymer material and thermally non-decomposable polymer material is filled in the annular deep hole 207, and chemical-mechanical polishing (Chemical-Mechanical Polishing, CMP) is used to remove the polymer material. The surface is redundant, forming a polymer medium layer 206 .

As shown in FIG. 6 , DRIE is used to etch the silicon pillar surrounded by the polymer annular dielectric layer 206 to form a circular deep hole 208 with the polymer dielectric layer 206 as the sidewall, and the etching depth is the same as that of the annular deep hole, namely 30～100μm.

As shown in FIG. 7 , TiW and copper are sequentially sputtered on the sidewall of the deep hole 208 as a metal adhesion/diffusion barrier layer and a copper seed layer. Copper electroplating technology is used to fill the deep hole with electroplating copper in the deep hole to form the conductor copper column 202 . Then, chemical mechanical polishing is used to remove redundant copper plating on the surface.

As shown in FIG. 8, a silicon dioxide dielectric layer 100 is deposited on the front surface of the chip 200, and then a contact hole in contact with the surface of the three-dimensional interconnection is defined by mask plate lithography, and the silicon dioxide is etched by RIE to form a contact hole of a copper column. Then metal sputtering, photolithography and RIE etching are used to manufacture the aluminum planar interconnection 101 on the surface of the chip 200 .

As shown in FIG. 9 , the temporary bonding glue 400 is spin-coated on the front of the chip by using the temporary bonding technology, and the auxiliary chip 500 is temporarily bonded by a bonding machine.

As shown in FIG. 10 , grinding and CMP techniques are used to thin the wafer from the back of the chip, and the thickness of the wafer is reduced to 30-100 μm, so that the conductive copper pillars 202 are exposed from the back of the chip.

As shown in FIG. 11 , a silicon dioxide dielectric layer 300 is deposited on the back of the chip, and then photolithography and RIE etching are used to manufacture contact holes for three-dimensional interconnection, exposing the surface of the conductor copper pillar. Then sputtering, photolithography and RIE etching the metal aluminum to form the planar interconnection 301 on the back side.

As shown in FIG. 12 , the temporarily bonded companion chip 500 is removed.

As shown in Figure 13, the chip is placed in a vacuum chamber and heated, so that polyimide is cured while polypropylene carbonate is thermally decomposed. The pyrolysis product of polypropylene carbonate diffuses out of the dielectric layer through the silicon dioxide dielectric layer on the upper and lower surfaces of the chip, forming a polyimide dielectric layer 201 with a porous structure.

Example 2:

As shown in FIG. 14 , photolithography is carried out using a mask plate on the front of the chip 200 to define a circular three-dimensional interconnection structure pattern of a three-dimensional interconnection structure, and the passivation layer is etched by reactive ion etching (RIE, Reactive Ion Etching) 205 , and then using Deep Reactive Ion Etch (DIRE, Deep Reactive Ion Etch) technology to etch an annular deep hole 209 with a depth of 30-100 μm in the region corresponding to the circular dielectric layer.

As shown in Figure 15, the mixture of thermally decomposable polymer material and thermally non-decomposable polymer material is filled in the annular deep hole 209, and chemical-mechanical polishing (Chemical-Mechanical Polishing, CMP) is used to remove the The surface is redundant, forming a polymer medium layer 210 .

As shown in FIG. 16 , TiW and copper are sequentially sputtered on the sidewall of the deep hole 209 as a metal adhesion/diffusion barrier layer and a copper seed layer. Copper electroplating technology is used to fill the deep hole with electroplating copper in the deep hole to form the conductor copper column 202 . Then, chemical mechanical polishing is used to remove redundant copper plating on the surface.

As shown in FIG. 17, a silicon dioxide dielectric layer 100 is deposited on the front surface of the chip 200, and then a contact hole in contact with the three-dimensional interconnection surface is defined by mask plate lithography, and a contact hole of a copper column is formed by etching silicon dioxide by RIE. Then use metal sputtering, photolithography and RIE etching to manufacture the aluminum planar interconnection 101 on the surface of the chip 200

As shown in FIG. 18 , the temporary bonding glue 400 is spin-coated on the front of the chip by using the temporary bonding technology, and the auxiliary chip 500 is temporarily bonded by a bonding machine.

As shown in FIGS. 10 to 13 , the remaining steps adopt the same process as that in Embodiment 1 to complete the process in FIGS. 10 to 13 .

So far, through Embodiment 1 and Embodiment 2, the three-dimensional interconnection device of the porous insulating medium layer according to the embodiment of the present invention is respectively realized.

According to the method for preparing a three-dimensional interconnection device with a porous insulating medium layer proposed in an embodiment of the present invention, by heating a mixed polymer material of a first polymer material that can be thermally decomposed and a second polymer material that cannot be thermally decomposed, The first polymer material is decomposed, and the porous insulating medium layer is formed from the second polymer material to reduce the capacitance of the three-dimensional interconnection, and the thermal stress generated by the thermal expansion of the conductor can be relieved through the porous insulating medium layer, preferably The reliability of the three-dimensional interconnection can be ensured, and the strength and reliability of the three-dimensional interconnection structure can be guaranteed through the conductor. It has a lower dielectric constant and greater deformation capacity than solid polymer materials, and is simple, convenient, and easy to implement.

Any process or method descriptions in flowcharts or otherwise described herein may be understood to represent modules, segments or portions of code comprising one or more executable instructions for implementing specific logical functions or steps of the process , and the scope of preferred embodiments of the invention includes alternative implementations in which functions may be performed out of the order shown or discussed, including substantially concurrently or in reverse order depending on the functions involved, which shall It is understood by those skilled in the art to which the embodiments of the present invention pertain.

The logic and/or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium, For use with instruction execution systems, devices, or devices (such as computer-based systems, systems including processors, or other systems that can fetch instructions from instruction execution systems, devices, or devices and execute instructions), or in conjunction with these instruction execution systems, devices or equipment for use. For the purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate or transmit a program for use in or in conjunction with an instruction execution system, device or device. More specific examples (non-exhaustive list) of computer-readable media include the following: electrical connection with one or more wires (electronic device), portable computer disk case (magnetic device), random access memory (RAM), Read Only Memory (ROM), Erasable and Editable Read Only Memory (EPROM or Flash Memory), Fiber Optic Devices, and Portable Compact Disc Read Only Memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program can be printed, since the program can be read, for example, by optically scanning the paper or other medium, followed by editing, interpretation or other suitable processing if necessary. The program is processed electronically and stored in computer memory.

It should be understood that various parts of the present invention can be realized by hardware, software, firmware or their combination. In the embodiments described above, various steps or methods may be implemented by software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or combination of the following techniques known in the art: Discrete logic circuits, ASICs with suitable combinational logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

Those of ordinary skill in the art can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. During execution, one or a combination of the steps of the method embodiments is included.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing module, each unit may exist separately physically, or two or more units may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. If the integrated modules are realized in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, and the like.

In the description of this specification, descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be construed as limitations to the present invention. Variations, modifications, substitutions, and modifications to the above-described embodiments are possible within the scope of the present invention.

Claims (8)

1. A three-dimensional interconnection device of a porous insulating dielectric layer, characterized in that it comprises: a chip having an annular deep hole; an electrical conductor penetrating the chip through the annular deep hole; and A porous insulating medium layer, the porous insulating medium layer is arranged in the annular deep hole and between the chip and the conductor, wherein the porous insulating medium layer can be decomposed by heating The mixed polymer material obtained by mixing the first polymer material and the second polymer material that cannot be thermally decomposed according to a preset ratio is generated from the second polymer material after being heated to decompose the first polymer material The porous structure is used to reduce the capacitance of the three-dimensional interconnection and relieve the thermal stress caused by the thermal expansion of the conductor, and the porous insulating medium layer is a sponge-like polymer material. 2 . The three-dimensional interconnection device of porous insulating dielectric layer according to claim 1 , wherein the first polymer material is one of polynorbornene, polycarbonate and polypropylene carbonate. 3. The three-dimensional interconnection device of the porous insulating medium layer according to claim 1, wherein the second polymer material is polyimide, polymethyl methacrylate, benzocyclobutene and One of poly(p-phenylene terephthalamide). 4 . The three-dimensional interconnection device of porous insulating medium layer according to claim 1 , wherein the conductor is a columnar conductor. 5. The three-dimensional interconnection device with a porous insulating medium layer according to claim 1, wherein the porous insulating medium layer is formed by heating the chip under vacuum conditions. 6. A method for preparing a three-dimensional interconnection device of a porous insulating dielectric layer, comprising the following steps: mixing the thermally decomposable first polymer material and the non-thermally decomposable second polymer material according to a preset ratio to form a mixed polymer material; An annular deep hole is etched on the front of the chip, and the mixed polymer material is filled in the annular deep hole, and the silicon pillar surrounded by the annular deep hole is etched away to obtain a circular shape with the mixed polymer material as the side wall deep hole; Deposit a diffusion barrier material and a copper seed layer on the mixed polymer material sidewall of the circular deep hole, and electroplate copper in the circular deep hole to fill the circular deep hole to form a conductor, and make a plane on the chip surface Insulating dielectric layer and planar interconnection; Auxiliary chips are bonded on the front of the chip by a temporary bonding method, the chip is thinned from the back of the chip until the conductors are exposed, a planar insulating dielectric layer and planar interconnection are made on the back of the chip, and the auxiliary chips; and Heating the chip under vacuum conditions to decompose the first polymer material in the mixed polymer material to generate a porous insulating medium layer composed of the second polymer material, so as to realize the three-dimensional interconnection of the porous insulating medium layer . 7. The method for preparing a three-dimensional interconnection device of a porous insulating medium layer according to claim 6, wherein the first polymer material is polynorbornene, polycarbonate and polypropylene carbonate. A sort of. 8. The preparation method of the three-dimensional interconnection device of the porous insulating medium layer according to claim 7, characterized in that, the second polymer material is polyimide, polymethyl methacrylate, benzocyclo One of butene and poly-p-phenylene terephthalamide.