CN105244321B - A kind of semiconductor devices and its manufacturing method and electronic device - Google Patents
A kind of semiconductor devices and its manufacturing method and electronic device Download PDFInfo
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- CN105244321B CN105244321B CN201410269703.4A CN201410269703A CN105244321B CN 105244321 B CN105244321 B CN 105244321B CN 201410269703 A CN201410269703 A CN 201410269703A CN 105244321 B CN105244321 B CN 105244321B
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- grid line
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- area
- semiconductor substrate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000005520 cutting process Methods 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 36
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacturing method and electronic device, which comprises provides semiconductor substrate；The multiple active areas extended in a first direction are formed in the semiconductor substrate；The control grid line extended in a second direction across multiple active areas is formed on the active area, wherein the second direction and the first direction are vertical；The cutting exposure mask that definition has cutting area pattern is formed, the control grid line in the cutting area is etched, the control grid line of active region is at least completely removed.Manufacturing method according to the invention, by changing the layout direction of control grid line and cutting the layout of exposure mask, it more easily realizes to the control of residual polycrystalline silicon after control grid line cutting, avoids the appearance of word line bridging problem, and then improve the performance and yield of device.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor devices and its manufacturing method and electronics
Device.
Background technique
Semiconductor memory system is more and more commonly used in various electronic devices.For example, non-volatile partly to lead
Body memory can be used in cellular phone, digital camera, personal digital assistant, mobile computing device, non-moving computing device and
In other devices.With the fast development of electronic industry especially consumer electronics, the development of semiconductor storage increasingly at
For one of the mark post of electronics technology development.It dominates from initial accounted for DRAM (i.e. dynamic RAM) till now with Flash
Memory (i.e. nonvolatile flash memory memory body) is maximum camp；The development speed of semiconductor memory is constantly challenged mole fixed
Rule, in the twinkling of an eye NAND Flash has come 3X nanometer era, has more even striden into 2X nanometer era.
However in the manufacturing process of 3xnm nand memory, a kind of special failure mode --- word is often generated
Line bridge (Word Line Bridge), cause one of word line bridging the reason is that, using double-pattern technology, to storage array
In P2 cutting region in after the polysilicon control grid polar curve parallel with active area cut, a large amount of residual polycrystalline silicons are being isolated
Superstructure leads to the dangerous of the appearance of word line bridging problem.
It is, therefore, desirable to provide a kind of new production method, to solve the above problems.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, comprising:
Semiconductor substrate is provided；
The multiple active areas extended in a first direction are formed in the semiconductor substrate；
The control grid line extended in a second direction across multiple active areas is formed on the active area, wherein institute
It states second direction and the first direction is vertical；
The cutting exposure mask that definition has cutting area pattern is formed, the control grid line in the cutting area is lost
It carves, at least completely removes the control grid line of active region.
Optionally, the isolation structure in the semiconductor substrate is also formed between the adjacent active area.
Optionally, the material of the control grid line is polysilicon.
Optionally, the etch process has polysilicon to the high etching selectivity of oxide.
Optionally, the active area has been respectively formed on floating grid.
Optionally, ONO dielectric layer is formed between the floating grid and the control grid line.
Optionally, the etching further includes the cutting etching to the control grid line a plurality of in the cutting area.
The present invention also provides a kind of semiconductor devices manufactured using the above method.
In addition the present invention also provides a kind of electronic device, including above-mentioned semiconductor devices.
In conclusion manufacturing method according to the invention, by the layout direction and the cutting exposure mask that change control grid line
Layout, it is easier to realize to control grid line cutting after residual polycrystalline silicon control, avoid the appearance of word line bridging problem,
And then improve the performance and yield of device.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A to Fig. 1 D shows the system for indicating implementation method integated semiconductor memory arrangement according to prior art
Make the schematic layout figure of method, wherein Figure 1A is top view, and Figure 1B is the sectional view of the line A-A along Figure 1A, and Fig. 1 C is to overlook
Figure, Fig. 1 D are the sectional view of the line A-A along Fig. 1 C；
Fig. 2A to Fig. 2 D shows the implementation method for indicating according to embodiments of the present invention one and integrates semiconductor storage dress
The schematic layout figure for the manufacturing method set, wherein Fig. 2A is top view, and Fig. 2 B is the sectional view of the line A-A along Fig. 2A, Fig. 2 C
For top view, Fig. 2 D is the sectional view of the line A-A along Fig. 2 C；
Fig. 3 is the flow chart according to the step of method is successively implemented in the embodiment of the present invention one.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with
With other embodiments.
1A-1D describes wordline circle of a kind of existing implementation method pair and nand-type flash memory devices with reference to the accompanying drawing
The step of wordline in face region is cut.
As shown in Figure 1A, semiconductor substrate 100 is provided, is formed to have along first direction in the semiconductor substrate 100 and be prolonged
Multiple active areas 101 stretched, and neutralize the isolation structure 102 between the active area positioned at semiconductor substrate, and with have
The control grid line 103 that source region extends in a first direction in parallel.The material of the control grid line is polysilicon.The control gate
Polar curve a part is located at active region, and a part is located above trench isolations.Rectangular area 104 is P2 cutting area in figure.Such as
Shown in Figure 1B, described 103 a part of control grid line is located at 106 top of floating grid 105 and ONO dielectric layer, and a part is located at
102 top of isolation structure in semiconductor substrate 100.
As shown in Fig. 1 C-1D, using dual patterning technique, after formation definition has the exposure mask of P2 cutting area pattern, P2 is cut
The control grid line cut in area is etched, and the thick polysilicon of comparison is remained above channel separating zone 102, causes control gate
Polar curve 103 bridges problem, and then affects the reliability and yield of memory.
In consideration of it, the invention proposes a kind of new manufacturing method, to solve the above problem occurred.
Embodiment one
In the following, describing the wordline to the wordline interface zone with nand-type flash memory devices referring to Fig. 2A-Fig. 2 D and Fig. 3
The detailed step cut.
As seen in figs. 2a-2b, semiconductor substrate 200 is provided, the semiconductor substrate 200 can be silicon, silicon-on-insulator
(SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
(SiGeOI) and at least one of germanium on insulator (GeOI).
The multiple active areas 201 extended in a first direction are formed in the semiconductor substrate 200；Each active area
It include multiple charge storage cells, such as floating grid 205 on 201.Illustratively, it is formed on each active area multiple
The floating grid extended in a first direction.
The material of the floating grid 205 is including but not limited to certain metals, metal alloy, metal nitride and metal
Silicide and its laminate and its compound.The material of floating grid also may include the polysilicon and polycrystalline silicon-germanium of doping
Alloy material and polycide material (polysilicon of doping/metal silicide laminated material).In the present embodiment
The material of middle floating grid is polysilicon layer.Any existing technology can be used and form the floating grid, therefore not to repeat here.
The step of forming floating grid for a person skilled in the art is that well known technological means is not just described in detail herein, can
To form floating grid using any suitable method.
The top of floating grid 205 is formed with ONO dielectric layer 206.The ONO dielectric layer 206 is usually silica-nitridation
Thermal oxide or chemical vapor deposition can be used in silicon-silica three-decker, illustratively, lower layer's silica of the three-decker
Long-pending method is formed, and silicon nitride is frequently with such as low-pressure chemical vapor deposition or plasma reinforced chemical vapour deposition method shape
At.Upper layer silica is formed using such as chemical vapor deposition method.
The isolation structure 202 being also formed between adjacent active regions 201 in the semiconductor substrate 200.It is optional
Ground, the isolation structure are shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure.In an example
In, when isolation structure is fleet plough groove isolation structure, the material of the fleet plough groove isolation structure can be silica, silicon oxynitride
And/or other existing advanced low-k materials.
The control grid line 203 extended in a second direction across multiple active areas is formed on the active area 201, wherein
The second direction and the first direction are vertical；In one example, the material of the control grid line is polysilicon.
In one example, the method for the control grid line that manufacture extends in a second direction includes: in ONO dielectric layer 206
Upper formation control gate layer, the control gate layer are polysilicon layer, then form pattern, which includes in a second direction
Extend and in a first direction apart from one another by strip part.Control gate layer is etched using the pattern, is formed in
Multiple control grid lines that two sides upwardly extend.
Due to controlling the layout change of grid line, accordingly when carrying out subsequent P2 cutting using double-pattern technology,
It then needs the cutting mask plate used needed for cutting to P2 to be laid out again, using the cutting mask plate after new layout, forms figure
The cutting exposure mask of case, definition has the pattern of P2 cutting area 204 on the cutting exposure mask, in Fig. 2A in P2 cutting region 204
Control grid line 203 is etched, so that floating grid and isolation structure are exposed, the etch process can use wet process
Etching or dry etching, etch process have polysilicon to the high etching selectivity of oxide.
Optionally, technique is etched using dry etching, dry method etch technology includes but is not limited to: reactive ion etching
(RIE), ion beam milling, plasma etching or laser cutting.
In a specific embodiment of the invention, using the photoresist layer being patterned as exposure mask, using dry etching
Technique performs etching control grid line in the case where being passed through the etching condition of hydrogen bromide and chlorine, reaction room pressure can for 5~
20 millitorrs (mTorr)；Power: 300-800W；Time: 5-15s；The range of flow of the hydrogen bromide and chlorine can be vertical for 0~150
Square cm per minute (sccm) and 50~200 cc/mins (sccm).It should be noted that above-mentioned engraving method is only
Illustratively, it is not limited to which this method, those skilled in the art can also select other common methods.
It is noted that merely illustrate the cutting that grid line is controlled one for simplicity, in figure, and P2 cutting may be used also
Cutting etching is carried out to a plurality of control grid line simultaneously.
As shown in figures 2 c-2d, the control grid line quilt after P2 cutting etching, on active area in cutting area 204
It completely removes, and is also possible to remain on isolation structure 202 on a small quantity than relatively thin polysilicon.To control grid line etching
In the process, as long as guaranteeing that the control grid line on active area 201 is completely removed, i.e. 205 top of floating grid is residual without polysilicon
It stays, then the cutting for controlling grid line just successfully completes, and will not generate the risk of word line bridging.
Referring to Fig. 3, the flow chart proposed by the present invention cut to control grid line is shown, it is whole for schematically illustrating
The process of a manufacturing process.
In step 301, semiconductor substrate is provided；Be formed in the semiconductor substrate extend in a first direction it is multiple
Active area；
In step 302, the control extended in a second direction across multiple active areas is formed on the active area
Grid line, wherein the second direction and the first direction are vertical；
In step 303, the cutting exposure mask that definition has cutting area pattern is formed, to the control gate in the cutting area
Polar curve is etched, and at least completely removes the control grid line of active region.
In conclusion manufacturing method according to the invention, by the layout direction and the cutting exposure mask that change control grid line
Layout, it is easier to realize to control grid line cutting after residual polycrystalline silicon control, avoid the appearance of word line bridging problem,
And then improve the performance and yield of device.
Embodiment two
The present invention also provides a kind of semiconductor devices, the semiconductor devices selects method system described in embodiment one
It is standby.Grid line is controlled in the semiconductor devices that the method is prepared through the invention, word line bridging problem is not present, have
Excellent performance and yield.
Embodiment three
The present invention also provides a kind of electronic devices, including semiconductor devices described in embodiment two.Wherein, semiconductor device
Part is semiconductor devices described in embodiment two, or the semiconductor devices that the manufacturing method according to embodiment one obtains.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.The electronic device of the embodiment of the present invention above-mentioned is partly led due to having used
Body device, thus there is better performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (9)
1. a kind of manufacturing method of semiconductor devices, comprising:
Semiconductor substrate is provided；
The multiple active areas extended in a first direction are formed in the semiconductor substrate；
The control grid line extended in a second direction across multiple active areas is formed on the active area, wherein described the
Two directions and the first direction are vertical；
The cutting exposure mask that definition has cutting area pattern is formed, the control grid line in the cutting area is etched, until
The control grid line of active region is completely removed, less to avoid word line bridging problem.
2. the method according to claim 1, wherein being also formed between the adjacent active area positioned at described
Isolation structure in semiconductor substrate.
3. the method according to claim 1, wherein the material of the control grid line is polysilicon.
4. according to the method described in claim 3, it is characterized in that, there is the etch process polysilicon to lose to the height of oxide
Carve selection ratio.
5. the method according to claim 1, wherein the active area has been respectively formed on floating grid.
6. according to the method described in claim 5, it is characterized in that, between the floating grid and the control grid line shape
At there is ONO dielectric layer.
7. the method according to claim 1, wherein the etching further includes to a plurality of described in the cutting area
Control the cutting etching of grid line.
8. a kind of semiconductor devices manufactured using method described in one of claim 1-7.
9. a kind of electronic device, including semiconductor devices according to any one of claims 8.
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| CN201410269703.4A CN105244321B (en) | 2014-06-17 | 2014-06-17 | A kind of semiconductor devices and its manufacturing method and electronic device |
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| CN201410269703.4A CN105244321B (en) | 2014-06-17 | 2014-06-17 | A kind of semiconductor devices and its manufacturing method and electronic device |
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| CN105244321B true CN105244321B (en) | 2018-12-21 |
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| CN112864152B (en) | 2019-11-26 | 2022-06-24 | 长鑫存储技术有限公司 | Memory, memory substrate structure and preparation method thereof |
| CN119447111B (en) * | 2024-11-07 | 2025-09-30 | 上海积塔半导体有限公司 | Semiconductor test structure and test method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070026613A1 (en) * | 2004-05-06 | 2007-02-01 | Samsung Electronics Co., Ltd. | Flash memory device having a split gate |
| US20070190719A1 (en) * | 2004-11-24 | 2007-08-16 | Macronix International Co., Ltd. | Method of forming a contact on a semiconductor device |
| CN101140937A (en) * | 2006-09-08 | 2008-03-12 | 三星电子株式会社 | Non-volatile memory structure and method of forming same |
| CN101197263A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of high voltage transistor and memory device |
| CN103855166A (en) * | 2012-12-04 | 2014-06-11 | 三星电子株式会社 | Semiconductor memory devices and methods of fabricating the same |
-
2014
- 2014-06-17 CN CN201410269703.4A patent/CN105244321B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070026613A1 (en) * | 2004-05-06 | 2007-02-01 | Samsung Electronics Co., Ltd. | Flash memory device having a split gate |
| US20070190719A1 (en) * | 2004-11-24 | 2007-08-16 | Macronix International Co., Ltd. | Method of forming a contact on a semiconductor device |
| CN101140937A (en) * | 2006-09-08 | 2008-03-12 | 三星电子株式会社 | Non-volatile memory structure and method of forming same |
| CN101197263A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of high voltage transistor and memory device |
| CN103855166A (en) * | 2012-12-04 | 2014-06-11 | 三星电子株式会社 | Semiconductor memory devices and methods of fabricating the same |
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