CN105262467A - Circuit and method for body biasing - Google Patents
Circuit and method for body biasing Download PDFInfo
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Abstract
Various example embodiments are directed to methods and circuits for mitigation of on-resistance variation and signal attenuation in transistors due to body effects. In some embodiments, an apparatus includes a transistor configured to provide a data signal from a first one of the source or the drain to the other one of the source or the drain in response to a control signal provided to the gate. A body bias circuit is configured to bias the body of the transistor based on a voltage of the data signal to reduce variation in the on-resistance exhibited by the first transistor. As a result of the reduced variation in the on resistance, attenuation of the data signal is reduced. In one embodiment, the apparatus includes the body bias transistor and a switch. The gate of the body bias transistor is connected to protect the body bias transistor free from the influence of an Electrostatic Discharge (ESD) event.
Description
The part that the application is the applying date is on April 18th, 2014, application number is the U.S. Patent application of 14/256799 continues application, the rights and interests that this U.S. Patent application requires " MOSBodyEffectCompensationforaHigh-SpeedMOSSwitch " by name, the applying date is the U.S. Provisional Patent Application 61/918529 on December 19th, 2013, the two is combined in this all in full.
Technical field
Each aspect of the present invention directing switch circuit, points to the switching circuit based on transistor especially.
Background technology
Transistor is used to various circuit and equipment, with between the source electrode and drain electrode of transistor for the communication of data-signal provides can the path of switch.Transistor is the function of source electrode bulk voltage from the threshold voltage that off state (high resistance) is switched to conducting state (low resistance), and this is called as bulk effect.Due to this bulk effect, transistor resistance in the on-state (being called conducting resistance) may be different along with the different voltage of the data-signal communicated between transistor source from drain electrode.Due to the change of conducting resistance, the data-signal of this communication may be attenuated.
Summary of the invention
The execution mode of each example points to the Method and circuits reduced due to conducting resistance change and signal attenuation in the transistor of bulk effect.In some embodiments, a kind of device comprises transistor, and transistor has source electrode, drain electrode, grid and body end.Transistor arrangement is, in response to the control signal being provided to grid, provides data-signal from first source electrode or drain electrode to another.Body bias circuit is configured to, and the body end of bias transistor based on the voltage of data-signal, to reduce the decay of data-signal.In one embodiment, this device comprises body-biased transistors and switch, and the grid of body-biased transistors is connected with the impact of protective bias transistor from static discharge (ESD) event.
In one embodiment, between the source electrode that the first switch is connected to transistor seconds and the first transistor or in draining first, between the source electrode that second switch is connected to third transistor and the first transistor or another in draining.Further, the grid of transistor seconds is connected between second switch and third transistor, and the grid of third transistor is connected between the first switch and transistor seconds.
In some embodiments, the method for data exchange is provided.Utilize transistor, data-signal is communicated in response to control signal by between the source electrode and the drain electrode of transistor of transistor.Based on the voltage of data-signal, the body end of transistor is biased, to reduce the decay of transistor to data-signal.The method also relates to by opening switch and one of the source electrode or drain electrode of the grid of body-biased transistors and transistor is disconnected, and wherein the grid of body-biased transistors is connected to one of source electrode or drain electrode and between one of the source electrode or drain electrode of body-biased transistors of transistor.
Above discussion/summary should not be considered as describing each execution mode of the present invention or all embodiments.Following accompanying drawing and description also illustrate various execution mode.
Accompanying drawing explanation
By the detailed description carried out below in conjunction with each accompanying drawing, the execution mode of each example more completely can be understood, wherein:
Fig. 1 shows first switching circuit with body bias circuit according to the one or more execution mode of the present invention;
Fig. 2 shows according to the offset body end of one or more execution mode of the present invention to reduce the flow process of signal attenuation;
Fig. 3 has gone out the second switch circuit with body bias circuit according to the one or more execution mode of the present invention; And
Shown in Fig. 4 is the 3rd switching circuit with body bias circuit according to the one or more execution mode of the present invention;
Shown in Fig. 5 is the 4th switching circuit with body bias circuit according to one or more execution mode of the present invention.
Embodiment
The aspect of each execution mode is illustrated by the example in accompanying drawing, and is described in detail, and each execution mode that this place is discussed also can be suitable for amendment and replacement form.But should be understood that, the present invention is not limited to described particular implementation.On the contrary, be intended to cover and allly fall into all modifications of the present invention, equivalent and replace comprising definition each side in the claims.In addition, in the application's full text, " example " of indication is only the use of statement, and non-is restriction.
Should believe, each aspect of the present invention can be applicable in the device of the number of different types relating to transistor switching circuit, system and method.Many aspects of the present invention can be shown by all examples described by context, and the present invention is not limited to described example.
The execution mode of each example points to method and the circuit of conducting resistance change and signal attenuation in the transistor reducing to cause due to bulk effect.In some embodiments, a kind of device comprises transistor, and transistor has source electrode, drain electrode, grid and body end.Transistor arrangement is, in response to the control signal being provided to grid, provides data-signal from first source electrode or drain electrode to another.As previously discussed, due to bulk effect, the conducting resistance of transistor there will be change.Due to the change in conducting resistance, data-signal may be decayed by transistor.Body bias circuit is configured to, and the body end of bias transistor based on the voltage of data-signal, to reduce the change of the conducting resistance of being shown by the first transistor.Due to the reduction of conducting resistance change, the decay of data-signal can be reduced.
Each execution mode differently can be biased the body end of N-type transistor or P-type crystal pipe.In some implementations, body bias circuit is configured to, and by being biased towards smaller in the source voltage of source electrode or the drain voltage of drain electrode by transistor, carrys out the body end of biased N-type transistor.In other realizes, body bias circuit is configured to, and is biased by transistor, carrys out the body end of biased P-type crystal pipe towards the greater in the source voltage of source electrode and the drain voltage of drain electrode.
In some implementations, body bias circuit comprises the first and second switching circuits.For biased N-type transistor, the first switching circuit is configured to, and is less than source voltage in response to drain voltage, the body end of transistor is connected to the drain electrode of transistor.Second switch Circnit Layout is, is greater than source voltage in response to drain voltage, the body end of transistor is connected to the source electrode of transistor.
Conversely, be biased P-type crystal pipe, the first switching circuit is configured to, and is greater than drain voltage in response to drain voltage, the body end of transistor is connected to the drain electrode of transistor.Second switch Circnit Layout is, is less than source voltage in response to drain voltage, the body end of transistor is connected to the source electrode of transistor.
In some embodiments, body bias circuit configures and is arranged as and is biased by the body end of the first transistor, to follow the voltage of input data signal.Such as, body bias circuit can increase the voltage be applied on body end in response to the voltage of the data-signal of input increases, and reduces in response to the voltage reduction of the data-signal of input the voltage be applied on body end.
Further disclose the method for data switch.Utilize transistor, data-signal is communicated in response to control signal by between the source electrode and the drain electrode of transistor of transistor.Based on the voltage of data-signal, the body end of transistor is biased, to reduce the decay of transistor to data-signal.If transistor is N-type transistor, body end is biased by towards smaller in the source voltage of source electrode or the drain voltage of drain electrode.If transistor is P-type crystal pipe, body end is biased by towards the greater in source voltage or drain circuit.Body end can illustratively by being connected respectively to source electrode or drain electrode and being biased towards source voltage or drain voltage by body end.
As shown above, each execution mode can be used for biased N-type or P-type crystal pipe.Although each execution mode is not limited thereto, be simplified illustration, each example is substantially all shown with reference to N-type transistor and describes.
With reference now to diagram, Fig. 1 shows the switching circuit with body bias circuit according to the one or more execution mode of the present invention.Switching circuit 100 comprises transistor 110, and transistor 110 has source electrode (S), drain electrode (D), grid (G) and body end (B).Transistor 110 is configured to, and in response to the control signal be provided on grid (Cntl), provides data-signal (Data) from first source electrode or drain electrode to another in source electrode or drain electrode.As previously discussed, due to bulk effect, the conducting resistance of transistor 110 there will be change.Due to the change in conducting resistance, data-signal (Data) may be decayed by transistor.Body bias circuit 120 is configured to, and based on the drain voltage (Vd) of drain electrode and the source voltage (Vs) of source electrode, the body end of bias transistor, to reduce the change of the conducting resistance that transistor 110 is shown.Due to the reduction of conducting resistance change, the decay of data-signal (Data) can be reduced.
Fig. 2 shows according to the offset body end of one or more execution mode of the present invention to reduce the flow process of signal attenuation.Such as, this flow process can be realized by the body bias circuit shown in Fig. 1.Module 210, the source voltage of monitoring transistor and drain voltage.In this flow process, P-type crystal pipe and the biased of N-type transistor are different.For N-type transistor, flow process is pointed to determination module 214 by determination module 212.If drain voltage Vd is less than source voltage Vs, flow process is pointed to module 218 by determination module 214, is biased by body end towards drain voltage.If drain voltage Vd is not less than source voltage Vs, flow process is pointed to module 220 by determination module 214, is biased by body end towards source voltage.
For P-type crystal pipe, flow process is pointed to determination module 216 by determination module 212.If drain voltage Vd is less than source voltage Vs, flow process is pointed to module 220 by determination module 216, is biased by body end towards source voltage.If drain voltage Vd is not less than source voltage Vs, flow process is pointed to module 218 by determination module 216, is biased by body end towards drain voltage.After module 218 or module 220 are biased by body end, this flow process gets back to module 210, and repeats.This flow process can repeat continuously.
By being biased towards smaller in the source voltage, drain voltage of N-type transistor and towards the greater in the source voltage, drain voltage of P-type crystal pipe by body end, the change of conducting resistance can be reduced.In a kind of emulation realized, nmos pass transistor by the data-signal of 0V-2V, by the change of conducting resistance to be reduced to the change of about 0.3 ohm from the change of about 0.8 ohm.
In this example, this flow process is configured to biased P type or N-type transistor.In some implementations, this flow process can be configured to the transistor (P type or N-type) of an only biased type.
Fig. 3 illustrates that the another kind according to one or more execution modes of the present invention has the switching circuit of body bias circuit.Switching circuit 300 comprises transistor 310, and transistor 110 has source electrode (S), drain electrode (D), grid (G) and body end (B).Transistor 310 is configured to, and in response to the control signal be provided on grid (Cntl), provides data-signal (Data) from first source electrode or drain electrode to another in source electrode or drain electrode.Due to bulk effect, the conducting resistance of transistor 310 there will be change.Due to the change in conducting resistance, data-signal (Data) may be decayed by transistor.Body bias circuit 320 is configured to, and based on the drain voltage (Vd) of drain electrode and the source voltage (Vs) of source electrode, the body end of bias transistor, to reduce the change of the conducting resistance that transistor 310 is shown.In this example, transistor 310 is nmos pass transistor.Body bias circuit 320 is configured to body end to be biased towards the smaller in source voltage or drain voltage.
In this example, body bias circuit 320 comprises the first transistor 322, and it is configured to the drain electrode in response to drain voltage is less than source voltage, the body end of transistor 310 being connected to transistor 310.Body bias circuit 320 also comprises transistor seconds 324, and it is configured to the source electrode in response to source voltage is less than drain voltage, the body end of transistor 310 being connected to transistor 310.Thus the body end of transistor 310 is pulled to the smaller in source voltage and drain voltage by body bias circuit 320.
In this example, because this is biased, body end is not fully towards drain electrode or source voltage charge/discharge.But be less than the threshold switching voltage of transistor 322 and 324 once the difference between the voltage and source/drain voltage of body end, body end and source electrode and drain electrode disconnect by transistor 322 and 324 (also referred to as body-biased transistors).This maintains by drain/source just (be negative for PMOS) voltage to body end, and contributes to preventing ghost effect, and such as breech lock, drain-source are directly leaked.
Shown in Fig. 4 is the 3rd switching circuit with body bias circuit according to the one or more execution mode of the present invention.Switching circuit 400 comprises transistor 410 and body bias circuit 420, and body bias circuit 420 has transistor 422 and 424, its configuration and the element 310,320,322 and 324 be arranged as in the switching circuit of reference shown in Fig. 3.In this example, switching circuit comprises a kilo-ohm level resistor 440 further and is configured to isolation well electromotive force to discharge over the ground, and this can reduce the ghost effect in switching circuit further.In some implementations, switching circuit 400 can also comprise switch 430,432, with by transistor 422 with 424 source/drain terminal be connected with drain electrode end with the source electrode of transistor 410/disconnect.By the source/drain terminal of transistor 422 and 424 and the source electrode of transistor 410 and drain electrode end being disconnected, body bias circuit 420 is not activated.In some embodiments, body bias circuit 420 can be controlled by user or control circuit is enabled/do not enabled.In one embodiment, switch 430 and 432 controls by gate voltage, and this gate voltage controls the gate voltage of transistor 422 and 424 far above being used for.Such as, the gate voltage of switch 430 and 432 can in scope X-Y volt, and the gate voltage of transistor 422 and 424 can in scope 0-4 volt.Often and, switch 430 and 432 can be MOS transistor, and it can have the puncture voltage more much higher than transistor 422 and 424, such as, higher than the twice rank of transistor 422 and 424.
In one embodiment, switching circuit may be subject to the impact of static discharge (ESD) event, and this may cause circuit not meet specific ESD specification.Such as, please refer to Fig. 4, when transistor 422 and 424 is directly connected to outside I/o pad, transistor 422 and 424 is subject to esd event impact.In one embodiment, after the grid of body-biased transistors are connected to switch 430 and 432, the grid opposite outer I/o pad of body-biased transistors 422 and 424 is hidden, with the impact of protective bias transistor from esd event.
Shown in Fig. 5 is the 4th switching circuit with body bias circuit according to one or more execution mode of the present invention, after the grid of body-biased transistors are connected to switch wherein, with the impact of protective bias transistor from esd event.Switching circuit 500 comprises transistor 510 and body bias circuit 520, and body bias circuit 520 has transistor 522 and 524, its configuration and the element 410,420,422 and 424 be arranged as in the switching circuit of reference shown in Fig. 4.In the execution mode of Fig. 5, the grid of transistor 522 and 524 is connected between the source/drain of switch and contrary transistor.Such as, the grid of transistor 522 is connected between the drain electrode of transistor 524 and switch 532, and the grid of transistor 524 are connected between the drain electrode of transistor 522 and switch 530.In the execution mode of Fig. 5, the source/drain terminal of transistor 522,524 is connected with the source electrode of transistor 510 and drain electrode end/disconnects with 532 by switch 530.By the source/drain terminal of transistor 522 and 524 and the source electrode of transistor 510 and drain electrode end being disconnected, body bias circuit 520 is not activated.In some embodiments, body bias circuit 520 can be controlled by user or control circuit is enabled/do not enabled.
The execution mode of this description goes for the types of applications using transistor switching circuit, includes but not limited to for the switch of high-speed communication, reflector, input/output circuitry and/or line drive.High-speed applications can use various communication protocol to carry out data communication, includes but not limited to: DDR, SATA, display interface, PCIe, USB, MIPI, HDMI, v-by-one and Ethernet.
Various module, module or other circuit also can realize one or more for what carry out in the action shown in described herein and/or figure and behavior.In such cases, " module " (being " logical circuit " or " module " sometimes) is a kind of circuit, and it carries out one or more (as voltage bias) in these or relevant action/behavior.Such as, in execution modes more discussed above, one or more module is discrete logical circuit or Programmable Logic Device, configures and be arranged as these action/behaviors carried out as the circuit module in Fig. 2.In certain embodiments, such programmable circuit is one or more computer circuits, is programmed to execution one group of (or many groups) instruction (and/or configuration data).Described instruction (and/or configuration data) form of firmware or software can be stored in memory (circuit), and can read from described memory (circuit).As a kind of example, first module and the second module comprise the set by the hardware based circuit of CPU and one group of instruction existed with form of firmware, wherein the first module comprises a CPU hardware circuit and one group of instruction, and the second module comprises the 2nd CPU hardware circuit and another group instruction.
Specific execution mode points to computer program (such as non-volatile memory device), it comprises machine or computer readable medium, store instruction thereon, instruction can be run by computer (or other electronic equipments), performs these action/behaviors.
Based on the above discussion and describe, person of ordinary skill in the field can make various modifications or variation when strictly conforming to aforementioned embodiments and application to the present invention.Such as, aspect of the present invention and feature are shown in independent accompanying drawing in some cases, but should be understood that, although may not point out in accompanying drawing of the present invention or specification clearly, some feature wherein in a width accompanying drawing can be incorporated in the feature of another accompanying drawing to be implemented.These amendments do not deviate from true spirit of the present invention and scope, comprise shown in following claim.
Claims (19)
1. a device, is characterized in that, comprising:
The first transistor, there is source electrode, drain electrode, grid and body end, the first transistor configures and is arranged as, in response to the control signal being provided to grid, data-signal is provided, the decay of the first transistor data signals due to bulk effect to another in source electrode or drain electrode from first source electrode or drain electrode; And
Body bias circuit, configures and is arranged as the body end of voltage based on data-signal and biased the first transistor, and reduces the first transistor to the decay of data-signal, and wherein said body bias circuit comprises:
Have the transistor seconds of source electrode, drain and gate, wherein source electrode and drain electrode are connected between the body end of the first transistor and the source electrode of the first transistor or in draining first;
Have the third transistor of source electrode, drain and gate, wherein source electrode and drain electrode are connected between the body end of the first transistor and the source electrode of the first transistor or another in draining;
This device comprises further:
First switch, between the source electrode being connected to transistor seconds and the first transistor or in draining first;
Second switch, between the source electrode being connected to third transistor and the first transistor or another in draining;
Wherein the grid of transistor seconds is connected between second switch and third transistor, and the grid of third transistor is connected between the first switch and transistor seconds.
2. device as claimed in claim 1, is characterized in that:
The first transistor is N-type transistor, and due to bulk effect, the conducting resistance between its source electrode from drain electrode changes for the different voltages of data-signal; And
Body bias circuit configures and is arranged as and is biased to smaller between the source voltage and the drain voltage of drain electrode of source electrode by the body end of the first transistor, thus reduces the change of the conducting resistance represented by the first transistor.
3. device as claimed in claim 2, is characterized in that:
Body bias circuit configures and is arranged as
In response to drain voltage is less than source voltage, the drain voltage of the body end of the first transistor to drain electrode is biased; And
In response to source voltage is less than drain voltage, the body end of the first transistor is biased to source voltage.
4. device as claimed in claim 2, is characterized in that:
Transistor seconds configures and is arranged as the drain electrode in response to drain voltage is less than source voltage, the body end of the first transistor being connected to the first transistor; And
Third transistor configures and is arranged as the source electrode in response to drain voltage is greater than source voltage, the body end of the first transistor being connected to the first transistor.
5. device as claimed in claim 1, is characterized in that:
The first transistor is P-type crystal pipe, and due to bulk effect, the conducting resistance between its source electrode from drain electrode changes for the different voltages of data-signal; And
Body bias circuit configuration and be arranged as the body end of the first transistor is biased to the greater between the source voltage and the drain voltage of drain electrode of source electrode, thus the change reducing the conducting resistance represented due to the first transistor.
6. device as claimed in claim 5, is characterized in that:
Body bias circuit configures and is arranged as
In response to drain voltage is greater than source voltage, the body end of the first transistor is biased to drain voltage; And
In response to source voltage is greater than drain voltage, the body end of the first transistor is biased to source voltage.
7. device as claimed in claim 6, is characterized in that:
Transistor seconds configures and is arranged as the drain electrode in response to drain voltage is greater than source voltage, the body end of the first transistor being connected to the first transistor; And
Third transistor configures and is arranged as the source electrode in response to drain voltage is less than source voltage, the body end of the first transistor being connected to the first transistor.
8. device as claimed in claim 1, is characterized in that: body bias circuit configures and is arranged as the body end of biased the first transistor, to follow the voltage of data-signal.
9. a device, is characterized in that, comprising:
The first transistor, has source electrode, drain electrode, grid and body end, and due to bulk effect, the source electrode of described transistor changes for the different voltage of the data-signal inputted from the conducting resistance between drain electrode; And
Body bias circuit, configures and is arranged as the body end of biased the first transistor, to reduce the change of the conducting resistance that the first transistor represents, thus reduces the decay of the data-signal of input;
Body bias circuit comprises:
Have the transistor seconds of source electrode, drain and gate, wherein source electrode and drain electrode are connected between the body end of the first transistor and the source electrode of the first transistor or in draining first;
Have the third transistor of source electrode, drain and gate, wherein source electrode and drain electrode are connected between the body end of the first transistor and the source electrode of the first transistor or another in draining;
This device comprises further:
First switch, between the source electrode being connected to transistor seconds and the first transistor or in draining first;
Second switch, between the source electrode being connected to third transistor and the first transistor or another in draining;
Wherein the grid of transistor seconds is connected between second switch and third transistor, and the grid of third transistor is connected between the first switch and transistor seconds.
10. device as claimed in claim 9, is characterized in that, comprise further:
Switch, comprise described the first transistor, and the Controlling vertex that there is the I/O node being connected to drain electrode, the input/output node being connected to source electrode and be connected to grid, switchgear distribution and be arranged as the data-signal transmitting input in response to Controlling vertex exceedes threshold voltage between I/O node and input/output node; And
Wherein body bias circuit is configured to the body end of biased the first transistor to follow the data-signal of input.
11. devices as claimed in claim 9, is characterized in that:
The first transistor is N-type transistor; And
Body bias circuit configures and is arranged as and is biased to smaller between the source voltage and the drain voltage of drain electrode of source electrode by the body end of the first transistor.
12. devices as claimed in claim 9, is characterized in that:
The first transistor is N-type transistor; And
Transistor seconds configures and is arranged as the drain electrode in response to drain voltage is less than source voltage, the body end of the first transistor being connected to the first transistor; And
Third transistor configures and is arranged as the source electrode in response to drain voltage is greater than source voltage, the body end of the first transistor being connected to the first transistor.
13. devices as claimed in claim 9, is characterized in that:
The first transistor is P-type crystal pipe; And
Transistor seconds configures and is arranged as the drain electrode in response to drain voltage is greater than source voltage, the body end of the first transistor being connected to the first transistor; And
Third transistor configures and is arranged as the source electrode in response to drain voltage is less than source voltage, the body end of the first transistor being connected to the first transistor.
14. 1 kinds of methods, is characterized in that, comprising:
In response to control signal between the source electrode of transistor and the drain electrode of transistor communicated data signal, due to bulk effect, the decay of transistor data signals;
The body end of bias transistor based on the voltage of data-signal, to reduce the decay of transistor to data-signal; And
One of the source electrode or drain electrode of the grid of body-biased transistors and transistor are disconnected by opening switch, wherein the grid of body-biased transistors is connected to one of source electrode and drain electrode and between one of the source electrode and drain electrode of body-biased transistors of transistor.
15. methods as claimed in claim 14, is characterized in that:
Transistor is N-type transistor; And
Offset body end comprises and being biased to the source voltage of source electrode and the drain voltage smaller of drain electrode by body end.
16. methods as claimed in claim 15, it is characterized in that, offset body end comprises:
In response to drain voltage is less than source voltage, the drain voltage of the body end of transistor to drain electrode is biased; And
In response to source voltage is less than drain voltage, the body end of the first transistor is biased to source voltage.
17. methods as claimed in claim 16, is characterized in that:
The body end of transistor is comprised to the drain voltage drained is biased: body end is connected to drain electrode; And
The body end of transistor is comprised to the source voltage of source electrode is biased: body end is connected to source electrode.
18. methods as claimed in claim 14, is characterized in that:
Transistor is P-type crystal pipe; And
Drain voltage in response to drain electrode is greater than the source voltage of source electrode, is biased by the drain voltage of the body end of transistor to drain electrode; And
Be greater than drain voltage in response to source voltage, the body end of transistor is biased to source voltage.
19. 1 kinds of devices, is characterized in that, comprising:
The first transistor, has source electrode, drain electrode, grid and body end, and the first transistor configures and is arranged as, and in response to the control signal being provided to grid, provides data-signal, the decay of the first transistor data signals due to bulk effect from input to output; And
Body bias circuit, configure and be arranged as the body end of voltage based on data-signal and biased the first transistor, to reduce the decay of the first transistor to data-signal, wherein body bias circuit comprises:
First body-biased transistors, has source electrode, drain and gate, and wherein source electrode and drain electrode are connected between the body end of the first transistor and the input of the first transistor;
Second body-biased transistors, has source electrode, drain and gate, and wherein source electrode and drain electrode are connected between the body end of the first transistor and the output of the first transistor;
This device comprises further:
Be connected to the first switch between the first body-biased transistors and the input of the first transistor;
Be connected to the second switch between the second body-biased transistors and the output of the first transistor;
Wherein the grid of the first body-biased transistors is connected between second switch and the second body-biased transistors, and the grid of the second body-biased transistors is connected between the first switch and the first body-biased transistors.
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| US14/328,472 | 2014-07-10 | ||
| US14/328,472 US9264034B2 (en) | 2013-12-19 | 2014-07-10 | Circuit and method for body biasing |
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| CN105262467B CN105262467B (en) | 2018-05-04 |
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| CN110212900A (en) * | 2019-06-10 | 2019-09-06 | 桂林电子科技大学 | A kind of double trap CMOS complementary switch for eliminating bulk effect and substrate leakage |
| WO2024022226A1 (en) * | 2022-07-25 | 2024-02-01 | 上海唯捷创芯电子技术有限公司 | Radio-frequency switch circuit supporting high-power mode, chip, and electronic device |
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| CN102484434B (en) * | 2009-09-11 | 2014-10-01 | 株式会社理光 | Dead Time Generating Circuits and Motor Control Devices |
| CN104170257A (en) * | 2012-03-30 | 2014-11-26 | 德克萨斯仪器股份有限公司 | Source-follower based voltage mode transmitter |
| CN104769844A (en) * | 2012-11-15 | 2015-07-08 | 德州仪器公司 | Wide Common Mode Range Transmission Gate |
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| CN110212900A (en) * | 2019-06-10 | 2019-09-06 | 桂林电子科技大学 | A kind of double trap CMOS complementary switch for eliminating bulk effect and substrate leakage |
| WO2024022226A1 (en) * | 2022-07-25 | 2024-02-01 | 上海唯捷创芯电子技术有限公司 | Radio-frequency switch circuit supporting high-power mode, chip, and electronic device |
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