CN105304634B - Three-dimensional storage device - Google Patents

Abstract

The invention discloses a three-dimensional storage device. The three-dimensional memory device comprises a memory element area, a first step structure, a second step structure, a first conductive strip and a second conductive strip. The memory element region includes a first stacked structure and a second stacked structure. The first stacked structure includes a first semiconductor strip, and the second stacked structure includes a second semiconductor strip. The first step structure is located at one side of the storage element area, and one end of the first semiconductor strip is connected with the first step structure. The second stepped structure is located on the opposite side of the storage element region, and one end of the second semiconductor strip is connected with the second stepped structure. The first conductive strip is coupled to the first semiconductor strip through the first ladder structure. The second conductive strip is coupled to the second semiconductor strip through the second step structure.

Description

3D storage device

technical field

The present invention relates to a storage device, and in particular to a planar three-dimensional storage device provided with a plurality of storage units.

Background technique

With the advancement of integrated circuit manufacturing technology, a three-dimensional memory device with stacked memory cells on multiple planes has been developed to obtain a larger storage capacity.

In a three-dimensional memory array, the bit lines are arranged to access different layers in the memory array, so the configuration of the bit lines significantly affects the speed of reading and/or programming the memory. Therefore, how to provide a memory device that can improve memory reading and/or programming bandwidth is one of the topics that the industry is currently working on.

Contents of the invention

The present invention relates to a three-dimensional storage device. The conductive structure of the three-dimensional storage device is arranged to improve the reading and programming bandwidth of the memory.

According to an embodiment, a three-dimensional integrated circuit is proposed, including a storage element region, a first ladder structure, a second ladder structure, a first conductive strip, and a second conductive strip. The storage element area includes a first stacked structure and a second stacked structure. The first stack structure includes a first semiconductor strip, and the second stack structure includes a second semiconductor strip. The first ladder structure is located on one side of the storage element region, and one end of the first semiconductor strip is connected to the first ladder structure. The second ladder structure is located on the opposite side of the storage element region, and one end of the second semiconductor strip is connected to the second ladder structure. The first conductive strip is coupled to the first semiconductor strip through the first ladder structure. The second conductive strip is coupled to the second semiconductor strip through the second ladder structure.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the preferred embodiments are specifically cited below, together with the attached drawings, and are described in detail as follows:

Description of drawings

FIG. 1 is a schematic diagram of a three-dimensional storage device according to an embodiment.

FIG. 2 is a top view of a three-dimensional storage device.

FIG. 3 is a schematic diagram illustrating an example of a read operation of a three-dimensional storage device.

FIG. 4 shows a waveform diagram of signals for reading a three-dimensional memory device.

FIG. 5 is a schematic diagram illustrating another example of a read operation of a three-dimensional storage device.

FIG. 6 illustrates a sense amplifier for reading a 3D memory device.

FIG. 7 is a waveform diagram of relevant signals read by a sense amplifier from a three-dimensional memory device.

FIG. 8 is a top view of a three-dimensional storage device according to an embodiment of the invention.

【Symbol Description】

100, 800: three-dimensional storage device

102, 802(1), 802(2): storage element area

104A, 104B, 804A, 804B, 804C: ladder structure

106(1)-106(8), 806(1)-806(8): conductive strip

108(1)-108(8): laminated structure

114: Conductive plug

112(1)-112(n), 116(1)-116(8), 118(1)-118(8), _{120_odd} , _{120_even} : Conductive structure

702: Sense Amplifier

A1-A4, B1-B4: Semiconductor strips

ML1: first metal layer

ML2: second metal layer

ML3: third metal layer

SV: Sensing signal

GV: mask signal

MS: memory cell string

P1: Precharge phase

P2: Setting and Sensing Phase

P3: Restoration phase

GSL: Ground Select Line Signal

CSL: Source Line Signal

SSL _{_sel} : Selected serial selection line signal

SSL _{_unsel} : unselected serial selection line signal

Channel: memory cell channel voltage

ML3BL: The bit line signal of the third metal layer

WL _{_unsel} : unselected word line signal

WL _{_sel} : Selected word line signal

BLCLAMP: bit line clamp signal

CSL, SSL, BLSEL, BLC, BLK, BLC_I, LPC, BRST, BRSTN, STBN, CNB: Signal

Detailed ways

The following is a detailed description of the embodiments, which are only used as examples for illustration and will not limit the scope of protection of the present invention. In addition, the drawings in the embodiments omit unnecessary components to clearly show the technical characteristics of the present invention.

Please refer to Figure 1 and Figure 2 at the same time. FIG. 1 is a schematic diagram of a three-dimensional storage device 100 according to an embodiment. FIG. 2 shows a top view of the 3D storage device 100 . The three-dimensional memory device 100 includes a memory element region 102, ladder structures 104A, 104B, and a plurality of conductive strips 106(1)-106(8). A plurality of memory cells are defined in the memory element area 102 , and each conductive strip 106 ( 1 )- 106 ( 8 ) is, for example, a bit line (BL) of a memory cell string.

The storage element region 102 includes a plurality of rows of stacked structures 108(1)-108(8) extending in the X direction. Laminated structures 108(1), 108(3), 108(5), 108(7) in odd rows and laminated structures 108(2), 108(4), 108(6), 108(8 in even rows ) staggered. Stack 108(1) is parallel to and adjacent to stack 108(2); stack 108(3) is parallel to and adjacent to stack 108(4); stack 108(5) is parallel to and adjacent to stack Structure 108(6) is parallel and adjacent; stack structure 108(7) is parallel and adjacent to stack structure 108(8). Stacks 108(1)-108(8) each include a plurality of separate semiconductor strips (e.g., semiconductor strips A1-A4 in stack 108(1), semiconductor strips B1-A4 in stack 108(2) B4). As shown in FIG. 1 , the semiconductor strips A1 - A4 are located on different layers and separated by dielectric strips, and the semiconductor strips B1 - B4 are located on different layers and separated by dielectric strips. In order to clearly show the structure of the memory device of the embodiment, FIG. 1 does not show the part of the dielectric strip.

The conductive structures 112(1)-112(n) are disposed on the sidewalls of the stacked structures 108(1)-108(8) and are spaced apart from each other along the Z direction, for example as word lines ( word line, WL), where n is a positive integer greater than 1.

The stepped structure 104A is located on one side of the storage element region 102 , and one end of the semiconductor strips of the stacked structures 108 ( 1 ), 108 ( 3 ), 108 ( 5 ), and 108 ( 7 ) in odd rows is connected to the stepped structure 104A. The stepped structure 104B is located on the opposite side of the storage element region 102 , and one end of the semiconductor strips of the even-numbered stacked structures 108 ( 2 ), 108 ( 4 ), 108 ( 6 ), and 108 ( 8 ) is connected to the stepped structure 104B.

Conductive strips 106(1), 106(3), 106(5), 106(7) are arranged alternately with conductive strips 106(2), 106(4), 106(6), 106(8). Conductive strips 106(1), 106(3), 106(5), 106(7) are coupled to stacked structures 108(1), 108(3), 108(5), 108(7) of semiconductor strips. In the example of FIG. 1 , the conductive strips 106(1), 106(3), 106(5), and 106(7) are located in the third metal layer ML3 above the laminated structures 108(1)-108(8), And respectively connected to different layers of the ladder structure 104A through conductive plugs (plug) 114, so as to be electrically connected to different layers in the stacked structure 108(1), 108(3), 108(5), 108(7) semiconductor strips. Similarly, the conductive strips 106(2), 106(4), 106(6), and 106(8) are located in the third metal layer ML3, and are respectively coupled to the stacked structure 108(2), through the ladder structure 104B. Different layers of semiconductor strips in 108(4), 108(6), 108(8).

In the example of FIG. 1, conductive strips 106(1)-106(8) are parallel to the semiconductor strips of each stack 108(1)-108(8). The conductive strips 106( 1 ), 106( 3 ), 106( 5 ), and 106( 7 ) straddle the storage element region 102 and above the stepped structure 104B, and are electrically isolated from the stepped structure 104B. The conductive strips 106 ( 2 ), 106 ( 4 ), 106 ( 6 ), and 106 ( 8 ) straddle the storage element region 102 and above the stepped structure 104A, and are electrically isolated from the stepped structure 104A. The pitch of two adjacent semiconductor strips located on the same layer (such as the semiconductor strip A1 of the stacked structure 108(1) and the semiconductor strip B1 of the stacked structure 108(2) located on the same layer) is related to the relationship between the two adjacent conductive strips. The strips (eg, conductive strips 106(1) and 106(2)) are equally spaced. Compared with the traditional three-dimensional memory structure, the three-dimensional memory device of the embodiment of the present invention can provide larger reading and programming bandwidth.

In the example of FIG. 1, the conductive structures 116(1), 116(3), 116(5), and 116(7) are respectively arranged in the odd-numbered stacked structures 108(1), 108(3), and 108(5). , 108(7) on the sidewalls of the semiconductor strips and adjacent to the ladder structure 104A, used as serial connection selection lines for odd-numbered stacked structures 108(1), 108(3), 108(5), and 108(7) . Similarly, the conductive structures 116(2), 116(4), 116(6), and 116(8) are arranged in the even-numbered stacked structures 108(2), 108(4), 108(6), 108(8) respectively. ) on the sidewall of the semiconductor strip and adjacent to the ladder structure 104B, used as the serial connection selection line of the even-numbered stacked structures 108(2), 108(4), 108(6), and 108(8). In other words, in the example of FIG. 1 , the serial selection gates of the odd pages and the even pages are arranged in opposite directions.

The conductive structures 116(1)-116(8) are electrically connected to the series selection line formed by the first metal layer ML1 and the second metal layer ML2, and are connected by providing a voltage to the first metal layer ML1 and the second metal layer ML2. The formed serial selection line can control the corresponding semiconductor strips of the stacked structure to be in a selected state or an unselected state.

Conductive structures 118(1), 118(3), 118(5), 118(7) are arranged on semiconductor strips of odd-numbered stacked structures 108(1), 108(3), 108(5), 108(7) The sidewalls of the stacked structures 108(1), 108(3), 108(5), and 108(7) are located adjacent to the stepped structure 104B. One end of the semiconductor strips of the stack structures 108(1), 108(3), 108(5), 108(7) is terminated in a conductive structure 118(1), 118(3), 118(5), 118(7 ). Similarly, conductive structures 118(2), 118(4), 118(6), 118(8) are disposed on even rows of stacked structures 108(2), 108(4), 108(6), 108(8) The sidewalls of the semiconductor strips are located adjacent to the stepped structure 104A, serving as source lines of the stacked structures 108(2), 108(4), 108(6), and 108(8). One end of the semiconductor strips of the stack structures 108(2), 108(4), 108(6), 108(8) is terminated in a conductive structure 118(2), 118(4), 118(6), 118(8 ).

The conductive structure _{120_odd} is disposed on the sidewalls of the semiconductor strips of the odd-numbered stacked structures 108(1), 108(3), 108(5), and 108(7) to serve as the stacked structures 108(1), 108 (3), 108(5), 108(7) ground selection wires. Similarly, the conductive structures _{120_even} are disposed on the sidewalls of the semiconductor strips of the stacked structures 108(2), 108(4), 108(6), and 108(8) in even rows to serve as the stacked structures 108(2 ), 108(4), 108(6), 108(8) ground selection wires. In one embodiment, the conductive structure serving as the ground selection line is located between the conductive structure serving as the series selection line and the conducting structure serving as the source line, and adjacent to the conductive structure serving as the source line.

It can be understood that the number of rows of the stacked structure, the number of layers of semiconductor strips, the number of columns of word lines, the number of conductive strips, etc. in the above embodiment are not limited to the numbers shown in FIG. into greater or lesser numbers. In addition, the conductive material in the above embodiments may include metal, polysilicon, metal silicide, or other suitable materials. The dielectric material may include oxide or silicide, such as silicon oxide, silicon nitride, or silicon oxynitride, or other suitable materials.

Please refer to FIG. 3 , which shows an example of the read operation of the three-dimensional storage device 100 . In the example of FIG. 3, an odd page may be selected first. By applying the sensing signal SV to the conductive strips 106(1), 106(3), 106(5), 106(7) as bit lines to sense the K layer (K=4 in this example) in the memory device 100 The memory cells are shielded by applying a mask signal GV (such as ground voltage) to the conductive strips 106(2), 106(4), 106(6), 106(8). Next, the selected even-numbered pages are turned on. In this embodiment, the sensing operation can be performed in one word line setting waveform, thus essentially reading two pages in one waveform, thus doubling the memory read speed.

FIG. 4 shows an example of a signal waveform for reading the three-dimensional memory device 100 . In the pre-charge phase P1, the ground select line signal (GSL) is set to high voltage, the source line signal (CSL) is set to ground voltage, and the cascade select line signal ( _{SSL_sel} ) and unselected cascade The select line signal ( _{SSL_unsel} ) is set high to set the memory cell channel voltage (Channel) as the ground level. During the set and sense phase P2, the selected string select line ( _{SSL_sel} ) is applied with a pass voltage (about 6 volts); the unselected string select line signal ( _{SSL_unsel} ) is set to a low voltage ( about -2 volts); the bit line signal (ML3BL) of the third metal layer is set to the sense voltage (about 1 volt); the unselected word line signal ( _{WL_unsel} ) is set to the pass voltage (about 6 volts ); the selected word line signal (WL _{_sel} ) is set to a low voltage (less than about 0 volts). By applying a bit line clamp signal (BLCLAMP), the data stored in the memory cell can be sensed through the sensing circuit. The set bit line and sense phase repeats, for example, the reading of two pages. In the recovery phase P3, the memory cell channel is discharged to recover to the ground voltage. It can be understood that the waveform diagram in FIG. 4 is only used for illustration, and is not intended to limit the present invention.

Please refer to FIG. 5 , which shows another example of the read operation of the three-dimensional storage device 100 . In the example of FIG. 5 , two pages can be selected for reading at the same time, one of which is an odd page and the other is an even page. To double the memory read speed, bit lines and ground select lines are set, and all cascade select lines are turned off.

Please refer to Figure 6 and Figure 7. FIG. 6 shows an example of the sense amplifier 702 for reading the 3D memory device 100 . FIG. 7 shows an example of a waveform diagram of relevant signals read by the sense amplifier 702 from the three-dimensional memory device 100 . As shown in FIG. 7 , the relevant signals of the three-dimensional storage device 100 include signals CSL, SSL, BLSEL, BLC, BLK, BLC_I, LPC, BRST, BRSTN, STBN, and CNB. The sense amplifier 702 performs conventional memory sensing operations through the above signals, so details of the operation of the sense amplifier 702 will not be repeated here. For a memory cell string MS of the three-dimensional memory device 100 , the sense amplifier 702 performs current sensing to read data stored in a specific memory cell.

FIG. 8 shows a top view of a three-dimensional storage device 800 according to an embodiment of the present invention. The three-dimensional memory device 800 includes a plurality of memory element regions. As shown in FIG. 8 , a three-dimensional memory device 800 includes a plurality of memory element areas 802 ( 1 ) and 802 ( 2 ). The storage element regions 802(1), 802(2) are interleaved with the plurality of ladder structures 804A, 804B, 804C. The arrangement of the stacked structures in the storage element regions 802(1) and 802(2) is the same as that of the previous embodiment, so it will not be repeated here. Conductive strips 806(1)-806(8) are parallel to the stack structures in memory element regions 802A and 802B. The conductive strips 806(1), 806(3), 806(5), and 806(7) are electrically connected to the ladder structures 804A and 804C through conductive plugs, and are electrically isolated from the ladder structure 804B (not connected to the ladder structure 804B ). Conductive strips 806(2), 806(4), 806(6), 806(8) are electrically connected to ladder structure 804B through conductive plugs, and are electrically isolated from ladder structures 804A, 804C (not from ladder structures 804A, 804C connection). In other words, the conductive strips 806(1), 806(3), 806(5), and 806(7) are electrically connected to the ladder structures in odd columns. The conductive strips 806(2), 806(4), 806(6), 806(8) are electrically connected to the ladder structures of the even columns. In this embodiment, the position of each stepped structure 804A- 804C can be translated along the X direction. For example, a shift-scamble design can be used to average the bitline sense capacitance.

According to the above, the three-dimensional memory device of the embodiment of the present invention provides a bit line design with dense pitch. Due to the increased number of bit lines, the 3D memory device of the embodiments of the present invention can provide improved read and program bandwidth compared to conventional 3D memory structures.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (8)

1. a kind of three-dimensional memory devices, including：

One memory element area, including：

One first laminated construction, including one first semiconductor bar；And

One second laminated construction, including one second semiconductor bar, second laminated construction is parallel with first laminated construction and phase It is adjacent；

One first hierarchic structure, the side outside the memory element area, one end of first semiconductor bar connect first rank Terraced structure；

One second hierarchic structure, the offside outside the memory element area, one end of second semiconductor bar connect the second-order Terraced structure；

One first conductive bar, first semiconductor bar is coupled to through first hierarchic structure；And

One second conductive bar, through the second ladder structure couples to second semiconductor bar；

Wherein between the spacing of first semiconductor bar and second semiconductor bar and first conductive bar and second conductive bar Away from equal.

2. three-dimensional memory devices according to claim 1, wherein the memory element area further include：

Multiple first laminated construction, including multiple first semiconductor bars separated from each other；And

Multiple second laminated construction, including multiple second semiconductor bars separated from each other, these first laminated construction and this A little second laminated construction are staggered.

3. three-dimensional memory devices according to claim 2, including：

Multiple first conductive bars, these first semiconductor bars of different layers are respectively connected to through first hierarchic structure；With And

Multiple second conductive bars, these second semiconductor bars of different layers are respectively connected to through second hierarchic structure, this A little first conductive bars are staggered with these second conductive bars.

4. three-dimensional memory devices according to claim 1, wherein first conductive bar are across the memory element area and are somebody's turn to do The top of second hierarchic structure, and electrically isolated with second hierarchic structure；Second conductive bar across the memory element area with And the top of first hierarchic structure, and electrically isolated with first hierarchic structure.

5. a kind of three-dimensional memory devices, including：

The one first memory element area in multiple memory element areas, wherein these memory element areas includes：

One first laminated construction, including one first semiconductor bar；And

One second laminated construction, including one second semiconductor bar, second laminated construction is parallel with first laminated construction and phase It is adjacent；

Multiple hierarchic structures, these hierarchic structures are staggered with these memory element areas；

One first conductive bar, first semiconductor bar is coupled to through one first hierarchic structure of these hierarchic structures, wherein should First conductive bar is electrically connected to these hierarchic structures of odd column；And

One second conductive bar, through these hierarchic structures one second ladder structure couples to second semiconductor bar, wherein should Second conductive bar is electrically connected to these hierarchic structures of even column；

Wherein between the spacing of first semiconductor bar and second semiconductor bar and first conductive bar and second conductive bar Away from equal.

6. three-dimensional memory devices according to claim 5, wherein the first memory element area further include：

Multiple first laminated construction, including multiple first semiconductor bars separated from each other；And

Multiple second laminated construction, including multiple second semiconductor bars separated from each other, these first laminated construction and this A little second laminated construction are staggered.

7. three-dimensional memory devices according to claim 6, including：

Multiple first conductive bars, these first semiconductor bars of different layers are respectively connected to through first hierarchic structure；With And

Multiple second conductive bars, these second semiconductor bars of different layers are respectively connected to through second hierarchic structure, this A little first conductive bars are staggered with these second conductive bars.

8. three-dimensional memory devices according to claim 5, wherein these hierarchic structures of first conductive bar and even column Electrically isolate；These hierarchic structures of second conductive bar and its ordered series of numbers electrically isolate.