CN105321553B - A kind of static random access memory cell of anti-single particle effect - Google Patents

Abstract

The present invention provides a static random access memory unit with anti-single event effect. The storage unit at least includes: a first cross-coupled inverter, which is composed of a first pull-up transistor and a second pull-up transistor; a second cross-coupled inverter The inverter is composed of a first pull-down tube and a second pull-down tube; the transmission tube is composed of a first access tube, a second access tube, a third access tube and a fourth access tube. The static random access memory unit of the present invention can effectively prolong the feedback time required for storage unit flipping, and can improve the anti-single event flipping ability of the storage unit under the condition that the recovery time remains unchanged; the anti-single event static random access memory unit of the present invention adopts The process is fully compatible with the digital logic process, has small parasitic capacitance, low power consumption, and natural anti-single event latch-up capability, and will not increase additional process costs.

Description

A Static Random Access Memory Unit Anti-Single Event Effect

technical field

The invention belongs to the technical field of memory design, and relates to a static random access memory unit, in particular to a static random access memory unit resistant to single event effect.

Background technique

The traditional 6T SRAM unit, as shown in Figure 1, is composed of two pull-up tubes, pull-down tubes and access tubes; due to the harsh working environment of aerospace electronic equipment, the memory unit is exposed to the radiation of various high-energy particles; However, memories are sensitive to high particle radiation. Traditional memory cells are generally difficult to meet radiation resistance requirements; therefore, designers often make improvements on the basis of traditional memory cells to improve the radiation resistance of the cells.

Single event effects and total dose effects are the most common and important two types of radiation effects.

The so-called single event effect, as shown in Figure 2, refers to the incident of high-energy particles into the sensitive area (for bulk silicon devices, the sensitive area refers to the reverse-biased PN junction at the drain end; for silicon-on-insulator devices, it refers to When the device is turned off (the body region when the device is off), the energy of the particle is absorbed by the silicon material. According to the solid energy band theory, the electrons in the valence band can gain energy and jump to the conduction band, and the corresponding holes transition downward in the valence band. to a higher energy position, so that both electrons and holes become freely moving carriers; due to the existence of the electric field applied by the surrounding voltage, the freely moving carriers move in a directional manner to form a current, but the lifetime of the carriers Limited, so the final current is a transient current; the transient current causes a voltage drop in the circuit within the unit, causing the stored data to change. This effect of logic errors caused by a single particle in the storage unit is called the single event effect .

There are many methods of single particle reinforcement, most of which are to extend the time of the feedback loop to reduce the impact of single particles; such as adding resistance or capacitance to the loop, and adding resistance and capacitance to form an RC loop, the following is the loop Add a schematic diagram of resistors to illustrate, as shown in Figure 2, assuming that the Q storage node stores a high level, at this time the first pull-up transistor (PU1) and the second pull-down transistor (PD2) are turned on; the second pull-down transistor ( PU2) and the first pull-down tube (PD1) are cut off; when high-energy particle radiation occurs, the potential of point Q drops; on the one hand, the gate of the first pull-up tube is at a low level, so VDD charges Q to make the potential rise On the other hand, the potential of point Q drops, and the second pull-up tube is slowly turned on, so VDD charges QB, and the potential of QB rises; it will be coupled to the gate of the first pull-down tube, making the potential of point Q further Therefore, the former makes the potential of point Q increase and restores the original potential. This recovery process is called recovery time; the latter makes the potential of point Q decrease, further reducing the potential of point Q, and forming a positive feedback. This feedback process is called It is the feedback time; adding a resistor in the feedback loop means prolonging the feedback time, making the Q point potential drop slower, trying to maintain a high level, so that the storage node keeps the original data unchanged.

The so-called total dose effect means that high-energy particles are incident into the insulating layer and ionize electrons and holes. Due to the existence of the electric field, electrons are easy to drift to VDD for recombination. Relatively speaking, holes move slowly and will be in the insulating layer. Accumulate in the MOS tube and induce corresponding electrons inside the MOS tube, causing the leakage of the tube, and these leakages are not controlled by the gate of the MOS tube. circuit performance. In silicon-on-insulator technology, there are many ways to strengthen the total dose. The common way to strengthen the device is to lead out the body region of the MOS tube and connect it to a fixed potential, thereby reducing the total dose effect.

Although the introduction of passive devices such as resistors or capacitors in the storage unit can improve the anti-single event effect, the resistance value of the resistor and the capacitance value of the capacitor are large in magnitude, and it must use additional processes to manufacture the resistors and capacitors; moreover, Even if these passive devices are manufactured, their area is unbearable for the storage unit, and it has a fatal impact on the SRAM unit.

In view of this, in order to enhance the anti-single event capability of the SRAM unit, the present invention proposes a method of prolonging the feedback time to improve the anti-single event capability; in addition, the silicon-on-insulator technology and the body-extraction technology can also be used to improve the anti-single event capability. Total dosing capacity; this process embodies one concept of the present invention.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a SRAM unit resistant to single event effects, which is used to solve the complicated manufacturing process caused by the introduction of resistors and capacitors in the random SRAM in the prior art. The problem of large device area.

In order to achieve the above purpose and other related purposes, the present invention provides a static random access memory unit that is resistant to single event effects, and the memory unit at least includes:

The first cross-coupled inverter is composed of a first pull-up transistor and a second pull-up transistor;

The second cross-coupled inverter is composed of a first pull-down transistor and a second pull-down transistor;

The transmission pipe is composed of a first access pipe, a second access pipe, a third access pipe and a fourth access pipe.

Preferably, the gate of the first pull-up transistor is connected to the drain of the second pull-up transistor, and the drain of the first pull-up transistor is connected to the gate of the second pull-up transistor, so Both the source of the first pull-up transistor and the source of the second pull-up transistor are connected to a high level;

The gate of the first pull-down transistor is connected to the source of the third access transistor and the drain of the fourth access transistor, and the drain of the first pull-down transistor is connected to the drain of the first pull-up transistor , the gate of the second pull-down transistor is connected to the source of the first access transistor and the drain of the second access transistor, the drain of the second pull-down transistor is connected to the second pull-up transistor The drains are connected, and the source of the first pull-down transistor and the source of the second pull-down transistor are both connected to a low level;

The source of the first access transistor is connected to the drain of the second access transistor, the drain of the first access transistor is connected to the bit line of the memory cell, and the source of the second access transistor is connected to the second access transistor. The drain of a pull-up transistor and the drain of the first pull-down transistor are connected to form a first storage node, and the gate of the first access transistor and the gate of the second access transistor are controlled by word lines;

The source of the third access transistor is connected to the drain of the fourth access transistor, the drain of the third access transistor is connected to the reverse bit line of the memory cell, and the source of the fourth access transistor is connected to the drain of the fourth access transistor. The drain of the second pull-up transistor is connected to the drain of the second pull-down transistor to form a second storage node, and the gates of the third access transistor and the gate of the fourth access transistor are controlled by the word line.

Preferably, the gate of the first pull-up transistor is connected to the drain of the second pull-up transistor, and the drain of the first pull-up transistor is connected to the gate of the second pull-up transistor, so Both the source of the first pull-up transistor and the source of the second pull-up transistor are connected to a high level;

The gate of the first pull-down transistor is connected to the drain of the fourth access transistor, the drain of the first pull-down transistor is connected to the drain of the first pull-up transistor, and the source of the first access transistor electrode and the source of the second access transistor are connected to form the first storage node, the gate of the second pull-down transistor is connected to the drain of the second access transistor, and the drain of the second pull-down transistor is connected to the second upper The drain of the pull-down transistor, the source of the third access transistor, and the source of the fourth access transistor are connected to form a second storage node, and the source of the first pull-down transistor and the source of the second pull-down transistor are connected to each other. low level;

The drain of the first access transistor is connected to the bit line of the memory cell, and the gate of the first access transistor and the gate of the second access transistor are both controlled by the word line;

The drain of the third access transistor is connected to the reverse bit line of the memory cell, and the gate of the third access transistor and the gate of the fourth access transistor are both controlled by the word line.

Preferably, both the first pull-up tube and the second pull-up tube are PMOS tubes, and the sizes of the two tubes are strictly matched to increase the stability of the unit.

Preferably, both the first pull-down tube and the second pull-down tube are NMOS tubes, and the sizes of the two tubes are strictly matched to increase the stability of the unit.

Preferably, the first pull-up tube, the second pull-up tube, the first pull-down tube and the second pull-down tube all use body extraction technology to connect the body region to a fixed potential.

Preferably, the body regions of the first pull-up transistor and the second pull-up transistor are connected to a high level, and the body regions of the first pull-down transistor and the second pull-down transistor are connected to a low level.

Preferably, the first access tube, the second access tube, the third access tube and the fourth access tube are all NMOS tubes.

Preferably, the fabrication substrate of the anti-single event effect SRAM unit is a silicon-on-insulator (SOI) substrate.

Also provided is an application of using the static random storage unit to improve the anti-single event effect.

As mentioned above, in the anti-single event effect SRAM unit of the present invention, the memory unit includes at least a first cross-coupled inverter, which is composed of a first pull-up transistor and a second pull-up transistor; the second cross-coupled The type inverter is composed of a first pull-down tube and a second pull-down tube; the transmission tube is composed of a first access tube, a second access tube, a third access tube and a fourth access tube. The present invention can effectively prolong the feedback time required for memory cell flipping, and can improve the anti-single event flipping ability of the storage cell under the condition of constant recovery time; the process and digital logic adopted by the anti-single event static random access memory cell The process is fully compatible, and has the advantages of small parasitic capacitance, low power consumption, and natural anti-single event latch-up capability, while not increasing additional process costs.

Description of drawings

Figure 1 is a circuit schematic diagram of a traditional SRAM6T unit.

FIG. 2 is a schematic circuit diagram of a SRAM6T unit in the prior art that adds resistance to the single event effect.

FIG. 3 is a schematic circuit diagram of the anti-single event effect SRAM unit in Embodiment 1 of the present invention.

FIG. 4 is a schematic circuit diagram of a single event effect resistant SRAM unit in Embodiment 2 of the present invention.

Component designation description

10 First cross-coupled inverter

20 Second cross-coupled inverter

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to attached picture. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Embodiment one

As shown in FIG. 3 , the present invention provides a single-event-resistant SRAM unit, which at least includes: a first cross-coupled inverter 10, a second cross-coupled inverter 20, and a transmission tube .

The first cross-coupled inverter 10 is composed of a first pull-up transistor and a second pull-up transistor. As an example, both the first pull-up transistor and the second pull-up transistor are PMOS transistors, which are denoted as PU1 and PU2 respectively. The dimensions of the two pull-up tubes are strictly matched to increase the stability of the storage unit.

The second cross-coupled inverter 20 is composed of a first pull-down transistor and a second pull-down transistor. As an example, both the first pull-down transistor and the second pull-down transistor are NMOS transistors, which are denoted as PD1 and PD2 respectively. The dimensions of the two pull down tubes are strictly matched to increase the stability of the storage unit.

The transmission pipe is controlled by the word line and is composed of a first access pipe, a second access pipe, a third access pipe and a fourth access pipe. As an example, the first access transistor, the second access transistor, the third access transistor and the fourth access transistor are all NMOS transistors, which are respectively denoted as AC1, AC2, AC3, and AC4.

In this embodiment, the gate of the first pull-up tube PU1 is connected to the drain of the second pull-up tube PU2; the source of the first pull-up tube PU1 is connected to a high level; The drain of the pipe PU1 is connected to the gate of the second pull-up pipe PU2;

The gate of the second pull-up tube PU2 is connected to the drain of the first pull-up tube PU1; the source of the second pull-up tube PU2 is connected to a high level; The drain is connected to the gate of the first pull-up transistor PU1.

The gate of the first pull-down transistor PD1 is connected to the source QB' (or drain) of the third access transistor AC3 and the drain QB' (or source) of the fourth access transistor AC4 The drain of the first pull-down tube PD1 is connected to the drain of the first pull-up tube PU1 and the source (or drain) of the second access tube AC2; the first pull-down tube The source of PD1 is connected to low level;

The gate of the second pull-down transistor PD2 is connected to the source Q' (or drain) of the first access transistor AC1 and the drain Q' (or source) of the second access transistor AC2; The drain of the second pull-down transistor PD2 is connected to the drain of the second pull-up transistor PU2 and the source (or drain) of the fourth access transistor AC4; the source of the second pull-down transistor PD2 Pole connected to low level.

For the transfer transistor controlled by the word line, the first access transistor AC1 and the second access transistor AC2 form a series loop between the bit line BL and the first storage node Q; the first access transistor AC1 and the second access transistor AC2 The gate of the gate is controlled by the word line WL; the source Q' (or drain) of the first access transistor AC1, and the drain Q' (or source) of the second access transistor AC2 control the second pull-down transistor PD2 The gate of the third access transistor AC3 and the fourth access transistor AC4 form a series loop of the reverse bit line BLB and the second storage node QB; the gates of the third access transistor AC3 and the fourth access transistor AC4 are both Controlled by the word line WL; the source QB' (or drain) of the third access transistor AC3 and the drain QB' (or source) of the fourth access transistor AC4 control the gate of the first pull-down transistor PD2.

The specific working mode of the memory unit corresponding to the first embodiment is described in detail below:

The memory cell has three working states: When the memory cell is in the writing state, such as writing "0" data: first pull the bit line BL low, raise the reverse bit line BLB, and then raise the word line WL, the first The access tube AC1 and the second access tube AC2 work in the linear area, the third access tube AC3 works in the saturation area, and the fourth access tube AC4 works in the linear area. Through charging and discharging, the first storage node Q is finally pulled to low level, and the second storage node QB is raised to high level; when working in the read state, for example, the stored data is "0", the bit line BL and reverse bit line BLB are first raised to high level through the pre-charging circuit, Then the word line is raised, the first access tube AC1 and the second access tube AC2 are turned on, and the bit line BL is discharged through the bit line BL, so that the potential of the bit line BL is lowered, and then the voltage between the bit line BLB and the bit line BL is reversed through the sense amplifier. The potential difference between them is amplified to determine that the stored data is "0" data; when the memory cell is working in the hold state, it is only necessary to pull the word line WL low, the first access tube, the third access tube Therefore, the data on the bit line BL and the inverted bit line BLB will not affect Q' and QB'.

Assuming that the data stored in the memory cell is "1" data, that is, the first storage node Q is at a high level, the second storage node QB is at a low level; the word line WL is at a low level (for a single memory cell, absolutely Most of the time is in the holding state); the high-energy particle bombardment of the MOS tube body region in the cut-off state is the worst case, so it is assumed that the high-energy particle bombards the body region of the first pull-down tube PD1: at this time, the first pull-down tube PD1 and the second pull-down tube PD1 The pull-up tube PU2 is in the off state, the second pull-down tube PD2 and the first pull-up tube PU1 are in the on-state; after the bombardment of high-energy particles, a transient large current is formed in the body region of the first pull-down tube PD1, and a part of the current It will flow to the low-point VSS terminal through the body-leading structure of the body region; another part of the current will cause the potential of the first storage node Q to decrease. At this time, on the one hand, the second storage node QB is still at low potential, and the first pull-up transistor PU1 is turned on, charging the first storage node Q through the high potential VDD to prevent its potential from decreasing; The source or drain of the MOS transistor connected to a storage node Q, because the second access transistor is off, its equivalent resistance is in the mega-ohm level, and because the first access transistor connected to the second access transistor is The cut-off, connected to the second pull-down tube is its gate, and its equivalent resistance is several orders of magnitude higher than the mega-ohm level, so this greatly prolongs its feedback time, thereby improving the anti-single event effect.

Embodiment two

As shown in FIG. 4 , the present invention provides another anti-single event effect SRAM unit, which at least includes: a first cross-coupled inverter 10, a second cross-coupled inverter 20, and a transmission Tube.

The first cross-coupled inverter 10 is composed of a first pull-up transistor and a second pull-up transistor. As an example, both the first pull-up transistor and the second pull-up transistor are PMOS transistors, which are denoted as PU1 and PU2 respectively. The dimensions of the two pull-up tubes are strictly matched to increase the stability of the storage unit.

The second cross-coupled inverter 20 is composed of a first pull-down transistor and a second pull-down transistor. As an example, both the first pull-down transistor and the second pull-down transistor are NMOS transistors, which are denoted as PD1 and PD2 respectively. The dimensions of the two pull down tubes are strictly matched to increase the stability of the storage unit.

The transmission pipe is controlled by the word line and is composed of a first access pipe, a second access pipe, a third access pipe and a fourth access pipe. As an example, the first access transistor, the second access transistor, the third access transistor and the fourth access transistor are all NMOS transistors, which are respectively denoted as AC1, AC2, AC3, and AC4.

In this embodiment, the gate of the first pull-up transistor PU1 is connected to the drain of the second pull-up transistor PU2; the source of the first pull-up transistor PU1 is connected to a high level; The drain of a pull-up transistor PU1 is connected to the gate of the second pull-up transistor PU2;

The gate of the second pull-up tube PU2 is connected to the drain of the first pull-up tube PU1; the source of the second pull-up tube PU2 is connected to a high level; The drain is connected to the gate of the first pull-up transistor PU1.

The gate of the first pull-down transistor PD1 is connected to the drain (or source) of the fourth access transistor AC4; the drain of the first pull-down transistor PD1 is connected to the first pull-up transistor The drain of PU1, the source (or drain) of the first access transistor AC1 and the source (or drain) of the second access transistor AC2 constitute the first storage node Q; the first The source of the pull-down transistor PD1 is connected to low level;

The gate of the second pull-down transistor PD2 is connected to the drain (or source) of the second access transistor AC2; the drain of the second pull-down transistor PD2 is connected to the second pull-up transistor PU2 The drain, the source (or drain) of the third access transistor AC3 and the source (or drain) of the fourth access transistor AC4 form a second storage node QB; the second pull-down transistor The source of PD2 is connected to low level.

For the transmission transistor controlled by the word line, the drain (or source) of the first access transistor AC1 is connected to the bit line of the memory cell, and the gate of the first access transistor AC1 is connected to the second access transistor AC1. The gate of AC2 is controlled by the word line; the drain (or source) of the third access transistor AC3 is connected to the reverse bit line of the memory cell, and the gate of the third access transistor AC3 is connected to the fourth access The gate of transistor AC4 is controlled by the word line.

The word line WL controls the conduction between the bit line BL and the first storage node Q by controlling the first access transistor AC1; the word line WL controls the connection between the gate of the second pull-down transistor PD2 and the first storage node Q by controlling the second access transistor AC2. The conduction of the storage node Q; the word line WL controls the conduction of the reverse bit line BLB and the second storage node QB by controlling the third access tube AC3; the word line WL controls the first lower bit line by controlling the fourth access tube AC4 The gate of the transistor PD1 is connected to the second storage node QB.

The specific working mode of the memory unit corresponding to the second embodiment is described in detail below:

The memory cell has three working states: When the memory cell is in the writing state, such as writing "0" data: first pull the bit line BL low, raise the reverse bit line BLB, and then raise the word line WL, the first The access tube AC1 is turned on, the first storage node is discharged through the first access tube; the third access tube is turned on, the fourth access tube is turned on, and the reverse bit line passes through the third access tube and the fourth access tube Raise the gate voltage of the first pull-down transistor, and then further discharge the first storage node Q through the first pull-down transistor; the reverse bit line charges the second storage node QB through the third access transistor, and the first storage node The potential of Q decreases, and QB is charged through the first pull-up tube PU1; when it is working in the read state, for example, the stored data is "0", the bit line BL and the reverse bit line BLB are first raised to high level through the pre-charging circuit , then the word line is raised, the first access transistor is turned on, and the bit line BL is discharged through the bit line BL, so that the potential of the bit line BL drops, and then the potential difference between the reverse bit line BLB and the bit line BL is amplified by the sense amplifier, so as to Judging that the stored data is "0" data; when the memory cell is working in the holding state, it is only necessary to pull the word line WL low, and the first access tube and the third access tube are cut off, so the bit lines BL, Inverted bit line BLB data will not affect Q and QB.

Assume that the data stored in the memory cell is "1" data, that is, the first storage node Q is at a high level, the second storage node QB is at a low level; the word line WL is at a low level; The body region of the pull-down tube PD1: at this time, the first pull-down tube PD1 and the second pull-up tube PU2 are in the cut-off state, and the second pull-down tube PD2 and the first pull-up tube PU1 are in the conduction state; after the bombardment of high-energy particles, the The body region of the pull-down transistor PD1 forms a transient large current, at this time, a part of the current flows to the low point VSS terminal through the body lead-out structure of the body region; the other part of the current causes the potential of the first storage node Q to drop. At this time, on the one hand, the second storage node QB is still at low potential, and the first pull-up transistor PU1 is turned on, charging the first storage node Q through the high potential VDD to prevent its potential from decreasing; The source or drain of the MOS transistor connected to a storage node Q, because the second access transistor is off, its equivalent resistance is in the mega-ohm level, and because the first access transistor connected to the second access transistor is The cut-off, connected to the second pull-down tube is its gate, and its equivalent resistance is several orders of magnitude higher than the mega-ohm level, so this greatly prolongs its feedback time, thereby improving the anti-single event effect.

It should be noted that, the first pull-up tube, the second pull-up tube, the first pull-down tube, and the second pull-down tube in the present invention all use body extraction technology to connect the body region to a fixed potential. Specifically, the body regions of the first pull-up transistor and the second pull-up transistor are connected to a high level, and the body regions of the first pull-down transistor and the second pull-down transistor are connected to a low level.

As an example, the fabrication substrate of the single event-resistant random access memory unit is a silicon-on-insulator substrate SOI.

It is worth mentioning that, for the convenience of description, the present invention only uses the single-port unit of the static random access memory for specific description. It can be obtained by slightly changing the number of tubes and the way of connection, but the spirit of the invention belongs to the original spirit of the present invention.

To sum up, the present invention provides a static random access memory unit that is resistant to single event effects, and the memory unit includes at least a first cross-coupled inverter, which is composed of a first pull-up transistor and a second pull-up transistor; The two cross-coupled inverters are composed of a first pull-down tube and a second pull-down tube; the transmission tube is composed of a first access tube, a second access tube, a third access tube and a fourth access tube. Both the pull-down transistor and the access transistor are NMOS transistors, and the pull-up transistor is a PMOS transistor. The present invention utilizes MOS tube to extend the feedback loop time to increase the stability of the unit, thereby improving the anti-single event capability of the unit; Matching, to ensure the matching of its process parameters, in order to further reduce the influence of mismatch in the circuit process, the two pull-up tubes and the two pull-down tubes adopt the body-leading structure; in addition, using SOI technology, the body-leading structure is used to manufacture The transistor can effectively suppress the floating body effect and the amplification effect of the parasitic triode, thereby improving the single event effect of the unit (it can also improve the anti-total dose effect); the SOI process adopted by the present invention is compatible with the digital logic process, and has small parasitic capacitance and low power consumption. Low power consumption, natural single-event latch-up resistance without increasing additional process costs.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (8)

1. A SRAM unit resistant to single event effect, characterized in that the memory unit at least comprises: The first cross-coupled inverter is composed of a first pull-up transistor and a second pull-up transistor; The second cross-coupled inverter is composed of a first pull-down transistor and a second pull-down transistor; The transmission pipe is composed of the first access pipe, the second access pipe, the third access pipe and the fourth access pipe, wherein: The gate of the first pull-up transistor is connected to the drain of the second pull-up transistor, the drain of the first pull-up transistor is connected to the gate of the second pull-up transistor, and the first pull-up transistor is connected to the gate of the second pull-up transistor. Both the source of the pull-up transistor and the source of the second pull-up transistor are connected to a high level; The gate of the first pull-down transistor is connected to the source of the third access transistor and the drain of the fourth access transistor, and the drain of the first pull-down transistor is connected to the drain of the first pull-up transistor , the gate of the second pull-down transistor is connected to the source of the first access transistor and the drain of the second access transistor, the drain of the second pull-down transistor is connected to the second pull-up transistor The drains are connected, and the source of the first pull-down transistor and the source of the second pull-down transistor are both connected to a low level; The source of the first access transistor is connected to the drain of the second access transistor, the drain of the first access transistor is connected to the bit line of the memory cell, and the source of the second access transistor is connected to the second access transistor. The drain of a pull-up transistor and the drain of the first pull-down transistor are connected to form a first storage node, and the gate of the first access transistor and the gate of the second access transistor are controlled by word lines; The source of the third access transistor is connected to the drain of the fourth access transistor, the drain of the third access transistor is connected to the reverse bit line of the memory cell, and the source of the fourth access transistor is connected to the drain of the fourth access transistor. The drain of the second pull-up transistor and the drain of the second pull-down transistor are connected to form a second storage node, and the gate of the third access transistor and the gate of the fourth access transistor are controlled by the word line; or: The gate of the first pull-up transistor is connected to the drain of the second pull-up transistor, the drain of the first pull-up transistor is connected to the gate of the second pull-up transistor, and the first pull-up transistor is connected to the gate of the second pull-up transistor. Both the source of the pull-up transistor and the source of the second pull-up transistor are connected to a high level; The gate of the first pull-down transistor is connected to the drain of the fourth access transistor, the drain of the first pull-down transistor is connected to the drain of the first pull-up transistor, and the source of the first access transistor electrode and the source of the second access transistor are connected to form the first storage node, the gate of the second pull-down transistor is connected to the drain of the second access transistor, and the drain of the second pull-down transistor is connected to the second upper The drain of the pull-down transistor, the source of the third access transistor, and the source of the fourth access transistor are connected to form a second storage node, and the source of the first pull-down transistor and the source of the second pull-down transistor are connected to each other. low level; The drain of the first access transistor is connected to the bit line of the memory cell, and the gate of the first access transistor and the gate of the second access transistor are both controlled by the word line; The drain of the third access transistor is connected to the reverse bit line of the memory cell, and the gate of the third access transistor and the gate of the fourth access transistor are both controlled by the word line. 2. The anti-single event effect SRAM unit according to claim 1, characterized in that: the first pull-up tube and the second pull-up tube are both PMOS tubes, and the sizes of the two tubes are strictly matched to increase Great unit stability. 3. The anti-single event effect static random access memory unit according to claim 1, characterized in that: the first pull-down transistor and the second pull-down transistor are both NMOS transistors, and the sizes of the two pipes are strictly matched to increase unit stability. 4. The anti-single event effect static random access memory unit according to claim 1, characterized in that: the first pull-up transistor, the second pull-up transistor, the first pull-down transistor and the second pull-down transistor all use bulk The extraction technique connects the body region to a fixed potential. 5. The anti-single event effect static random access memory unit according to claim 4, characterized in that: the body regions of the first pull-up transistor and the second pull-up transistor are connected to a high level, and the first pull-up transistor is connected to a high level. The body regions of the pull-down tube and the second pull-down tube are connected to low level. 6. The anti-single event effect SRAM unit according to claim 1, characterized in that: the first access tube, the second access tube, the third access tube and the fourth access tube are NMOS tube. 7 . The anti-single event effect SRAM unit according to claim 1 , characterized in that: the manufacturing substrate of the anti-single event effect SRAM unit is a silicon-on-insulator (SOI) substrate. 8. A method for improving resistance to single event effects by using the SRAM unit according to any one of claims 1-7.