CN105405886A - FinFET structure and manufacturing method thereof - Google Patents

Abstract

The present invention provides a FinFET structure and a manufacturing method thereof, comprising: a substrate structure, the bottom structure is an SOI substrate; a first fin and a second fin, the first and second fins are located at the above the substrate structure, parallel to each other; a gate stack, covering the substrate structure and part of the sidewalls of the first and second fins; a source region, located on the first fin not covered by the gate stack The covered area; the drain area, located in the area of the second fin not covered by the gate stack; the sidewall, located on both sides of the first and second fins, above the gate stack, for isolating A source region, a drain region and a gate stack; a channel region of a substrate structure, the channel region of the substrate structure is located in a region of the substrate structure close to the upper surface. The invention proposes a new device structure on the basis of the existing FinFET technology, so that the gate length of the device is not limited by the size of the footprint, and effectively solves the problem caused by the short channel effect.

Description

A kind of FinFET structure and manufacturing method thereof

technical field

The present invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a FinFET.

technical background

Moore's Law states that the number of transistors that can be accommodated on an integrated circuit doubles every 18 months, and the performance also doubles at the same time. At present, with the development of integrated circuit technology and technology, devices such as diodes, MOSFETs, and FinFETs have appeared successively, and the size of nodes has been continuously reduced. However, since 2011, silicon transistors have approached the atomic level and reached the physical limit. Due to the natural properties of this material, in addition to the short-channel effect, the quantum effect of the device also has a great impact on the performance of the device. The speed and performance of silicon transistors are hard to break through. Therefore, how to greatly improve the performance of silicon transistors without reducing the feature size has become a technical difficulty that needs to be solved urgently.

Contents of the invention

The invention provides a U-shaped FinFET structure and a manufacturing method thereof, and proposes a new device structure on the basis of the existing FinFET technology, so that the gate length of the device is not limited by the size of the footprint, and effectively solves the problem of short channel problems caused by the effect. Specifically, the structure includes:

a substrate structure, the substrate structure is an SOI substrate;

a first fin and a second fin, the first and second fins are located above the substrate structure and parallel to each other;

a gate stack, the gate stack covering the substrate structure and part of the sidewalls of the first and second fins;

a source region located in a region of the first fin not covered by the gate stack;

a drain region located in a region of the second fin not covered by the gate stack;

sidewalls, the sidewalls are located on both sides of the first and second fins, and are used to isolate the source region, the drain region and the gate stack.

Wherein, the first and second fins have the same height, thickness and width.

Wherein, the gate stack includes: an interface layer, a high-K dielectric layer, a metal gate work function adjustment layer, and polysilicon.

Wherein, the height of the gate stack is 1/2˜3/4 of the height of the first and second fins.

Correspondingly, the present invention also provides a method for manufacturing a U-shaped FinFET device, including:

a. providing a substrate structure, the substrate structure is an SOI substrate;

b. forming a first fin and a second fin on the substrate structure;

c. forming a gate stack over the substrate structure, the first fin and the second fin;

d. removing the gate stack layer above the first fin and the second fin and part of the sidewall, and the exposed part of the first and second fin forms the source and drain regions;

e. Forming sidewalls on both sides of the first fin and the second fin not covered by the gate stack.

Wherein, the gate stack includes: an interface layer, a high-K dielectric layer, a metal gate work function adjustment layer, and polysilicon.

Wherein, in step b, the method for forming the first fin and the second fin is:

b1) sequentially forming a channel material layer and a source-drain material layer on the substrate structure;

b2) Etching the channel material layer and the source-drain material layer to form a first fin and a second fin.

Wherein, the method of forming the first fin and the second fin is anisotropic etching.

Wherein, the first fin and the second fin have the same height, thickness and width.

Wherein, the distance between the first fin and the second fin is 5-50 nm.

Wherein, the gate stack includes: an interface layer, a high-K dielectric layer, a metal gate work function adjustment layer, and polysilicon.

Wherein, the height of the gate stack is 1/2˜3/4 of the height of the first and second fins.

Wherein, the method of forming the gate stack is atomic layer deposition.

Wherein, the method for removing part of the gate stack is anisotropic selective etching.

Wherein, the method of forming the source and drain regions is inclined ion implantation.

Wherein, the method of forming the source and drain regions is side scattering.

Wherein, the silicon on the surface not covered by the sidewall is used as the seed crystal for epitaxial growth to form source and drain epitaxial regions.

The present invention proposes a new U-shaped device structure on the basis of the existing FinFET technology. Compared with the prior art, this structure enables the device to have a vertical channel, so that the device has a constant footprint size. The gate length can be adjusted by changing the height of Fin to improve the short channel effect. First of all, because the device has a U-shaped vertical channel structure, the source and drain of the device are suspended above the substrate structure and are naturally separated from the substrate structure, so that the source-drain punchthrough of the device cannot occur, and thus has a lower subthreshold slope and leakage current. Secondly, because the device has a U-shaped vertical channel structure, the source and drain of the device are parallel to each other and suspended above the substrate structure, which effectively isolates the influence of the electric field at the drain end of the device on the source end, thus further improving the short channel effect of the device and making the device Has a smaller DIBL. Thirdly, because the device has a U-shaped vertical channel structure, the source and drain of the device are suspended above the substrate structure and are located in the same plane, so it is convenient to make source and drain contacts. At the same time, the present invention has an SOI structure, and the channel region located in the substrate region covered by the gate stack has excellent characteristics of an SOI device and has good gate control ability, so as to overcome the poor gate control ability of this region in bulk silicon devices shortcoming. Finally, since the channel region of the substrate structure in the present invention is heavily doped, it is completely turned on and is not controlled by the gate voltage, so the device has a higher operating current. The device structure proposed by the invention is fully compatible with the existing FinFET technology in terms of manufacturing technology, which greatly improves the performance of the device.

Description of drawings

Figures 1 to 10 schematically show cross-sectional views of each stage of forming a U-shaped FinFET device according to the method in Embodiment 1 of the present invention;

FIG. 11 schematically shows a cross-sectional view of a U-shaped FinFET device formed according to the method in Embodiment 2 of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

As shown in Figure 10, the present invention provides a FinFET structure, including: a substrate structure, the substrate structure is an SOI substrate; a first fin and a second fin, the first and second fins Located above the substrate structure and parallel to each other; gate stacks, the gate stacks cover the substrate structure and part of the sidewalls of the first and second fins; source regions, the source regions are located on the The area of the first fin not covered by the gate stack; the drain area, the drain area is located in the area of the second fin not covered by the gate stack; the side wall, the side wall is located in the The two sides of the first and second fins are used to isolate the source region, the drain region and the gate stack.

Wherein, the SOI substrate includes a top substrate 150 , a buried oxide layer 101 and a supporting substrate 100 .

Wherein, the first and second fins have the same height, thickness and width.

Wherein, the gate stack 300 includes: an interface layer, a high-K dielectric layer, a metal gate work function adjustment layer, and polysilicon.

Wherein, the height of the gate stack is 1/2˜3/4 of the height of the first and second fins.

The present invention proposes a new U-shaped device structure on the basis of the existing FinFET technology. Compared with the prior art, this structure enables the device to have a vertical channel, so that the device has a constant footprint size. The gate length can be adjusted by changing the height of Fin to improve the short channel effect. First of all, because the device has a U-shaped vertical channel structure, the source and drain of the device are suspended above the substrate structure and are naturally separated from the substrate structure, so that the source-drain punchthrough of the device cannot occur, and thus has a lower subthreshold slope and leakage current. Secondly, because the device has a U-shaped vertical channel structure, the source and drain of the device are parallel to each other and suspended above the substrate structure, which effectively isolates the influence of the electric field at the drain end of the device on the source end, thus further improving the short channel effect of the device and making the device Has a smaller DIBL. Thirdly, because the device has a U-shaped vertical channel structure, the source and drain of the device are suspended above the substrate structure and are located in the same plane, so it is convenient to make source and drain contacts. At the same time, the present invention has an SOI structure, and the channel region located in the substrate region covered by the gate stack has excellent characteristics of an SOI device and has good gate control ability, so as to overcome the poor gate control ability of this region in bulk silicon devices shortcoming. Finally, since the channel region of the substrate structure in the present invention is heavily doped, it is completely turned on and is not controlled by the gate voltage, so the device has a higher operating current. The device structure proposed by the invention is fully compatible with the existing FinFET technology in terms of manufacturing technology, which greatly improves the performance of the device.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the various figures, identical elements are indicated with similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale.

It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.

If it is to describe the situation of being directly on another layer or another area, the expression "directly on" or "on and adjacent to" will be used herein.

In the following, many specific details of the present invention are described, such as device structures, materials, dimensions, processing techniques and techniques, for a clearer understanding of the present invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art. For example, the semiconductor material of the substrate structure and fins can be selected from group IV semiconductors, such as Si or Ge, or group III-V semiconductors, such as GaAs, InP, GaN, SiC, or stacks of the above semiconductor materials.

First, Embodiment 1 of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1 , a supporting substrate 100 in the present invention is shown. The material of the supporting substrate 100 is a semiconductor material, such as silicon, germanium, gallium arsenide, etc. Preferably, in this embodiment, the material of the supporting substrate 100 used is silicon, and its thickness is 100-500 nm. Next, as shown in FIG. 2 , a buried oxide layer is formed on the supporting substrate 100 . Specifically, the buried oxide layer 101 may be formed by chemical vapor deposition or atomic layer deposition, and the thickness of the buried oxide layer is 20-50 nm. Finally, a top substrate 150 is formed above the buried oxide layer 101, that is, the effective substrate area when the device is in operation; in order to ensure the quality of the film, preferably, the top substrate 150 is formed by atomic layer deposition, Its thickness is 20-50 nm.

For the U-shaped FinFET structure in the present invention, its gate structure is divided into two parts, except for the areas covered by the gate stack on the first and second fins respectively, the top substrate between the fins The area on 150 covered by gate stack 300 is also part of the device channel. Since the thickness of the substrate structure is much larger than that of the fins, the control ability of the gate to the channel region on the substrate structure is relatively weak, which restricts the working current of the device to a certain extent. In order to improve this situation, we have improved the present invention in combination with SOI technology, using SOI substrates instead of bulk silicon substrates, so that the top layer silicon 150 in the substrate region has a very thin thickness, which can further realize the dielectric properties of components in integrated circuits. Isolation completely eliminates the parasitic latch-up effect in bulk silicon CMOS circuits; at the same time, compared with bulk silicon devices, the use of SOI substrates in the present invention can further reduce leakage current and enhance the gate control capability of devices, thereby greatly improving device performance.

Next, as shown in FIG. 4 , a channel material layer 110 and a source-drain material layer 120 are epitaxially grown on the top substrate 150 in sequence. The channel material layer 110 is the main part of the channel region of the device after subsequent processing, and can be lightly doped or not doped; the doping type depends on the type of the device. For N-type devices, the doping type of the channel material layer is P-type, and the available doping impurities are group III elements such as boron; for P-type devices, the doping type of the channel material layer is N-type, and the available doping impurities are N-type. Doping impurities are group five elements such as phosphorus and arsenic. In this embodiment, the channel region formed in the subsequent process has a doping concentration of 1e15cm ^-3 , and the doping element used is boron, which is formed by in-situ doping during epitaxy. The specific process steps are the same as The existing process is the same, and will not be repeated here.

The source-drain material layer 120 will become the main part of the source-drain region of the device after subsequent processing, and its doping concentration is equal to the required concentration of the source-drain region; the doping type depends on the type of the device. For N-type devices, the doping type of the channel material layer is N-type, and the doping impurities that can be used are group five elements such as phosphorus and arsenic; for P-type devices, the doping type of the channel material layer is P-type, which can be The doping impurities used are group III elements such as boron. In this embodiment, the source and drain regions formed in the subsequent process have a doping concentration of 1e19cm ^-3 , the doping element used is arsenic, and the doping is formed by in-situ doping during epitaxy. The specific process steps are the same as The existing process is the same, and will not be repeated here.

The structure after forming the source-drain material layer 120 is shown in FIG. 4 . The thickness of the channel material layer 110 shown in the figure is H2, which is equal to the height of the gate stack after the device is formed. The thickness of the source-drain material layer 120 is H1.

Next, the channel material layer 110 and the source-drain material layer 120 are etched through conventional processes such as projection, exposure, development, and etching to form the first fin 210 and the second fin 220. The etching The method can be dry etching or dry/wet etching. As shown in FIG. 5, the height of the first fin 210 and the second fin 220 after etching is equal to the thickness H2+H1 of the channel material layer 110 and the source-drain material layer 120, wherein the trench The thickness H2 of the channel material layer 110 is the height of the gate stack formed in the subsequent process, and the thickness H1 of the source-drain material layer 120 is the height of the source-drain region formed in the subsequent process.

Next, a gate stack 300 is formed on the top substrate 150 and the first fin 210 and the second fin 220 , which is the same as the existing FinFET process, and the gate stack 300 sequentially includes an interface layer 310 , high-K dielectric layer 320 , metal gate work function adjusting layer 330 and polysilicon 340 .

Wherein, the material of the interface layer 310 is silicon dioxide, which is used to eliminate defects and interface states on the surfaces of the first and second fins. Considering the gate control capability and other performances of the device, the thickness of the interface layer 310 is generally 0.5-1nm; the high-K dielectric layer 320 is generally a high-K dielectric, such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al ₂ O ₃ , La ₂ O ₃ , ZrO ₂ , LaAlO One or a combination thereof, the thickness of the gate dielectric layer can be 1nm-10nm, such as 3nm, 5nm or 8nm, the device structure after forming the high-K dielectric layer is shown in Figure 6; the metal gate work function adjustment layer 330 can be It is made of materials such as TiN and TaN, and its thickness ranges from 3nm to 15nm. The device structure after the metal gate work function adjustment layer 330 is formed is shown in FIG. 7 .

In order to make the gate stack 300 have good step coverage characteristics and obtain a high-quality film, the above processes for forming the gate stack are all formed by atomic layer deposition.

Next, polysilicon 340 is formed on the surface of the metal gate work function adjusting layer 330 . First, a layer of polysilicon is deposited on the surface of the device by chemical vapor deposition to cover the entire device by 10-50nm; next, the polysilicon layer is planarized, and the planarization method can be chemical Mechanical polishing (CMP), to make the polysilicon surface highly consistent, using the metal gate work function adjustment layer 330 as a stop layer for chemical mechanical polishing, so that the polysilicon in the remaining regions is flush with the metal gate work function adjustment layer 330; Next, anisotropic selective etching is used to perform directional etching on the polysilicon layer so that its surface is flush with the bottom of the source-drain material layer 120 , as shown in FIG. 8 .

Next, perform isotropic selective etching on the gate stack layer covering the first fin 210 and the second fin 220, remove its part above the polysilicon layer 340, and expose part of the fin, as Figure 9 shows. Oblique ion implantation or side scattering is performed on the exposed fins to form the source and drain regions.

Next, a spacer 230 is formed on the exposed portion of the sidewall of the fin to separate the gate stack from the source and drain regions. The sidewall 230 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide and combinations thereof, and/or other suitable materials. The side wall 230 may have a multi-layer structure. The sidewall can be formed by deposition and etching processes, and its thickness range can be 10nm-100nm, such as 30nm, 50nm or 80nm, as shown in FIG. 10 .

In Embodiment 2 of the present invention, as shown in FIG. 11 , optionally, after the sidewall 230 is formed, epitaxial growth is performed using the silicon in the area of the fin surface not covered by the sidewall 230 as a seed crystal to form the source and drain. The epitaxial region 240, namely raised-SD, is shown in FIG. 11 . In-situ doping is performed while the epitaxial growth is performed, so that the epitaxial region has the same doping concentration as the source and drain regions.

Next, as in the prior art, a silicide and a metal electrode are formed above the source-drain region and the gate, and the specific process steps will not be repeated here.

Although the example embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made to these embodiments without departing from the spirit and scope of the invention as defined by the appended claims. For other examples, those of ordinary skill in the art will readily understand that the order of process steps may be varied while remaining within the scope of the present invention.

In addition, the scope of application of the present invention is not limited to the process, mechanism, manufacture, material composition, means, method and steps of the specific embodiments described in the specification. From the disclosure of the present invention, those of ordinary skill in the art will easily understand that for the processes, mechanisms, manufacturing, material compositions, means, methods or steps that currently exist or will be developed in the future, they are implemented in accordance with the present invention Corresponding embodiments described which function substantially the same or achieve substantially the same results may be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include these processes, mechanisms, manufacture, material compositions, means, methods or steps within their protection scope.

Claims (18)

1. a U-shaped FinFET structure, comprising:

Substrat structure, described substrat structure is SOI substrate;

First fin (210) and the second fin (220), described first fin (210) and the second fin (220) are positioned at above described substrat structure, parallel to each other;

Gate stack (300), described gate stack covers the sidewall of described substrat structure and part first fin (210) and the second fin (220);

Source region (410), described source region be positioned at described first fin (210) not the region that covers by gate stack;

Drain region (420), described drain region be positioned at described second fin (220) not the region that covers by gate stack;

Side wall (230), described side wall (230) is positioned at described first fin (210) and the second fin (220) both sides, and gate stack (300) top, for isolating source region, drain region and gate stack.

2. FinFET structure according to claim 1, is characterized in that, described first fin (210) and the second fin (220) have identical height, thickness and width.

3. FinFET structure according to claim 1, is characterized in that, the distance between described first fin (210) and the second fin (220) is 5 ~ 50nm.

4. FinFET structure according to claim 1, is characterized in that, the height of described gate stack (300) is 1/2 ~ 3/4 of first, second fin described (210,220) height.

5. FinFET structure according to claim 1, it is characterized in that, described gate stack (300) comprising: boundary layer (310), high-K dielectric layer (320), metal gate work function regulating course (330) and polysilicon (340).

6. a U-shaped FinFET manufacture method, comprising:

A. provide substrat structure, described substrat structure is SOI substrate;

B. on described substrat structure, form the first fin (210) and the second fin (220);

C. gate stack is formed in described substrat structure, described first fin (210) and the second fin (220) top;

D. remove the gate stack of described first fin (210) and the second fin (220) top and partial sidewall, part first and second fin exposed forms source-drain area;

E. side wall (230) is formed at the first fin (210) do not covered by described gate stack and the second fin (220) both sides.

7. manufacture method according to claim 6, it is characterized in that, described gate stack (300) comprising: boundary layer (310), high-K dielectric layer (320), metal gate work function regulating course (330) and polysilicon (340).

8. manufacture method according to claim 6, is characterized in that, in stepb, the method forming described first fin (210) and the second fin (220) is:

B1) on described substrat structure, form layer of channel material (110) and source and drain material layer (120) successively;

B2) described layer of channel material (110) and source and drain material layer (120) are etched, form the first fin (210) and the second fin (220).

9. manufacture method according to claim 6, is characterized in that, the method forming described first fin (210) and the second fin (220) is anisotropic etching.

10. manufacture method according to claim 6, is characterized in that, described first fin (210) and the second fin (220) have identical height, thickness and width.

11. manufacture methods according to claim 6, is characterized in that, the distance between described first fin (210) and the second fin (220) is 5 ~ 50nm.

12. manufacture methods according to claim 6, it is characterized in that, described gate stack (300) comprising: boundary layer (310), high-K dielectric layer (320), metal gate work function regulating course (330) and polysilicon (340).

13. manufacture methods according to claim 6, is characterized in that, the height of described gate stack (300) is 1/2 ~ 3/4 of first, second fin described (210,220) height.

14. manufacture methods according to claim 6, is characterized in that, the method forming described gate stack is atomic layer deposition.

15. manufacture methods according to claim 6, is characterized in that, the method removing part gate stack is anisotropic selective etching.

16. manufacture methods according to claim 6, is characterized in that, the method forming described source-drain area is the ion implantation tilted.

17. manufacture methods according to claim 6, is characterized in that, the method forming described source-drain area is lateral scattering.

18. manufacture methods according to claim 6, is characterized in that, with the silicon on the surface do not covered by side wall for seed crystal carries out epitaxial growth, form source and drain epitaxial region.