CN105405890B - Semiconductor device including charged body sidewall and method of manufacturing the same - Google Patents

Abstract

A semiconductor device including charged bulk spacers and a method of manufacturing the same are disclosed. The semiconductor device may be an n-type device or a p-type device, each of which may include: a patterned first semiconductor layer and a second semiconductor layer sequentially formed on a substrate, wherein the first semiconductor layer and the second semiconductor layer are patterned as a fin structure, and the first semiconductor layer is laterally recessed relative to the second semiconductor layer; a body spacer formed in the lateral recess, the body spacer includes a dielectric material; an isolation layer formed on a substrate, the The top surface of the isolation layer is located between the top surface and the bottom surface of the first semiconductor layer, wherein the portion of the fin structure above the isolation layer serves as a fin of the semiconductor device; and a gate stack intersecting the fin is formed on the isolation layer. For an n-type device, the body spacer can have a net negative charge, making the first semiconductor layer appear p-type; while for a p-type device, the body spacer can have a net positive charge, making the first semiconductor layer appear n-type.

Description

Semiconductor device including charged bulk spacers and method of manufacturing the same

technical field

The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device including charged spacers and a manufacturing method thereof.

Background technique

As the size of planar semiconductor devices becomes smaller and smaller, the short channel effect becomes more and more obvious. For this reason, three-dimensional semiconductor devices such as FinFETs (Fin Field Effect Transistors) have been proposed. In general, a FinFET includes a fin formed vertically on a substrate and a gate intersecting the fin. Thus, a channel region is formed in the fin, and its width is mainly determined by the height of the fin. However, in the integrated circuit manufacturing process, it is difficult to control the fins formed on the wafer to have the same height, which leads to inconsistency in device performance on the wafer.

In particular, in bulk FinFETs (ie, FinFETs formed on a bulk semiconductor substrate), there may be leakage between the source and drain regions through the portion of the substrate below the fin, which may also be referred to as punch-through. Currently, it is difficult to form a high-quality punch-through prevention layer.

Contents of the invention

It is an object of the present disclosure, at least in part, to provide a semiconductor device with a novel punchthrough stop layer structure and a method of manufacturing the same.

According to one aspect of the present disclosure, there is provided an n-type semiconductor device, comprising: a patterned first semiconductor layer and a second semiconductor layer sequentially formed on a substrate, wherein the first semiconductor layer and the second semiconductor layer are patterned is a fin structure, and the first semiconductor layer is laterally recessed relative to the second semiconductor layer; the body spacer formed in the lateral recess, the body spacer includes a dielectric material; the isolation layer formed on the substrate, the The top surface of the isolation layer is located between the top surface and the bottom surface of the first semiconductor layer, wherein the portion of the fin structure above the isolation layer serves as a fin of the semiconductor device; and a gate stack intersecting the fin is formed on the isolation layer, Wherein, the body sidewall has a net negative charge, so that the first semiconductor layer presents a p-type.

According to another aspect of the present disclosure, there is provided a p-type semiconductor device, including: a patterned first semiconductor layer and a second semiconductor layer sequentially formed on a substrate, wherein the first semiconductor layer and the second semiconductor layer are The patterning is a fin-like structure, and the first semiconductor layer is laterally recessed relative to the second semiconductor layer; a body spacer formed in the lateral recess, the body spacer includes a dielectric material; an isolation layer formed on the substrate, The top surface of the isolation layer is located between the top surface and the bottom surface of the first semiconductor layer, wherein the portion of the fin structure above the isolation layer serves as a fin of the semiconductor device; and a gate stack intersecting the fin is formed on the isolation layer , wherein the body spacer has a net positive charge, so that the first semiconductor layer is n-type.

According to another aspect of the present disclosure, there is provided a method of manufacturing an n-type semiconductor device, comprising: sequentially forming a first semiconductor layer and a second semiconductor layer on a substrate; patterning the second semiconductor layer and the first semiconductor layer , to form a fin-like structure; selectively etch the first semiconductor layer in the fin-like structure to make it laterally recessed; fill the dielectric with a net negative charge in the lateral recess to form a body spacer; forming an isolation layer on the bottom, the isolation layer exposing a portion of the body sidewall, wherein the portion of the fin structure above the isolation layer serves as a fin of the semiconductor device; and forming a gate stack intersecting the fin on the isolation layer.

According to another aspect of the present disclosure, there is provided a method of manufacturing a p-type semiconductor device, comprising: sequentially forming a first semiconductor layer and a second semiconductor layer on a substrate; patterning the second semiconductor layer and the first semiconductor layer , to form a fin-like structure; selectively etch the first semiconductor layer in the fin-like structure to make it laterally recessed; fill the dielectric with a net positive charge in the lateral recess to form a body spacer; forming an isolation layer on the bottom, the isolation layer exposing a portion of the body sidewall, wherein the portion of the fin structure above the isolation layer serves as a fin of the semiconductor device; and forming a gate stack intersecting the fin on the isolation layer.

According to an embodiment of the present disclosure, the fin structure includes a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer is recessed relative to the second semiconductor layer. In this lateral recess of the first semiconductor layer, charged bulk spacers are formed. Specifically, for an n-type device, the body sidewall has a negative charge, thereby introducing holes into the first semiconductor layer, so that the first semiconductor layer presents a p-type; for a p-type device, the body sidewall has a positive charge, so that Electrons are introduced into the first semiconductor layer so that the first semiconductor layer exhibits an n-type. Therefore, the first semiconductor layer can well serve as a punch-through preventing layer of the semiconductor device. Compared with the conventional punch-through preventing layer formed by ion implantation or thermal diffusion, etc., a steeper distribution of electrons or holes in the punch-through preventing layer in the height direction of the fin can be achieved, thereby reducing random doping fluctuations.

Description of drawings

The above and other objects, features and advantages of the present disclosure will be more clearly described through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

1-10 are schematic diagrams illustrating the flow of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on" another layer/element in one orientation, the layer/element can be located "below" the other layer/element when the orientation is reversed.

According to an embodiment of the present disclosure, at least one semiconductor layer may be formed on a substrate, eg, by epitaxy. Like this, when patterning the fin structure by etching, for example, in order to form the fin structure of the same height, the depth of etching into the substrate can be reduced (or even zero, in this case, completely The fin structure is formed by the at least one semiconductor layer), so that it is easier to control the consistency of the etching depth. In addition, the thickness uniformity of the epitaxial layer can be relatively easily controlled, and as a result, the height uniformity of the fin structure finally formed can be improved.

In preferred embodiments of the underlying disclosure, said at least one semiconductor layer comprises two or more semiconductor layers. Among these semiconductor layers, adjacent semiconductor layers may have etch selectivity with respect to each other, so that each semiconductor layer may be selectively etched. After the fin structure is formed, a certain layer (or multiple layers) therein can be selectively etched to make it narrow (recessed) laterally. Dielectric can be filled in such lateral recesses to form body spacers. In addition, the isolation layer is formed such that the isolation layer exposes a portion of the body side wall. The body sidewalls are thus located at the bottom of the fins that are eventually formed (the portion of the initially formed fin structure surrounded by the isolation layer no longer acts as a true fin for channel formation).

In this way, at the bottom of the fin finally formed, due to the body sidewall, the dielectric layer between the subsequently formed gate and the fin is relatively thick, so that the parasitic capacitance formed is relatively small.

According to embodiments of the present disclosure, the body side walls may be charged. Specifically, for an n-type device, the body sidewall has a negative charge, thereby introducing holes into the first semiconductor layer, so that the first semiconductor layer presents a p-type; for a p-type device, the body sidewall has a positive charge, so that Electrons are introduced into the first semiconductor layer so that the first semiconductor layer exhibits an n-type. Therefore, the first semiconductor layer can function as a punch-through preventing layer.

The disclosure can be presented in various forms, some examples of which are described below.

As shown in Figure 1, a substrate 1002 is provided. The substrate 1002 may be various forms of substrates, such as but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, SiGe substrates, and the like. In the following description, for convenience of description, a bulk Si substrate is used as an example for description.

In the substrate 1002, an n-type well or a p-type well 1002-1 may be formed for subsequent formation of a p-type device or an n-type device respectively thereon. For example, an n-type well can be formed by implanting n-type impurities such as P or As into the substrate 1002 , and a p-type well can be formed by implanting p-type impurities such as B into the substrate 1002 . Annealing can also be performed after implantation, if desired. Those skilled in the art can think of multiple ways to form the n-type well and the p-type well, which will not be repeated here.

On the substrate 1002, for example, by epitaxial growth, a first semiconductor layer 1004 is formed. For example, the first semiconductor layer 1004 may include SiGe (Ge atomic percentage is, for example, about 5-20%) with a thickness of about 10-50 nm.

Next, a second semiconductor layer 1006 is formed on the first semiconductor layer 1004, for example, by epitaxial growth. For example, the second semiconductor layer 1006 may comprise Si and have a thickness of about 20-100 nm.

On the second semiconductor layer 1006, a protective layer 1008 may be formed. The protection layer 1008 may include, for example, oxide (eg, silicon oxide) with a thickness of about 10-50 nm. This protective layer 1008 may protect the ends of the fins during subsequent processing. In this example, protective layer 1008 has been patterned (eg, by photolithography) into a shape corresponding to the fins to be formed later.

Then, as shown in FIG. 2 , the second semiconductor layer 1006 and the first semiconductor layer 1004 are sequentially selectively etched such as reactive ion etching (RIE) using the patterned protective layer 1008 as a mask, thereby forming the fin structure F1 . It should be noted here that although the etching stops at the substrate 1002 in this embodiment, the present disclosure is not limited thereto. For example, the etching may further proceed into the substrate 1002, so that the resulting fin structure also includes a portion of the well 1002-1 at the bottom.

It should be pointed out here that the shape of the groove (between the fin structures) formed by etching is not necessarily the regular rectangular shape shown in FIG. .

Next, as shown in FIG. 3 , the first semiconductor layer 1004 (for example, SiGe) may be selectively etched relative to the protective layer 1008 (for example, silicon oxide), the substrate 1002 and the second semiconductor layer 1006 (for example, Si). , making the first semiconductor layer 1004 concave laterally. Therefore, the portion of the fin structure made of the first semiconductor layer is narrowed. The width of the lateral depression (dimension in the horizontal direction in the figure) may be about 3-10 nm.

Then, as shown in FIG. 4 , a dielectric is filled in the lateral recess to form a body spacer 1010 . Such filling can be accomplished, for example, by depositing a dielectric followed by etch back (eg, RIE) to selectively remove portions of the deposited dielectric that lie outside the lateral recess. The body spacer 1010 may include nitride (eg, silicon nitride) or a low-K dielectric such as SiOF, SiCOH, SiO, SiCO, SiCON, or a high-K dielectric, among others. In examples where the deposited dielectric includes nitride, a thin layer of oxide (not shown) may optionally be deposited as a pad layer prior to depositing the dielectric to relieve nitride stress.

According to an embodiment of the present disclosure, the body spacer 1010 may be charged so as to introduce holes or electrons into the first semiconductor layer 1002 . Specifically, the charged body spacer 1010 can change the electric potential field in the corresponding part (ie, the first semiconductor layer 1002 ) in the fin structure, and this electric potential field can pull in the thermally generated electrons or holes. Or pulled out of it, causing electrons or holes to accumulate in that part of the fin structure.

The charge in the body spacer may be achieved by charge contained in at least a portion of the dielectric forming the body spacer. For example, in the case where the body spacer is an oxide/nitride stack, either the nitride, or the oxide, or both the nitride and oxide may contain charges. For example, surface plasma treatment (eg, confined to the surface, such as within about 1-2 nm from the surface) can be performed to introduce charge into the dielectric. Specifically, the plasma bombards the surface of the dielectric layer to create defect states therein, which can be negatively or positively charged.

Specifically, for a p-type device to be formed on the n-type well 1002-1, the first semiconductor layer 1004 should be n-type as a whole; or, for an n-type device to be formed on the p-type well 1001-1, the second A semiconductor layer 1004 should be p-type as a whole. In this way, the first semiconductor layer 1004 can then act as a punch-through stop layer.

For this reason, the body spacer 1010 for a p-type device can carry a relatively high net positive charge (for example, a density of about 1×10 ¹⁷ ~1×10 ²¹ cm ⁻³ ), so that it can be introduced into the first semiconductor layer 1004 Relatively high electron concentration (eg, a density of about 1×10 ¹⁷ to 5×10 ¹⁸ cm ⁻³ ). Alternatively, the body spacer 1010 for an n-type device may have a relatively high net negative charge (for example, a density of about 1×10 ¹⁷ ~1×10 ²¹ cm ⁻³ ), so that a relative High hole concentration (eg, a density of about 1×10 ¹⁷ to 5×10 ¹⁸ cm ⁻³ ).

After forming the fin structure with charged body sidewalls through the above process, a gate stack intersecting the fin can be formed and a final semiconductor device (eg, FinFET) can be formed.

In order to isolate the gate stack and the substrate, an isolation layer 1012 is first formed on the substrate, as shown in FIG. 5 . Such isolation layers can be formed, for example, by depositing a dielectric material on the substrate and then etching back. During the etch-back process, the etch-back depth is controlled so that part of the body sidewall can be exposed (protruding relative to the top surface of the isolation layer) of the isolation layer after etching back. In this way, the isolation layer 1012 defines the fins F above it. The portion of the fin structure F1 below the fin F is surrounded by the isolation layer 1012 and thus does not act as a true fin for forming the channel region in the final device.

In one example, protective layer 1008 and dielectric material 1012 include the same material, such as an oxide. Therefore, during the process of etching back the dielectric material 1012, the protection layer 1008 may be removed at the same time, as shown in FIG. 5 .

Subsequently, gate stacks intersecting the fins may be formed on the isolation layer 1012 . For example, this can be done as follows. Specifically, as shown in FIG. 6 (FIG. 6(b) shows a cross-sectional view along line AA' in FIG. 6(a)), for example, a sacrificial gate dielectric layer 1014 is formed by deposition. For example, the sacrificial gate dielectric layer 1014 may include oxide with a thickness of about 0.8-1.5 nm. In the example shown in FIG. 6 , only the “Π”-shaped sacrificial gate dielectric layer 1014 is shown. However, the sacrificial gate dielectric layer 1014 may also include a portion extending on the top surface of the isolation layer 1012 . A sacrificial gate conductor layer 1016 is then formed, eg, by deposition. For example, the sacrificial gate conductor layer 1016 may include polysilicon. The sacrificial gate conductor layer 1016 may completely cover the fins and may be planarized such as chemical mechanical polishing (CMP). Afterwards, the sacrificial gate conductor layer 1016 is patterned to form a gate stack. In the example of FIG. 6, the sacrificial gate conductor layer 1016 is patterned into stripes intersecting the fins. In addition, the patterned sacrificial gate conductor layer 1016 can also be used as a mask to further pattern the gate dielectric layer 1014 .

As shown by the elliptical dotted circle in FIG. 6(b), at the lower part of the fin F, there is a body spacer 1010 between the subsequently formed gate conductor and the fin (in this example, the first semiconductor layer), resulting in parasitic Capacitance is relatively small.

After the patterned gate conductor is formed, for example, the gate conductor can be used as a mask to perform halo implantation and extension implantation.

Next, as shown in FIG. 7 ( FIG. 7( b ) shows a cross-sectional view along line BB′ in FIG. 7( a )), spacers 1018 may be formed on the sidewalls of the sacrificial gate conductor layer 1016 . For example, the spacer 1018 can be formed by depositing a nitride with a thickness of about 5-30 nm, and then performing RIE on the nitride. Those skilled in the art know many ways to form such sidewalls, which will not be repeated here.

When the trenches between the fins are in the shape of a frustum tapering from top to bottom (which is usually the case due to the nature of etching), the sidewalls 1018 are substantially not formed on the sidewalls of the fins.

After the spacer is formed, the gate conductor and the sidewall can be used as a mask to perform source/drain (S/D) implantation. Subsequently, the implanted ions may be activated by annealing to form source/drain regions.

Next, as shown in FIG. 8 , a dielectric layer 1020 is formed, for example, by deposition. The dielectric layer 1020 may include oxide, for example. Subsequently, a planarization process such as CMP is performed on the dielectric layer 1020 . The CMP may stop at spacer 1018 , exposing sacrificial gate conductor 1016 .

Subsequently, as shown in FIG. 9 , for example, the sacrificial gate conductor 1016 is selectively removed by using TMAH solution, and the sacrificial gate dielectric layer 1014 may be further removed, thereby forming a void inside the sidewall 1018 .

Then, as shown in FIG. 10 (FIG. 10(b) shows a cross-sectional view along the BB' line in FIG. 10(a), by forming a gate dielectric layer 1022 and a gate conductor layer 1024 in the gap, the final gate is formed. stack. The gate dielectric layer 1022 may include a high-K gate dielectric such as HfO ₂ , with a thickness of about 1-5 nm. The gate conductor layer 1024 may include a metal gate conductor. Preferably, a work function adjusting layer (not shown) may also be formed between the gate dielectric layer 1022 and the gate conductor layer 1024 .

In this way, the semiconductor device according to this embodiment is obtained. As shown in FIG. 10, the semiconductor device may include: a patterned first semiconductor layer 1004 and a second semiconductor layer 1006 sequentially formed on a substrate 1002, wherein the first semiconductor layer 1004 and the second semiconductor layer 1006 are patterned as Fin structure, and the first semiconductor layer 1004 is laterally recessed relative to the second semiconductor layer 1006; the charged body spacer 1010 formed in the lateral recess; the isolation layer 1012 formed on the substrate 1002, the isolation layer 1012 The top surface of the first semiconductor layer 1004 is located between the top surface and the bottom surface, wherein the part of the fin structure above the isolation layer 1012 (top surface) serves as the fin of the semiconductor device; and the fin intersecting formed on the isolation layer gate stack.

As mentioned above, for a p-type device, the first semiconductor layer 1004 can exhibit an n-type; and for an n-type device, the first semiconductor layer 1004 can exhibit a p-type. Such a first semiconductor layer can act as a punch-through barrier. Furthermore, such a first semiconductor layer can reduce B diffusion so that a clean junction can be formed between the channel region and the substrate body.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be advantageously used in combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (10)

1. An n-type semiconductor device, comprising: A patterned first semiconductor layer and a second semiconductor layer sequentially formed on a substrate, wherein the first semiconductor layer and the second semiconductor layer are patterned into a fin structure, and the first semiconductor layer is laterally recessed relative to the second semiconductor layer enter; a body side wall formed in said lateral recess, the body side wall comprising a dielectric material; an isolation layer formed on the substrate, the top surface of the isolation layer being located between the top surface and the bottom surface of the first semiconductor layer, wherein the portion of the fin structure above the isolation layer serves as a fin of the semiconductor device; and gate stack intersecting the fin formed on the isolation layer, Wherein, the body sidewall has a net negative charge, so that the first semiconductor layer presents a p-type. 2. The n-type semiconductor device according to claim 1, wherein the density of negative charges in the body sidewall is 1×10 ¹⁷ to 1×10 ²¹ cm ⁻³ , and the density of holes in the first semiconductor layer is 1×10 17 cm −3 . 10 ¹⁷ ~5×10 ¹⁸ cm ^-3 . 3. A p-type semiconductor device, comprising: A patterned first semiconductor layer and a second semiconductor layer sequentially formed on a substrate, wherein the first semiconductor layer and the second semiconductor layer are patterned into a fin structure, and the first semiconductor layer is laterally recessed relative to the second semiconductor layer enter; a body side wall formed in said lateral recess, the body side wall comprising a dielectric material; an isolation layer formed on the substrate, the top surface of the isolation layer being located between the top surface and the bottom surface of the first semiconductor layer, wherein the portion of the fin structure above the isolation layer serves as a fin of the semiconductor device; and gate stack intersecting the fin formed on the isolation layer, Wherein, the body sidewalls carry net positive charges, so that the first semiconductor layer presents an n-type. 4. The p-type semiconductor device according to claim 3, wherein the density of positive charges in the body sidewall is 1×10 ¹⁷ to 1×10 ²¹ cm ⁻³ , and the concentration of electrons in the first semiconductor layer is 1×10 ¹⁷ to 5×10 ¹⁸ cm ^-3 . 5. The semiconductor device according to any one of claims 1 to 4, wherein the substrate comprises bulk Si, the first semiconductor layer comprises SiGe, and the second semiconductor layer comprises Si. 6. The semiconductor device of claim 5, wherein the body spacer comprises a stack of oxide and nitride. 7. A method of manufacturing an n-type semiconductor device, comprising: sequentially forming a first semiconductor layer and a second semiconductor layer on the substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin structure; selectively etching the first semiconductor layer in the fin structure to make it laterally recessed; filling the lateral recesses with a net negatively charged dielectric to form body spacers; forming an isolation layer on the substrate, the isolation layer exposing a portion of the body spacer, wherein the portion of the fin structure above the isolation layer serves as a fin of the semiconductor device; and A gate stack intersecting the fin is formed on the isolation layer. 8. A method of manufacturing a p-type semiconductor device, comprising: sequentially forming a first semiconductor layer and a second semiconductor layer on the substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin structure; selectively etching the first semiconductor layer in the fin structure to make it laterally recessed; filling the lateral recesses with a net positively charged dielectric to form body spacers; forming an isolation layer on the substrate, the isolation layer exposing a portion of the body spacer, wherein the portion of the fin structure above the isolation layer serves as a fin of the semiconductor device; and A gate stack intersecting the fin is formed on the isolation layer. 9. A method according to claim 7 or 8, wherein the substrate comprises bulk Si, the first semiconductor layer comprises SiGe and the second semiconductor layer comprises Si. 10. The method of claim 7 or 8, wherein forming the body side wall comprises: sequentially forming an oxide layer and a nitride layer on the substrate; and Portions of the oxide layer and nitride layer outside the lateral recesses are selectively removed.