CN105489499B - LTPS method for fabricating thin film transistor - Google Patents

Abstract

The invention provides a method for manufacturing an LTPS thin film transistor, comprising: providing a substrate, forming a buffer layer and a polysilicon layer on the substrate, forming a first photoresist layer by patterning on the middle region of the polysilicon layer, and forming a first photoresist layer on the polysilicon layer. Implanting first ions into the first doped region of the layer; patterning the first photoresist layer through an ashing process, reducing the overall area of the first photoresist layer to form a second photoresist layer; wherein, the The second photoresist layer covers part of the middle region, so that a second doped region is formed between the middle region and the two first doped regions; implanting the second doped region into the two second doped regions Ions; forming a first insulating layer on the polysilicon layer and the exposed buffer layer; forming a gate on the first insulating layer; forming a second insulating layer on the gate; forming a second insulating layer on the second insulating layer A source and a drain connected to the first doped region are formed on the top. The overall process uses five photomasks to simplify the process steps.

Description

LTPS Thin Film Transistor Manufacturing Method

technical field

The invention relates to the field of manufacturing thin film transistors, in particular to a method for manufacturing LTPS thin film transistors.

Background technique

Low temperature polysilicon (LTPS) thin film transistor liquid crystal display is different from the traditional amorphous silicon thin film transistor liquid crystal display, its electron mobility can reach more than 200cm2/V-sec, which can effectively reduce the size of thin film transistor devices area, so as to increase the aperture ratio, and reduce the overall power consumption while increasing the brightness of the display. In addition, the higher electron mobility can integrate part of the driving circuit on the glass substrate, reducing the number of driving ICs, and can also greatly improve the reliability of the liquid crystal display panel, thereby greatly reducing the manufacturing cost of the panel. Therefore, the LTPS thin film transistor liquid crystal display has gradually become a research hotspot.

However, due to the fact that the semiconductor region is getting shorter and shorter in the manufacture of LTPS thin film transistors, the short channel effect is becoming more and more obvious. The short channel effect causes abnormalities in NTFT characteristics, such as large Vth, high off current, etc. In order to avoid such abnormalities, a lightly doped region N- (LDD) is added or removed between N+ and the channel in general NTFT fabrication.

In the entire manufacturing process of traditional LTPS thin film transistors, it is necessary to use photoresist to pass through two masks when implanting N+ and N- ions. However, the entire manufacturing process of LTPS thin film transistors requires a total of six masks, which increases the manufacturing cost.

Contents of the invention

The invention provides a method for manufacturing an LTPS thin film transistor, which can simplify the manufacturing process and reduce the cost.

The manufacturing method of the LTPS thin film transistor of the present invention includes providing a substrate, and forming a buffer layer on the substrate;

patterning and forming a polysilicon layer on the buffer layer;

A first photoresist layer is formed by patterning on the middle region of the polysilicon layer, and the polysilicon layer is divided into a middle region and first doped regions located on opposite sides of the middle region; wherein the cross section of the first photoresist layer is an isosceles trapezoid, and its surface in contact with the middle region is the bottom surface of the trapezoid;

implanting first ions into the two first doped regions;

The first photoresist layer is patterned by an ashing process, so that the overall area of the first photoresist layer is reduced to form a second photoresist layer; wherein, the second photoresist layer covers part of the middle region , forming a second doped region between the middle region and the two first doped regions;

implanting second ions into the two second doped regions;

forming a first insulating layer on the polysilicon layer and the exposed buffer layer;

forming a first metal layer on the first insulating layer and patterning the first metal layer to form a gate,

forming a second insulating layer on the first insulating layer formed and exposed on the gate;

forming via holes on the first insulating layer and the second insulating layer by patterning; the via holes are opposite to the two first doped regions,

A source and a drain are formed on the second insulating layer by patterning, wherein the source and the drain are connected to the first doped region through the via hole.

Wherein, the step of "patterning and forming a polysilicon layer on the buffer layer" includes depositing an amorphous silicon layer on the buffer layer, crystallizing the amorphous silicon layer by laser crystallization to form a polysilicon layer, and forming a polysilicon layer on the polysilicon layer Patterning steps.

Wherein, in the step of "patterning the first photoresist layer by an ashing process to reduce the overall area of the first photoresist layer to form a second photoresist layer," the first photoresist layer The reduction of the overall area of the resist layer means that the periphery and top of the first photoresist layer are partly removed by photomask and etching to form a second photoresist layer with a smaller volume.

Wherein, the step of "forming via holes on the first insulating layer and the second insulating layer by patterning" includes,

forming a patterned photoresist layer on the second insulating layer through a photomask to form a via hole;

The photoresist layer is removed by etching and the first and second insulating layers corresponding to the via hole are etched to form the via hole; the position corresponding to the via hole is the first doped region.

Wherein, the first ion and the second ion are N-type ions, and the concentration of the first ion is greater than the concentration of the second ion.

Wherein, the N-type ions are phosphorus ions.

Wherein, the material of the buffer layer is selected from one of silicon oxide layer, silicon nitride layer, silicon oxynitride layer and combinations thereof.

Wherein, the material of the first metal layer is selected from one of copper, tungsten, chromium, aluminum and combinations thereof.

Wherein, the step "forming the source electrode and the drain electrode on the second insulating layer by patterning" includes forming a metal layer on the second insulating layer, wherein the metal layer fills the via hole, and patterning the via by setting a photoresist layer The metal layer forms the source and drain corresponding to the via holes.

The thin film transistor manufacturing method of the present invention is to reduce the volume of the first photoresist layer defining the first doped region through an ashing process and reuse it to define the second doped region, and remove the first photoresist layer less once The process of laying the second photoresist layer saves a photomask, simplifies the processing steps of the thin film transistor, and reduces the manufacturing cost of the thin film transistor.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a flowchart of a manufacturing method of an LTPS thin film transistor according to a preferred embodiment of the present invention.

2 to 8 are cross-sectional views of thin film transistors in various manufacturing processes of the LTPS thin film transistor according to the preferred embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Please refer to Fig. 1, shown in the figure is the flow chart of the LTPS thin film transistor manufacturing method of the preferred embodiment of the present invention, the LTPS thin film transistor manufacturing method of the present invention comprises the following steps,

Please refer to FIG. 2 , in step S1 , a substrate 10 is provided, and a buffer layer 11 is formed on the substrate by deposition. In this embodiment, the substrate 10 is a glass layer.

In this embodiment, the material of the buffer layer 11 is selected from one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and combinations thereof.

Please refer to FIG. 3, step S2, patterning and forming a polysilicon layer 12 on the buffer layer 11, the polysilicon layer 12 constitutes the active layer of the LTPS thin film transistor of the present invention, specifically through the first photomask pair The polysilicon layer 12 is etched and developed to form the active layer of the LTPS thin film transistor.

This step specifically includes depositing an amorphous silicon layer on the buffer layer 11, crystallizing the amorphous silicon layer by laser crystallization, patterning the crystallized amorphous silicon layer, and finally forming the The polysilicon layer 12 mentioned above. Wherein, the patterned crystallized amorphous silicon layer refers to processing methods such as photomask, etching and development; and the photomask is the first photomask used in this method. The photomask technology is a commonly used technology in the field, and will not be described again.

Please refer to FIG. 4, step S3, forming a first photoresist layer 13 by patterning on the middle region of the polysilicon layer 12, thereby dividing the polysilicon layer 12 into a middle region 121 and the first doped layers on opposite sides of the middle region 121. Miscellaneous area 122. In this embodiment, the cross-section of the first photoresist layer 13 is an isosceles trapezoid, and the surface contacting the middle region 121 is the bottom surface of the trapezoid. The first photoresist layer 13 is formed of a photoresist material. Specifically, the photoresist formed on the polysilicon layer 12 is processed into the first photoresist layer 13 by means of photomask and etching. Wherein the photomask is the second photomask used in the method.

Please refer to FIG. 5 , step S4 , implanting first ions in the two first doped regions 122 . In this embodiment, the first ions are N-type ions. In this embodiment, the N-type ions are phosphorus ions.

Please refer to FIG. 6, step S5, patterning the first photoresist layer 13 through an ashing process, so that the overall area of the first photoresist layer 13 is reduced to form a second photoresist layer 14; wherein, the The second photoresist layer 14 covers part of the middle region 121 , so that a second doped region 123 is formed between the middle region 121 and the two first doped regions 122 .

Specifically, the reduction in the overall area of the first photoresist layer 13 means that the periphery and top of the first photoresist layer are partly removed through photomask and etching, so as to form a second photoresist layer with a smaller volume. That is to say, the parts of the first photoresist layer 13 where the leaks are outside are all removed, and the whole decreases toward the center of the first photoresist layer. The etching method in the ashing process adopts dry etching. The ashing process is a commonly used technique in the art, and will not be described again.

Please refer to FIG. 7 , step S6 , implanting second ions in the two second doped regions 123 . In this embodiment, the first ions are N-type ions. The concentration of the first ion is greater than the concentration of the second ion.

Both the first photoresist layer and the second photoresist layer mentioned above are removed after ion implantation.

Referring to FIG. 8 , in step S7 , a first insulating layer 15 is formed on the polysilicon layer 12 and the exposed buffer layer 11 .

Step S8 , forming a first metal layer on the first insulating layer 15 and patterning the first metal layer to form the gate 16 . A second insulating layer 17 is formed on the first insulating layer 15 formed on the gate 16 and exposed. The patterning of the first metal layer in this step refers to processing methods such as photomask, etching and development; and the photomask is the third photomask used in this method. In this embodiment, the first insulating layer 15 and the second insulating layer 17 are made of one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiNxOy).

Step S9 , forming via holes on the first insulating layer 15 and the second insulating layer 17 by patterning; the via holes are opposite to the two first doped regions 122 . Specifically, S901 forms a patterned photoresist layer on the second insulating layer through a photomask to form via holes;

S902, removing the photoresist layer by etching and etching the first and second insulating layers corresponding to the via holes to form the via holes; the positions corresponding to the via holes are the first doped regions.

The patterning of the first insulating layer 15 and the second insulating layer 17 in this step means that the via holes are formed by processing methods such as photomask, etching and development; and the photomask is the fourth photomask used in this method .

Step S10 , forming a source 18 and a drain 19 on the second insulating layer 17 by patterning, wherein the source 18 and the drain 19 are connected to the first doped region 122 through the via hole. Patterning in this step refers to processing methods such as photomask etching and development. The photomask is the fifth photomask used in the method. This step includes forming a metal layer on the second insulating layer 17, wherein the metal layer fills the via hole, and patterning the metal layer by setting a photoresist layer to form the source electrode 18 and the drain electrode 19 corresponding to the via hole.

The thin film transistor manufacturing method of the present invention is to reduce the volume of the first photoresist layer defining the first doped region 122 through an ashing process and reuse it to define the second doped region, and remove the first photoresist layer less once. The process of laying the second photoresist layer saves one photomask, and the overall process uses five photomasks. The way of the region saves the number of times of photomask, simplifies the processing steps of the thin film transistor, and reduces the manufacturing cost of the thin film transistor.

The display device formed by the manufacturing method of the thin film transistor according to the embodiment of the present invention may be a liquid crystal panel, a liquid crystal TV, a liquid crystal display, an OLED panel, an OLED TV, electronic paper, a digital photo frame, a mobile phone, and the like.

What is disclosed above is only a preferred embodiment of the present invention, and of course it cannot limit the scope of rights of the present invention. Those of ordinary skill in the art can understand all or part of the process for realizing the above embodiments, and according to the rights of the present invention The equivalent changes required still belong to the scope covered by the invention.

Claims (9)

1. a kind of LTPS method for fabricating thin film transistor, which is characterized in that the method includes providing a substrate, and described Buffer layer is formed on substrate；

Patterning forms polysilicon layer on the buffer layer；

The first photoresist layer is formed by patterning on the middle position of the polysilicon layer, the first photoresist layer divides polysilicon layer At intermediate region and positioned at the first doped region of intermediate region opposite sides；The section of first photoresist layer is isosceles trapezoid, The surface that first photoresist layer is contacted with the intermediate region is trapezoidal bottom surface；

The first ion is injected in two first doped regions；

First photoresist layer is patterned by cineration technics, the first photoresist layer entire area is made to reduce to form Two photoresist layers；Wherein, intermediate region described in the second photoresist layer covering part, makes the intermediate region and two described first The second doped region is constituted between doped region；

The second ion is injected in two second doped regions；

The first insulating layer is formed on the polysilicon layer and exposed buffer layer；

The first metal layer is formed on the first insulating layer and patterned first metal layer forms grid；And on the grid Second insulating layer is formed on formation and the first exposed insulating layer；

Via hole is formed by being patterned in first insulating layer and second insulating layer；The via hole is mixed with two described first Miscellaneous area is opposite；

Pass through patterning and form source electrode and drain electrode on the second insulating layer, wherein source electrode and drain electrode by the via hole with The first doped region connection.

2. LTPS method for fabricating thin film transistor as described in claim 1, which is characterized in that described " on the buffer layer Patterning forms polysilicon layer " the step of include deposition of amorphous silicon layers on the buffer layer, radium-shine crystallisation is passed through to amorphous silicon layer Realize the crystallization to amorphous silicon layer, and the step of to the amorphous silicon layer pattern of crystallization.

3. LTPS method for fabricating thin film transistor as claimed in claim 2, which is characterized in that described " to pass through cineration technics pair First photoresist layer is patterned, and the first photoresist layer entire area is made to reduce to form the second photoresist layer, " the step of In, the first photoresist layer entire area reduction refers to around the first photoresist layer and top passes through light shield and etching is removed A part, and form the second photoresist layer of small volume.

4. LTPS method for fabricating thin film transistor as described in claim 1, which is characterized in that described " by being patterned in State and form via hole in the first insulating layer and second insulating layer " the step of include,

It forms patterned photoresist layer on the second insulating layer by light shield and formed hole location；

The photoresist layer is removed by etching and the first, second insulating layer corresponding to the hole location excessively is etched to form institute State via hole；The via hole corresponding position is first doped region.

5. LTPS method for fabricating thin film transistor as described in claim 1, which is characterized in that first ion and second from Son is N-type ion, and the concentration of first ion is greater than the concentration of the second ion.

6. LTPS method for fabricating thin film transistor as claimed in claim 5, which is characterized in that the N-type ion is phosphonium ion.

7. LTPS method for fabricating thin film transistor as described in claim 1, which is characterized in that the material of the buffer layer is selected from Silicon oxide layer, silicon nitride layer, one of silicon oxynitride layer and combinations thereof.

8. LTPS method for fabricating thin film transistor as described in claim 1, which is characterized in that the material of the first metal layer Selected from one of copper, tungsten, chromium, aluminium and combinations thereof.

9. LTPS method for fabricating thin film transistor as described in claim 1, which is characterized in that step is " by being patterned in State and form source electrode and drain electrode in second insulating layer " it include forming metal layer over the second dielectric, wherein metal layer fills up described Via hole forms the source electrode corresponding with via hole and drain electrode by setting photoresist layer patterned metal layer.