CN105489500A - Preparation method for super-junction VDMOS and super-junction VDMOS device - Google Patents

Abstract

The invention discloses a method for preparing a super junction VDMOS. A first N- epitaxial layer is grown on an N+ substrate, and a p-type impurity is implanted with boron through a photolithography plate to form a p-type region, and the second N- epitaxial layer is continuously grown. In the epitaxial layer, boron is implanted on the second N-epitaxy layer through a photolithography plate to form a body and a well is pushed; then, on the second N-epitaxial layer, a trench area is defined by photolithography and deep trench etching and Backfill the P-type single crystal silicon to form the P-pillar region of the super junction VDMOS device; then conduct the thermal growth of gate oxide and the deposition of N+ type polysilicon; Impurities in the N+ epitaxial layer, and annealed to form the N+ source region; then deposit the interlayer dielectric, and etch the electrode contact; sputter metal Al, and form the final device structure after photolithography; also discloses a super junction VDMOS The device can effectively increase the breakdown voltage and improve the reliability of the device under the condition of maintaining the depth-width and depth-width ratio of the trench through the present invention.

Description

Preparation method of super junction VDMOS and super junction VDMOS device

technical field

The invention belongs to the technical field of preparation of super-junction VDMOS, and in particular relates to a preparation method of super-junction VDMOS and a super-junction VDMOS device thereof.

Background technique

At present, there are two mainstream high-voltage super-junction preparation processes, one is the multiple injection and epitaxy technology represented by Infineon and ST bits. The other is the trench etching and backfilling technology represented by Toshiba and Huahong. Compared with the two technologies, the multiple implantation and epitaxy technology is more mature but expensive, the trench etching and backfilling technology is relatively simple, and the cost is relatively cheap. The technical path for trench etching and backfilling to form a super junction Generally speaking, the breakdown voltage depends on the depth of the trench to a large extent. The greater the depth, the higher the breakdown voltage. However, if the aspect ratio of the trench is too large, the process of backfilling the P-type single crystal silicon will It is a challenge that it is easy to form voids and affect the reliability of the device.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a method for preparing a super-junction VDMOS and a super-junction VDMOS device thereof.

In order to achieve the above object, technical solution of the present invention is achieved in that way:

An embodiment of the present invention provides a method for preparing a super-junction VDMOS. The method is as follows: growing a first N- epitaxial layer on an N+ substrate, performing boron implantation of p-type impurities through a photolithography plate to form a p-type region, and continuing the epitaxy grow the second N-epitaxial layer, implant boron on the second N-epitaxial layer through the photolithography plate, form the body and push the well; Etch trenches and backfill P-type monocrystalline silicon to form the P-pillar region of super-junction VDMOS devices; then perform thermal growth of gate oxide and deposition of N+-type polysilicon; after polysilicon photolithography, use photolithography to define N+ implantation region and implant N+ epitaxial layer impurities, and anneal to form N+ source region; then deposit the interlayer dielectric, and etch the electrode contact; sputter metal Al, and form the final device structure after photolithography.

In the above solution, the deep trench formed by deep trench etching is aligned with the p-type region located in the first N- epitaxial layer.

In the above solution, the first N- epitaxial layer with a thickness of 10-20 um is grown on the N+ substrate.

In the above solution, the N+ epitaxial layer impurity is As or P.

The embodiment of the present invention also provides a super-junction VDMOS device, which includes a superimposed N+ substrate, a first N- epitaxial layer, and a second N- epitaxial layer, and a P-type epitaxial layer is arranged in the first N- epitaxial layer. region, the second N-epitaxial layer is provided with a P-pillar region, and the P-pillar region is aligned with the P-type region.

In the above solution, the distance between the P-pillar region and the P-type region is 3um to 20um.

Compared with prior art, the beneficial effect of the present invention:

In the present invention, an embedded p-type region is aligned with the p-pillar region of the deep trench, and there is a certain distance between the p-type region and the p-pillar region. Effectively improve the breakdown voltage and avoid possible voids caused by p-type Si backfilling due to too deep trenches, thereby improving the reliability of the device.

Description of drawings

Fig. 1 is the schematic diagram of step 1 of the present invention;

Fig. 2 is the schematic diagram of step 2 of the present invention;

Fig. 3 is a schematic diagram of forming a body in Step 3 of the present invention;

Fig. 4 is the schematic diagram that step 4 of the present invention forms p-pillar;

Fig. 5 is the schematic diagram of step five of the present invention;

Fig. 6 is the schematic diagram of step 6 of the present invention;

Fig. 7 is a schematic diagram of step seven of the present invention;

Fig. 8 is a schematic diagram of step eight of the present invention;

9 is a schematic diagram of a conventional trench superjunction;

Fig. 10 is a comparison diagram of the breakdown voltage of the simulation of the traditional trench superjunction structure combined with the superjunction structure of the present invention;

Fig. 11 is an electric field distribution diagram of the simulated electric field extending x=0 of the conventional trench superjunction combined with the superjunction structure of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

An embodiment of the present invention provides a method for preparing a super-junction VDMOS. The method is as follows: growing a first N- epitaxial layer on an N+ substrate, performing boron implantation of p-type impurities through a photolithography plate to form a p-type region, and continuing the epitaxy grow the second N-epitaxial layer, implant boron on the second N-epitaxial layer through the photolithography plate, form the body and push the well; Etch trenches and backfill P-type monocrystalline silicon to form the P-pillar region of super-junction VDMOS devices; then perform thermal growth of gate oxide and deposition of N+-type polysilicon; after polysilicon photolithography, use photolithography to define N+ implantation region and implant N+ epitaxial layer impurities, and anneal to form N+ source region; then deposit the interlayer dielectric, and etch the electrode contact; sputter metal Al, and form the final device structure after photolithography.

The step is to etch the deep trench and backfill the P-type single crystal silicon to form the P-pillar region of the super junction VDMOS device and align it with the p-type region located in the first N- epitaxial layer.

The first N- epitaxial layer with a thickness of 10-20um is grown on the N+ substrate.

An embodiment of the present invention also provides a super-junction VDMOS device, as shown in FIG. A P-type region is arranged in the layer, a P-pillar region is arranged in the second N-epitaxial layer, and the P-pillar region is aligned with the P-type region.

The distance between the P-pillar region and the P-type region is 3um to 20um.

Example:

An embodiment of the present invention provides a method for preparing a super-junction VDMOS, which is implemented through the following steps:

Step 1: As shown in FIG. 1 , epitaxially grow the first N- epitaxial layer with a thickness of 10-20um on the N+ substrate, and implant boron through a photolithography plate to form a p-type region.

Step 2: Continue to grow the second N- epitaxial layer on the first epitaxial layer, as shown in FIG. 2 .

Step 3: Thermally grow a 400A oxide layer on the second N- epitaxial layer, inject p-type impurities through the photolithography plate, and push wells to form a body, as shown in Figure 3 .

Step 4: Next, use a photolithography plate to etch the deep trench and backfill the p-type single crystal silicon, and use CMP technology to remove the p-type Si outside the trench to form a p-pillar, as shown in Figure 4.

Step 5: Next, conduct thermal growth of a certain thickness of gate oxide and perform N-type doped poly deposition, and form a gate by poly dry etching of a photolithography plate, as shown in FIG. 5 .

Step 6: Then implant N-type impurities (As or P) through the photolithography plate and push wells to form N+ source regions, as shown in FIG. 6 .

Step 7: Next, deposit and grow a SiO ₂ layer with a certain thickness (ie, ILD) and conduct hole photolithography to form a contact, as shown in FIG. 7 .

Step 8: Finally, sputtering and photolithography of metal Al to form the final structure of the device, as shown in FIG. 8 .

As shown in Figures 8 and 9, the super junction structure of the present invention (Figure 8) is compared with the conventional trench super junction structure (Figure 9), in which the depth of the trench is the same as the thickness of the entire epitaxial layer.

Fig. 10 is a breakdown voltage comparison chart of a traditional trench superjunction combined with the superjunction structure of the present invention, wherein the depth of the trench is the same as the thickness of the entire epitaxial layer. From the results of the simulated breakdown voltage, the present invention introduces an embedded p-type region , can effectively increase the breakdown voltage of the device.

Fig. 11 is the electric field distribution of the electric field extension x=0 simulated by the traditional trench superjunction combined with the superjunction structure of the present invention, wherein the depth of the trench is the same as the thickness of the entire epitaxial layer, and the breakdown voltage is the integral of the electric field along the y direction. The introduction of the p-type region makes the electric field drop more gently at the tail end, so that the integrated area of the electric field is larger, and the breakdown voltage is increased.

An embedded p-type region is implanted at the bottom of the superjunction p-pillar, which is aligned with the superjunction p-pillar.

The p-type region is not connected to the p-pillar of the super junction, and the distance is within 3um to 20um.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (6)

1. the preparation method of a hyperconjugation VDMOS, it is characterized in that, the method is: at N+ Grown the one N-epitaxial loayer, the boron first being carried out p-type impurity by reticle injects formation p-type area, continue epitaxial growth the 2nd N-epitaxial loayer, 2nd N-extension injects boron by reticle, forms body and push away trap; Then on described 2nd N-epitaxial loayer, define trench region by photoetching and carry out deep plough groove etched and backfill P-type monocrystalline silicon, forming the P-pillar district of hyperconjugation VDMOS device; Then the heat growth of grid oxygen and the deposit of N+ type polysilicon is carried out; After polysilicon photoetching, define N+ injection zone by photoetching process and inject N+ impurities, and annealing forms N+ source region; Then carry out the deposit of inter-level dielectric, and etch electrode contact; Splash-proofing sputtering metal Al, forms last device architecture after photoetching.

2. the preparation method of hyperconjugation VDMOS according to claim 1, is characterized in that: described in carry out deep plough groove etched formation deep trench and be positioned at a described N-epitaxial loayer p-type area aim at.

3. the preparation method of hyperconjugation VDMOS according to claim 1 and 2, is characterized in that: described is the N-epitaxial loayer of 10-20um at N+ Grown thickness.

4. the preparation method of hyperconjugation VDMOS according to claim 3, is characterized in that: described N+ impurities is As or P.

5. a hyperconjugation VDMOS device, it is characterized in that, this device comprises N+ substrate, a N-epitaxial loayer, the 2nd N-epitaxial loayer that superposition is arranged, and is provided with p type island region in a described N-epitaxial loayer, being provided with P-pillar district in described 2nd N-epitaxial loayer, aligns with p type island region in described P-pillar district.

6. hyperconjugation VDMOS device according to claim 5, is characterized in that: the distance between described P-pillar district and p type island region is 3um to 20um.