CN105515543A - Stacked radio frequency power amplifier with optimal matching - Google Patents

Abstract

The invention discloses a stacked RF power amplifier with optimal matching, including an input matching circuit, an output broadband matching circuit, a bias circuit A, a bias circuit B, and at least two transistor drains and sources connected through inductance Stacked power amplification circuit; the signal source is connected to the gate of the bottom transistor of the power amplification circuit through the input matching circuit, and the bias circuit B is also connected to this gate; the bias circuit A is connected to the gates of the remaining transistors of the power amplification circuit , these gates are grounded by connecting gate capacitors; the drains of the uppermost transistors are connected to the load through the output broadband matching circuit. The circuit not only improves the withstand voltage capability and current driving capability of the output stage of the radio frequency power amplifier, improves the output impedance of the power amplifier, but also improves the overall linearity of the power amplifier.

Description

A Stacked RF Power Amplifier with Optimal Matching

technical field

The invention relates to a power amplifier, in particular to a radio frequency power amplifier.

Background technique

As an important component of the transceiver in the modern wireless communication system, the RF power amplifier is mainly used to amplify the low-power RF electrical signal without distortion, and radiate it through the antenna for information communication.

The RF power amplifier structure includes various forms, such as linear power amplifier structure and saturated power amplifier structure, etc. With the different modulation methods used in wireless communication systems, the corresponding RF power amplifiers are different. For example, in order to provide high-speed data stream services, modern communication systems use modulation methods such as QPSK, which requires that the power amplifier used in the system must have high linearity and efficiency.

In addition, as the functional modules of portable devices become more and more complex, if each functional module can be integrated on the same chip, the mass production and processing time of the chip can be greatly shortened. Therefore, how to reduce the effective area of the chip It has important practical application significance to realize the whole radio frequency module on a single chip with a cheap process.

However, since the baseband processing part of most wireless transceivers uses a silicon process, and this process is the most mature and lowest cost process, the use of a silicon CMOS process is an ideal solution for full integration. However, there are insurmountable physical defects in the silicon CMOS process itself, such as low breakdown voltage and low power density. The traditional design method connects multiple transistors in parallel to increase the overall current. However, if the supply voltage is too low, the optimal output impedance of the power amplifier will become very small, making the design of the output matching circuit very difficult.

In Chinese patent 201510150849.1, the cascode RF power amplifier structure is used to overcome the withstand voltage problem of the power stage. However, in this structure, the gates of the stacked transistors are connected to the decoupling capacitors, so that the poles are It is grounded during AC. However, when the input power of this structure is relatively large, impedance mismatch will occur, so that the power cannot be superimposed in the same direction, thereby limiting the power output capability of the power amplifier.

Contents of the invention

In Chinese patent 201510150849.1, the cascode RF power amplifier structure is used to overcome the withstand voltage problem of the power stage. However, in this structure, the gates of the stacked transistors are connected to the decoupling capacitors, so that the poles are It is grounded during AC. However, when the input power of this structure is large, impedance mismatch will occur, so that the power cannot be superimposed in the same phase, thereby limiting the power output capability of the power amplifier. The object of the present invention is to overcome the above disadvantages of the prior art, and provide a stacked RF power amplifier with optimal matching.

Concrete technical scheme of the present invention is:

A stacked RF power amplifier with optimal matching, the RF power amplifier includes an input matching circuit, an output broadband matching circuit, a bias circuit A, a bias circuit B, and at least two transistor drain sources connected through an inductor A stacked power amplification circuit; wherein, the radio frequency signal source is connected to the gate of the bottom transistor of the power amplification circuit through the input matching circuit, and the bias circuit B is connected to the gate of the bottom transistor; Said bias circuit A is connected to the gates of the remaining transistors of said power amplifying circuit except said bottom transistor, and the gates of said remaining transistors are grounded by connecting gate capacitance; The pole is connected to the load through the output broadband matching circuit. This technical solution uses separate bias circuits A and B to bias each transistor, wherein bias circuit B provides a suitable static operating point for the transistor stacked at the bottom layer, and bias circuit A provides Suitable static working point. The input matching circuit converts the impedance of the transistor of the power amplifier circuit into the source impedance of the signal source to complete the conjugate matching, thereby obtaining the maximum RF power gain. In order to enable each transistor to output the maximum power, a capacitor is loaded on the gate of each stacked transistor, and an inductor is connected between every two stacked transistors, so that the output voltage of each transistor is superimposed with the same amplitude, The linearity and power output capability of the power amplifier circuit are enhanced, and the impedance seen from the drain of each transistor to the load direction is the optimal impedance. The signal is output from the drain of the transistor on the top layer, and is transmitted to the load terminal through the output broadband matching circuit. The broadband matching circuit transforms the load impedance into the optimal impedance when the power amplifier circuit can output the maximum power.

Preferably, said bias circuit A and bias circuit B are replaced by an integrated bias circuit.

Preferably, the source of the bottommost transistor is directly grounded.

Preferably, the bias circuit B is a bias circuit composed of resistors and transistors, and the bias circuit A is a resistor divider bias circuit. Bias circuit B is a bias circuit composed of resistors and transistors, with high precision and small footprint; bias circuit A is resistor divider bias, this bias method not only has a good temperature suppression coefficient, but also is easy to integrate .

Preferably, the bias voltages of the stacked transistors in the power amplifying circuit are not equally divided, the bias voltage of the uppermost transistor is the lowest, the bias voltage of the lowermost transistor is the highest, and the bias voltages of the remaining transistors are between the two , so that when the power amplifier circuit outputs high power, the DC voltage of each transistor converges at one point, so that each transistor has a consistent static state at high output power, thereby enhancing the output power and linearity of the power amplifier circuit.

Preferably, a second harmonic suppression circuit is provided in the output broadband matching circuit; and the choke inductance and the output capacitor of the output stage of the power amplifier circuit can be combined to better realize the second harmonic short circuit and the third harmonic open circuit, Thus, the efficiency of the power amplifier circuit is greatly improved.

Preferably, the power supply is connected to the drain of the uppermost transistor of the power amplifier circuit via a filter circuit.

Preferably, the filter circuit is composed of a filter capacitor and a choke inductor.

Preferably, the filter circuit is composed of a low-frequency filter capacitor, a high-frequency filter capacitor and a choke inductor.

Beneficial effects of the present invention: the circuit not only improves the withstand voltage capability and current driving capability of the output stage of the radio frequency power amplifier, but also increases the output impedance of the power amplifier, so that the output matching circuit becomes easy to realize. In addition, by connecting capacitors to the gates of stacked transistors, every two adjacent transistors are connected through inductance, so as to provide a suitable AC impedance for the pole, and then make the output power of each transistor more uniform, thereby improving The overall linearity of the power amplifier is improved. The invention can also improve the output voltage swing, working bandwidth, power efficiency, power gain and maximum output power of the radio frequency power amplifier, and has better second harmonic suppression effect.

Description of drawings

Fig. 1 is a circuit diagram of the radio frequency power amplifier of the embodiment.

The part circled by the dotted box in the figure is the power amplifier circuit part.

detailed description

A preferred embodiment of the present invention, a stacked radio frequency power amplifier with optimal matching, the radio frequency power amplifier includes an input matching circuit, an output broadband matching circuit, a bias circuit A, a bias circuit B, and at least two A power amplifying circuit in which the drains and sources of two transistors are connected and stacked through inductances, inductances L1 to Ln in the figure; wherein, the radio frequency signal source RFin is connected to the gate of the transistor M1 at the bottom of the power amplifying circuit through the input matching circuit , the bias circuit B is connected to the gate of the bottom transistor M1; the bias circuit A is connected to the gates of other transistors in the power amplifier circuit except the bottom transistor, that is, transistors M2 to Mn; The source of the bottommost transistor M1 is directly grounded, and the gates of the remaining transistors are connected to the ground through gate capacitance, that is, capacitors C1 to Cn; the drain of the uppermost transistor Mn of the power amplifier circuit is connected to the output The broadband matching circuit and the load RL are sequentially connected. The power supply VDD is connected to the drain of the uppermost transistor Mn of the power amplifying circuit through a filter circuit; the filter circuit is composed of a low-frequency filter capacitor Cp1, a high-frequency filter capacitor Cp2 and a choke inductance Lc. The bias circuit B is a bias circuit composed of resistors and transistors. The bias circuit A is a resistor voltage-dividing bias circuit. The bias voltage is not equally divided. The bias voltage of the top transistor is the lowest, and the bias voltage of the bottom transistor is set at the highest voltage, and the rest of the transistors are biased at intermediate voltages.

Claims (9)

1. A stacked RF power amplifier with optimal matching is characterized in that: the RF power amplifier includes an input matching circuit, an output broadband matching circuit, a bias circuit A, a bias circuit B, and at least two transistor drains A power amplifying circuit in which the poles and sources are connected and stacked through inductance; wherein, the radio frequency signal source is connected to the gate of the bottom transistor of the power amplifying circuit through the input matching circuit, and the bias circuit B is connected to the bottom transistor The gate of the transistor; the bias circuit A is connected to the gates of the remaining transistors of the power amplifying circuit except the bottom transistor, and the gates of the remaining transistors are grounded by connecting gate capacitance; the power amplifying circuit The drain of the uppermost transistor is connected to the load through the output broadband matching circuit. 2. The radio frequency power amplifier with optimal matching stack according to claim 1, characterized in that: said bias circuit A and bias circuit B are replaced by an integrated bias circuit. 3. The radio frequency power amplifier with an optimally matched stack according to claim 1, characterized in that: the source of the bottommost transistor is directly grounded. 4. The stacked RF power amplifier with optimal matching according to claim 1, characterized in that: the bias circuit B is a bias circuit composed of resistors and transistors, and the bias circuit A is a resistor divider bias circuit set the circuit. 5. The stacked RF power amplifier with optimal matching according to claim 1, characterized in that: the bias voltages of the stacked transistors in the power amplifier circuit are not equally divided, and the bias voltage of the topmost transistor is the lowest, The bottommost transistor has the highest bias voltage, and the rest of the transistors have bias voltages in between. 6 . The stacked radio frequency power amplifier with optimal matching according to claim 1 , wherein a second harmonic suppression circuit is provided in the output broadband matching circuit. 7 . 7. The stacked RF power amplifier with optimal matching according to claim 1, wherein the power supply is connected to the drain of the uppermost transistor of the power amplifying circuit through a filter circuit. 8. The stacked radio frequency power amplifier with optimal matching according to claim 7, wherein the filter circuit is composed of a filter capacitor and a choke inductor. 9. The stacked radio frequency power amplifier with optimal matching according to claim 8, wherein the filter circuit is composed of a low frequency filter capacitor, a high frequency filter capacitor and a choke inductor.