CN105529326B - Memory element and its manufacturing method - Google Patents

Abstract

The present invention provides a storage element and a manufacturing method thereof, wherein the storage element comprises a plurality of cup-shaped capacitors, a bottom support layer and a top support layer. The cup-shaped capacitor is located on a substrate. The bottom support layer is arranged on the substrate between the plurality of lower side walls of the cup-shaped capacitor. The top support layer is arranged around the plurality of upper side walls of the cup-shaped capacitor. There is a gap between the top support layer and the bottom support layer. The top support layer comprises a peripheral support layer and a core support layer. The peripheral support layer is arranged outside the cup-shaped capacitor and connected to the cup-shaped capacitor. The core support layer is arranged inside the peripheral support layer. Moreover, the core support layer and the peripheral support layer are separated by a gap, which connects any two adjacent cup-shaped capacitors.

Description

Memory element and its manufacturing method

technical field

The present invention relates to a memory element and its manufacturing method.

Background technique

With the miniaturization of semiconductor technology, the traditional capacitor technology is no longer sufficient. Researchers develop dielectric materials with high dielectric constants and increase the surface area of capacitors to increase the capacitance of capacitors. In general, the most common way to increase surface area is to increase capacitor height or size. However, the above method easily leads to the problem of insufficient mechanical strength of the capacitor itself and the problem of short circuit (Short) of adjacent capacitors. When the mechanical strength of the capacitor is insufficient, it is easy to find that the capacitor structure is deformed or even collapsed; and when the adjacent capacitor is short-circuited, the reliability of the product will be reduced. In view of this, how to prevent adjacent capacitors from short-circuiting while having a reinforced structure has drawn great attention from the industry.

Contents of the invention

The present invention provides a memory element and its manufacturing method, which can avoid the problem of short circuit of adjacent capacitors.

The present invention provides a storage element and a manufacturing method thereof, which can increase the mechanical strength of a capacitor.

The present invention provides a memory element, which includes a plurality of cup capacitors, a bottom support layer and a top support layer. Cup capacitors are on the substrate. The bottom support layer is disposed on the substrate between the plurality of lower sidewalls of the cup-shaped capacitor. The top supporting layer is configured around the plurality of upper sidewalls of the cup-shaped capacitor. The top support layer and the bottom support layer have gaps between each other. The top support layer includes a peripheral support layer and a core support layer. The peripheral supporting layer is arranged on the periphery of the cup capacitor and connected with the cup capacitor. The core support layer is configured in the peripheral support layer. Moreover, there is a gap between the core support layer and the peripheral support layer, which connects any two adjacent cup-shaped capacitors.

The invention provides a method for manufacturing a memory element, the steps of which are as follows. Provide the substrate. The substrate has a plurality of conductor regions. A bottom support layer is formed on the substrate. The bottom supporting layer exposes the conductor area. A plurality of cup-shaped lower electrodes are formed on the substrate. The cup-shaped lower electrode is electrically connected with the conductor area. The bottom support layer is located between the plurality of lower sidewalls of the cup capacitor. A top support layer is formed on the substrate, which is disposed around the plurality of upper sidewalls of the cup capacitor. There is a gap between the top supporting layer and the bottom supporting layer. The top support layer includes a peripheral support layer and a core support layer. The peripheral support layer is located on the periphery of the cup-shaped capacitor and connected with the cup-shaped capacitor. The core support layer is located in the peripheral support layer and separated from the peripheral support layer by a gap. The core support layer connects any two adjacent cup capacitors.

Based on the above, the embodiment of the present invention utilizes a core support layer disposed between any two adjacent cup capacitors to avoid excessive hole expansion (Hole Expansion) of adjacent cup capacitors during the etching process, resulting in adjacent cup capacitors capacitor short circuit problem. In addition, the core supporting layer of the embodiment of the present invention can provide additional mechanical strength, so as to avoid deformation or even toppling of the cup capacitor of the embodiment of the present invention.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1A to 1H are schematic top views of the manufacturing process of a storage element according to a first embodiment of the present invention;

2A to 2H are schematic cross-sectional views along the line A-A of FIGS. 1A to 1H ;

3A to 3H are schematic cross-sectional views along the line B-B of FIGS. 1A to 1H ;

4A to 4F are schematic top views of the manufacturing process of the storage element according to the second embodiment of the present invention;

5A to 5F are schematic cross-sectional views along the line A-A of FIGS. 4A to 4F, respectively;

FIGS. 6A to 6F are schematic cross-sectional views along line B-B of FIGS. 4A to 4F .

Explanation of reference signs:

10, 40, 50: Groove;

20, 60: opening;

30, 70, 80: clearance;

32, 72: void;

100, 200: substrate;

102, 126, 202, 226: dielectric layer;

104, 204: conductor area;

106, 106a, 110, 110a, 110b, 111, 118, 118a, 206, 206a, 210, 210a, 210b, 211, 218a, 218b: support layer;

108, 108a, 208, 208a: insulation layer;

112, 120, 120a, 212, 220, 220a: mask layer;

114, 122, 222: photoresist layer;

116, 218: material layer;

116a, 116b, 216a, 216b: spacers;

123, 223: groove;

124, 128, 224, 228: electrodes;

130, 230: capacitors;

219: Padding layer.

Detailed ways

1A to 1H are schematic top views of a manufacturing process of a storage device according to a first embodiment of the present invention. 2A to 2H are schematic cross-sectional views along line A-A of FIGS. 1A to 1H . 3A to 3H are schematic cross-sectional views along line B-B in FIGS. 1A to 1H .

Please refer to FIG. 1A , FIG. 2A and FIG. 3A at the same time. First, a substrate 100 is provided. The substrate 100 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor over insulator substrate (Semiconductor Over Insulator, SOI for short). Semiconductors are, for example, atoms of group IVA, such as silicon or germanium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of group IVA, such as silicon carbide or germanium silicide, or a semiconductor compound formed of atoms of group IIIA and group VA, such as gallium arsenide.

Then, a dielectric layer 102 and a plurality of conductor regions 104 are sequentially formed on the substrate 100 . The material of the dielectric layer 102 can be, for example, silicon oxide, silicon oxynitride or a low dielectric constant material, and its formation method can be formed by chemical vapor deposition. The conductor region 104 is disposed in the dielectric layer 102 . In one embodiment, the conductive regions 104 are arranged in an array. The material of the conductor region 104 can be, for example, doped polysilicon, non-doped polysilicon or a combination thereof, and its formation method can be formed by chemical vapor deposition. In one embodiment, the conductive region 104 may be electrically connected to a buried word line in the substrate 100 , for example.

Next, a bottom support layer 106 , an insulating layer 108 and a peripheral support layer 110 are sequentially formed on the substrate 100 . The bottom support layer 106 and the peripheral support layer 110 can be, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiCON), silicon carbide (SiC) or a combination thereof, and the formation method can use chemical vapor deposition method. The thickness of the bottom support layer 106 is, for example, 50 angstroms to 1500 angstroms; the thickness of the peripheral support layer 110 is, for example, 50 angstroms to 2500 angstroms.

The material of the insulating layer 108 can be, for example, silicon oxide or borophosphosilicate glass (BPSG), and its formation method can be chemical vapor deposition. The thickness of the insulating layer 108 is, for example, 5000 angstroms to 30000 angstroms.

Please continue to refer to FIG. 1A , FIG. 2A and FIG. 3A at the same time. Next, a mask layer 112 and a patterned photoresist layer 114 are sequentially formed on the peripheral support layer 110 . In one embodiment, the mask layer 112 may be, for example, a composite layer composed of a hard mask layer and a bottom anti-reflection layer, but the invention is not limited thereto. The material of the hard mask layer can be, for example, silicon material, metal material or carbon material. The material of the bottom anti-reflection layer can be, for example, organic polymer, carbon or silicon oxynitride. The method for forming the hard mask layer and the bottom anti-reflection layer can be formed by chemical vapor deposition. The material of the patterned photoresist layer 114 is, for example, carbon, photoresist-like material, or oxynitride.

Please refer to FIG. 1A , FIG. 1B , FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3B at the same time, using the patterned photoresist layer 114 as a mask, an etching process is performed to form the peripheral supporting layer 110 a. The peripheral support layer 110 a has a groove 10 therein, exposing the surface of the insulating layer 108 . The location of the trench 10 partially overlaps with the location of the plurality of conductor regions 104 . The shape of the trench 10 includes square, rectangular, racetrack or star. Next, the remaining patterned photoresist layer 114 and/or mask layer 112 on the peripheral support layer 110a is removed.

Referring to FIG. 1B , FIG. 2B , and FIG. 3B simultaneously, a spacer material layer 116 is formed on the trench 10 . The spacer material layer 116 covers the top surface of the peripheral support layer 110 a and the sidewalls and bottom of the trench 10 (as shown in FIGS. 2D and 3D ). In one embodiment, the spacer material layer 116 may conformally cover the top surface of the peripheral support layer 110 a and the sidewalls and bottom of the trench 10 . The material of the spacer material layer 116 is, for example, silicon oxide (SiO), silicon oxynitride (SiON) or borophosphosilicate glass (BPSG) and the like. Its formation method is, for example, chemical vapor deposition. The material of the spacer material layer 116 is not limited to the above, as long as it has a high etching selectivity ratio with the peripheral support layer 110a, it is within the scope of the present invention.

Next, referring to FIG. 1C , FIG. 2C , and FIG. 3C , an anisotropic etching process is performed on the spacer material layer 116 to form a spacer 116 a on the sidewall of the trench 10 . Afterwards, the core support layer 118 is formed in the area surrounded by the spacer wall 116a. Specifically, after the spacers 116a are formed on the sidewalls of the trench 10, a support material layer is formed on the peripheral support layer 110a to cover the top surface of the peripheral support layer 110a, the sidewalls of the spacers 116a and the sides of the trench 10. on the bottom (not shown). Next, an etch-back process is performed on the support material layer to remove part of the support material layer and expose the top surface of the peripheral support layer 110a to form a core support layer 118 in the trench 10 (as shown in FIG. 2F and FIG. 3F ). In one embodiment, the core support layer 118 may be, for example, block-shaped. Shapes of the core support layer 118 include square, rectangular, racetrack, or star. The core support layer 118 can be, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiCON), silicon carbide (SiC) or a combination thereof, which can be formed by chemical vapor deposition. In an embodiment, the etch back process may be, for example, a dry etch process or a wet etch process.

Referring to FIG. 1D , FIG. 2D and FIG. 3D simultaneously, a mask layer 120 and a patterned photoresist layer 122 are sequentially formed on the substrate 100 . In an embodiment, the mask layer 120 may be, for example, a composite layer composed of a hard mask layer and a bottom anti-reflection layer, and the invention is not limited thereto. The material of the hard mask layer can be, for example, silicon material, metal material or carbon material. The silicon material can be, for example, undoped polysilicon or silicon oxynitride (SiON). The material of the bottom anti-reflection layer can be, for example, organic polymer, carbon or silicon oxynitride. The method for forming the hard mask layer and the bottom anti-reflection layer can be formed by chemical vapor deposition. The material of the patterned photoresist layer 122 can be, for example, carbon, photoresist-like material, or oxynitride. The patterned photoresist layer 122 has a plurality of grooves 123 . The position of the groove 123 corresponds to the position of the conductor region 104 below.

Please refer to FIG. 1E, FIG. 1F, FIG. 2E, FIG. 2F, FIG. 3E and FIG. 3F at the same time, use the patterned photoresist layer 122 as a mask, perform an etching process, and remove part of the mask layer 120 to form a patterned mask layer 120a. Then, using the patterned mask layer 120a as a mask, an etching process is performed to remove part of the peripheral support layer 110a, the core support layer 118, the insulating layer 108 and the bottom support layer 106 to form the peripheral support layer 110b and the core support layer. 118a, the insulating layer 108a and the bottom support layer 106a, and form a plurality of openings 20, exposing a plurality of conductor regions 104. During the etching process, the patterned photoresist layer 122 is also removed simultaneously. In addition, since the material around each opening 20 is approximately the same (mostly the surrounding support layer 110b), when performing the etching process, it can reduce the difference in the etching rate caused by the difference in the etching material, resulting in the communication between adjacent openings 20. Case. In this way, subsequent capacitive short circuit problems caused by the connection of adjacent openings 20 can be avoided.

Referring to FIG. 1F , FIG. 2F and FIG. 3F at the same time, a lower electrode 124 is formed on the inner side and bottom of each opening 20 . Specifically, a lower electrode material layer (not shown) is conformally formed on the substrate 100 first. The bottom electrode material layer covers the inside and bottom of each opening 20 and the top surface of the mask layer 120a. Next, an anisotropic etching process is performed to remove part of the material layer of the lower electrode, exposing the top surface of the mask layer 120 a to form the lower electrode 124 on the inner side and the bottom of each opening 20 . The lower electrode 124 in each opening 20 is electrically connected to the corresponding conductor region 104 . The material of the lower electrode 124 can be, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium tungsten (TiW), aluminum (Al), copper (Cu) or metal silicide, which can be used formed by chemical vapor deposition.

Please refer to FIG. 1F, FIG. 1G, FIG. 2F, FIG. 2G, FIG. 3F, and FIG. 3G at the same time, and perform an isotropic etching process to remove the patterned mask layer 120a, spacer 116b and insulating layer 108a. A gap 30 is formed between 118a and the peripheral support layer 110b. Since the materials of the peripheral support layer 110b, the core support layer 118a, the spacer 116b, and the insulating layer 108a are different, and the isotropic etching process has a high etching selectivity for the peripheral support layer 110b, the core support layer 118a, the spacer 116b, and the insulating layer 108a Therefore, the etching rates of the peripheral support layer 110b and the core support layer 118a are slower. Then, etchant flows in from the gap 30 to remove the insulating layer 108a to form a gap (Gap) 32 between the bottom support layer 106a and the peripheral support layer 110b and the core support layer 118a, exposing part of the outer side of the bottom electrode 124 . That is, the outer side of the lower electrode 124 in the opening 20 is exposed. At this time, after the insulating layer 108a is completely removed, a hollow structure is formed. The bottom support layer 106 a , the peripheral support layer 110 b , the core support layer 118 a and the bottom electrode 124 support the structure of the storage device according to the first embodiment of the present invention. Since the patterned mask layer 120a on the peripheral support layer 110b is also removed, the top surface of the lower electrode 124 is higher than the top surfaces of the peripheral support layer 110b and the core support layer 118a, thereby increasing the subsequent process. The charge storage capacity of the formed cup capacitor 130 (shown in FIG. 2H and FIG. 3H below). In one embodiment, the above-mentioned isotropic etching process includes a wet etching process, which may for example use an etching buffer (Buffer Oxide Etchant, BOE for short), hydrofluoric acid (HF), diluted hydrofluoric acid (Diluted Hydrogen Fluoride , referred to as DHF) or buffered hydrofluoric acid (BHF) and so on.

As shown in FIG. 1G , the peripheral support layer 110b surrounds the core support layer 118a, and there is a gap 30 between the peripheral support layer 110b and the core support layer 118a. The peripheral support layer 110 b and the core support layer 118 a form a top support layer 111 , and the top support layer 111 is disposed around a plurality of upper sidewalls of the lower electrode 124 . Since there is a core support layer 118a between any two adjacent openings 20, and the material of the core support layer 118a and the spacer 116b has a high etching selectivity ratio, it can avoid excessive formation of the opening 20 in the above-mentioned isotropic etching process. The case of reaming. In addition, the core support layer 118a also provides additional mechanical strength to support the structure of the memory device of the first embodiment of the present invention.

Referring to FIG. 1H , FIG. 2H and FIG. 3H simultaneously, the dielectric layer 126 and the upper electrode 128 are conformally formed on the lower electrode 124 to form a plurality of cup capacitors 130 . The upper electrode 128 also covers the bottom support layer 106a, the peripheral support layer 110b, and the core support layer 118a. The dielectric layer 126 is interposed between the upper electrode 128 and the lower electrode 124, and between the upper electrode 128 and the bottom support layer 106a, between the upper electrode 128 and the peripheral support layer 110b, and between the upper electrode 128 and the core support layer 118a between. In one embodiment, the dielectric layer 126 includes a high dielectric constant material layer, such as hafnium oxide (HfO), zirconium oxide (ZrO), aluminum oxide (AlO), aluminum nitride (AlN), titanium oxide (TiO), lanthanum oxide (LaO), yttrium oxide (YO), gadolinium oxide (GdO), tantalum oxide (TaO), or combinations thereof. The material of the upper electrode 126 can be, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium tungsten (TiW), aluminum (Al), copper (Cu) or metal silicide. The dielectric layer 126 and the top electrode 128 can be formed by chemical vapor deposition or atomic layer deposition (ALD) process.

Please refer to FIGS. 1H and 3H at the same time. The storage device according to the first embodiment of the present invention includes a plurality of cup capacitors 130 , a bottom support layer 106 a and a top support layer 111 . Cup capacitor 130 is located on substrate 100 . The bottom support layer 106 a is disposed on the substrate 100 between the plurality of lower sidewalls of the cup capacitor 130 . The top supporting layer 111 is disposed around a plurality of upper sidewalls of the cup capacitor 130 . More specifically, the top support layer 111 includes a peripheral support layer 110b and a core support layer 118a. The peripheral supporting layer 110 b is disposed on the periphery of the cup capacitor 130 and connected to the cup capacitor 130 . The core support layer 118a is disposed within the peripheral support layer 110b. The peripheral support layer 110b, the core support layer 118a and the bottom support layer 106a have gaps 32 between them. There is a gap 30 between the core support layer 118 a and the peripheral support layer 110 b, which connects any two adjacent cup capacitors 130 . In one embodiment, the gap 32 between the peripheral support layer 110b, the core support layer 118a and the bottom support layer 106a is filled with air. Since the dielectric coefficient of the air filling is close to 1, it is less likely to generate parasitic capacitance (Parasitic Capacitor) between adjacent cup capacitors 130 .

The cup capacitor 130 includes a plurality of lower electrodes 124 , upper electrodes 128 and a dielectric layer 126 . The lower electrode 124 is located on the substrate 100 , wherein the lower electrode 124 may be, for example, a cup-shaped lower electrode. A plurality of lower sidewalls of the lower electrode 124 are connected to the bottom support layer 106a. A plurality of upper sidewalls of the lower electrode 124 are connected to the top supporting layer 111 . The upper electrode 128 covers the surface of the lower electrode 126 , that is, covers the inner side, the bottom and the outer side of the lower electrode 126 . The dielectric layer 126 is at least disposed between the upper electrode 128 and the lower electrode 124 . In addition, the upper electrode 128 also covers the bottom support layer 106 a and the top support layer 111 . The dielectric layer 126 is also interposed between the upper electrode 128 and the bottom support layer 106 a and between the upper electrode 128 and the top support layer 111 . In one embodiment, the top surface of the cup capacitor 130 is higher than the top surfaces of the peripheral support layer 110 b and the core support layer 118 a, which can increase the charge storage capacity of the cup capacitor 130 . In an embodiment, the storage device according to the first embodiment of the present invention further includes a plurality of conductor regions 104 disposed on the substrate 100 . Each conductive region 104 is electrically connected to the bottom of the corresponding cup capacitor 130 .

4A to 4F are schematic top views of the manufacturing process of the storage device according to the second embodiment of the present invention. 5A to 5F are schematic cross-sectional views along line A-A of FIGS. 4A to 4F . FIGS. 6A to 6F are schematic cross-sectional views along line B-B of FIGS. 4A to 4F .

Please refer to FIG. 4A , FIG. 5A and FIG. 6A at the same time. According to the method of the first embodiment, a dielectric layer 202 and a plurality of conductor regions 204 are sequentially formed on the substrate 200 . The bottom support layer 206 , the insulating layer 208 and the peripheral support layer 210 having the trench 40 . And a spacer wall 216 a is formed on the sidewall of the trench 40 . The materials and formation methods of the dielectric layer 202, the plurality of conductor regions 204, the bottom support layer 206, the insulating layer 208, the peripheral support layer 210 having the trench 40, and the spacers 216a are the same as those of the dielectric layer 102, The plurality of conductor regions 104 , the bottom support layer 106 , the insulating layer 108 , the peripheral support layer 210 and the spacers 116 a are described above, and will not be repeated here.

Next, a support material layer 218 is conformally formed on the peripheral support layer 210 a to cover the top surface of the peripheral support layer 210 a , the sidewalls of the spacers 216 a and the bottom of the trench 40 . The supporting material layer 218 can be, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiCON), silicon carbide (SiC) or a combination thereof, which can be formed by chemical vapor deposition.

After that, referring to FIG. 4B , FIG. 5B and FIG. 6B , an anisotropic etching process is performed on the support material layer 218 to remove part of the support material layer 218 to form a core support layer 218 a on the sidewall of the spacer 216 a. The core support layer 218 a surrounds the trench 50 . In one embodiment, the anisotropic etching process may be, for example, a dry etching process. The dry etching process may be, for example, a reactive ion etching process (RIE). The core support layer 218a is located within the peripheral support layer 210a. The spacer 216a is disposed between the peripheral support layer 210a and the core support layer 218a. In one embodiment, the core support layer 218a may be ring-shaped, for example. Shapes of the core support layer 218a include square, rectangular, racetrack, or star.

Referring to FIG. 4B , FIG. 5B and FIG. 6B simultaneously, the filling layer 219 is formed in the core support layer 218 a. Specifically, a filling material layer is firstly formed on the core support layer 218a, which covers the peripheral support layer 210a, the spacers 216a and the top surfaces of the core support layer 218a and is filled into the groove 50 (not shown). Then, a part of the filling material layer is removed by a planarization process, exposing top surfaces of the peripheral support layer 210 a , the spacers 216 a and the core support layer 218 a to form the filling layer 219 in the trench 50 . In one embodiment, the planarization process may be, for example, a chemical mechanical polishing process (CMP) or an etch-back process. The material of the filling material layer may include, for example, silicon oxide, and its formation method may be formed by chemical vapor deposition.

Please refer to FIG. 4C, FIG. 5C and FIG. 6C at the same time. The steps are as described in FIG. 1D, FIG. 2D and FIG. The mask layer 220 covers the top surfaces of the peripheral support layer 210a, the spacers 216a, and the core support layer 218a. The patterned photoresist layer 222 has a plurality of grooves 223 . The position of the groove 223 corresponds to the position of the conductor region 204 below. The materials and formation methods of the mask layer 220 and the patterned photoresist layer 222 are the same as those of the mask layer 120 and the patterned photoresist layer 122 in the first embodiment above, and will not be repeated here.

Please refer to FIG. 4D, FIG. 5D and FIG. 6D at the same time. The steps are as described in FIG. 1F, FIG. 2F and FIG. , to form a patterned mask layer 220a. Then, using the patterned mask layer 220a as a mask, an etching process is performed to remove part of the peripheral support layer 210a, the core support layer 218a, the insulating layer 208 and the bottom support layer 206 to form the peripheral support layer 210b and the core support layer. 218b, the insulating layer 208a and the bottom supporting layer 206a, and form a plurality of openings 60 to expose a plurality of conductor regions 204 . During the etching process, the patterned photoresist layer 222 is also removed simultaneously. The method for forming the opening 60 is the same as that of the opening 20 in the first embodiment above, and will not be repeated here.

Afterwards, the bottom electrode 224 is formed on the inner side and the bottom of each opening 60 . The material and forming method of the bottom electrode 224 are as described above for the bottom electrode 124 of the first embodiment, and will not be repeated here.

Referring to FIG. 4E , FIG. 5E and FIG. 6E at the same time, an isotropic etching process is performed to remove the patterned mask layer 220 a , spacers 216 b , and insulating layer 208 a to expose part of the outer side of the lower electrode 224 . When the insulating layer 208a and the spacer 216b are removed, the filling layer 219 and the underlying insulating layer 208a are also removed to form the gap 70 in the core support layer 218b. Specifically, after an isotropic etching process is performed to remove the spacers 216b and the filling layer 219, a gap 80 is formed between the core support layer 218b and the peripheral support layer 210b, and a gap 70 is formed in the core support layer 218b. Since the materials of the peripheral support layer 210b, the core support layer 218b, the spacer 216b, the insulating layer 208a, and the filling layer 219 are different, and the isotropic etching process has a significant impact on the peripheral support layer 210b, the core support layer 218b, the spacer 216b, and the insulating layer 208a. 1. The filling layer 219 has a high etching selectivity ratio, therefore, the etching rates of the peripheral supporting layer 110b and the core supporting layer 118b are relatively slow. Then, etchant flows in from the gap 70 and the gap 80 to remove the insulating layer 208a to form a gap 72 between the bottom support layer 206a, the peripheral support layer 210b and the core support layer 218b, that is, expose the lower part of the opening 60. The outside of the electrode 224. At this time, after the insulating layer 208a is completely removed, a hollow structure is formed. It uses the bottom support layer 206 a , the peripheral support layer 210 b , the core support layer 218 b and the bottom electrode 224 to support the structure of the storage device according to the second embodiment of the present invention. In one embodiment, the above-mentioned isotropic etching process includes a wet etching process, which may for example use an etching buffer (Buffer Oxide Etchant, BOE for short), hydrofluoric acid (HF), diluted hydrofluoric acid (Diluted Hydrogen Fluoride , referred to as DHF) or buffered hydrofluoric acid (BHF) and so on.

As shown in FIG. 4E, the peripheral support layer 210b surrounds the core support layer 218b, and there is a gap 80 between the peripheral support layer 210b and the core support layer 218b. The core support layer 218b may, for example, be ring-shaped with a gap 70 therein. Since there is a core support layer 218b between any two adjacent openings 60, and the material of the core support layer 218b and the spacer wall 216b has a high etching selectivity ratio, it can avoid excessive formation of the opening 60 in the above-mentioned isotropic etching process. The case of reaming. Moreover, the core supporting layer 218b also provides additional mechanical strength to support the structure of the storage device in the second embodiment of the present invention. Additionally, the core support layer 218b has gaps 70 therein. When performing the above isotropic etching process, the etchant can also flow in from the gap 70 in addition to flowing in from the gap 80 to speed up the removal of the insulating layer 208 a, thereby achieving the effect of saving process time.

Please refer to FIG. 4F, FIG. 5F and FIG. 6F at the same time. The steps are as described in FIG. 1H, FIG. 2H and FIG. 230. The upper electrode 228 also covers the bottom support layer 206a, the peripheral support layer 210b and the core support layer 218b. The dielectric layer 226 is also interposed between the upper electrode 228 and the bottom support layer 206a and between the upper electrode 228 and the peripheral support layer 210b and the core support layer 218b. The materials and formation methods of the dielectric layer 226 and the upper electrode 228 are the same as those of the dielectric layer 126 and the upper electrode 128 in the first embodiment above, and will not be repeated here.

In summary, the embodiment of the present invention utilizes the core support layer disposed between any two adjacent cup capacitors to avoid excessive hole expansion of adjacent cup capacitors during the isotropic etching process, while Causes a short circuit problem between two adjacent cup capacitors. Moreover, the peripheral support layer and the core support layer of the embodiment of the present invention can provide additional mechanical strength, so as to prevent the cup capacitor of the embodiment of the present invention from being deformed or even toppled over, thereby improving the reliability of the product. Since the gaps between the peripheral support layer, the core support layer and the bottom support layer in the embodiment of the present invention are filled with air (its dielectric coefficient is close to 1), therefore, it is less likely to generate a gap between adjacent cup-shaped capacitors. parasitic capacitance. In addition, another embodiment of the present invention has gaps in the core support layer, which can speed up the removal of the insulating layer, so as to achieve the effect of saving process time.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (10)

1. A storage element, characterized in that, comprising: a plurality of cup capacitors on the substrate; a bottom support layer disposed on the substrate between the plurality of lower sidewalls of the cup capacitor; and The top support layer is arranged around the plurality of upper side walls of the cup-shaped capacitor, and there is a gap between the bottom support layer and the top support layer, and the top support layer includes: a peripheral support layer surrounding and connected to the capacitor cup; and The core support layer is in the peripheral support layer and separated from the peripheral support layer by a gap, and connects any two adjacent cup-shaped capacitors. 2. The memory element according to claim 1, wherein the cup capacitor comprises: A plurality of cup-shaped lower electrodes are located on the substrate, the plurality of lower side walls of the cup-shaped lower electrodes are connected to the bottom support layer, and the plurality of upper side walls of the cup-shaped lower electrodes are connected to the top support layer connection; an upper electrode covering the surface of the cup-shaped lower electrode; and The dielectric layer is disposed at least between the upper electrode and the cup-shaped lower electrode. 3. The memory element according to claim 2, wherein the upper electrode also covers the bottom support layer and the top support layer, and the dielectric layer is also interposed between the upper electrode and the top support layer. Between the bottom support layer and between the upper electrode and the top support layer. 4 . The memory element according to claim 1 , wherein the core supporting layer is block-shaped or ring-shaped. 5. The storage element according to claim 1, wherein the shape of the core support layer comprises a rectangle, a racetrack or a star. 6 . The memory element according to claim 1 , wherein materials of the bottom support layer and the top support layer each comprise silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide or a combination thereof. 7. The memory device according to claim 1, further comprising a plurality of conductor regions disposed on the substrate, wherein each conductor region is electrically connected to the bottom of the corresponding cup-shaped capacitor. 8. The memory element according to claim 1, wherein the gap between the top support layer and the bottom support layer is filled with air. 9. A method for manufacturing a memory element, comprising: providing a substrate having a plurality of conductor regions thereon; forming a bottom support layer on the substrate, the bottom support layer exposing the conductor region; forming a plurality of cup-shaped lower electrodes on the substrate, the cup-shaped lower electrodes are electrically connected to the conductor region, wherein the bottom support layer is located between the plurality of lower sidewalls of the cup-shaped capacitor; as well as A top support layer is formed on the substrate, disposed around a plurality of upper sidewalls of the cup-shaped capacitor, and has a gap with the bottom support layer, and the top support layer includes: a peripheral support layer surrounding and connected to the capacitor cup; and The core support layer is in the peripheral support layer and separated from the peripheral support layer by a gap, and connects any two adjacent cup-shaped capacitors. 10 . The method for manufacturing a memory element according to claim 9 , wherein the core support layer is block-shaped or ring-shaped. 11 .