CN105550432A - Three-dimensional integrated circuit chip and power network layout method thereof - Google Patents

Abstract

The present invention provides a three-dimensional integrated circuit chip and its power supply network layout method. The method includes: providing at least two layers of chips connected to each other; setting a rewiring layer on the top chip of the at least two layers of chips; The wiring layer communicates with the middle area of the top chip; connects the rewiring layer with an external power supply. In the three-dimensional integrated circuit chip and its power supply network layout method of the present invention, a rewiring layer is arranged on the top chip, and an external power supply is introduced into the middle area of the top chip through the rewiring layer, and other chips pass through silicon holes located in the middle area from the top layer. The chip obtains power supply. Since it is not limited by the thickness and area of the top-layer chip itself, it does not occupy the winding resources of the top-layer chip. The thickness and width of the wire on the redistribution layer can be designed to be very large, thereby greatly reducing the resistance on the wire. In this way, the power supply effect of the top chip will be greatly improved, thereby improving the power supply performance of the entire 3DIC chip.

Description

Three-dimensional integrated circuit chip and its power supply network layout method

technical field

The invention relates to the field of integrated circuits, in particular to a three-dimensional integrated circuit chip and a power supply network layout method thereof.

Background technique

With the increasing scale of SoC (system integrated chip), 3DIC (three-dimensional integrated circuit) chip is becoming mainstream. Ultra-large-scale 3DIC chips face huge challenges in the design of power supply networks. Insufficient power supply capacity will cause the entire 3DIC chip to fail to work properly. Therefore, how to extend the traditional SoC's two-dimensional power supply network to three dimensions and ensure the power supply capability is an important technology.

FIG. 1 is a schematic diagram of an existing 3DIC chip power supply solution. As shown in the figure, at least two layers (here shown as three layers) of chips 10 communicate with each other through TSVs (Through Silicon Vias) 20, wherein the top layer chips 11 are connected to pads 40 located at the edge area by wires 30, the pads 40 communicates with an external power supply (not shown) so as to introduce the external power supply to the top chip 11 , and other chips 12 obtain power supply from the top chip 11 through the TSV 20 located in the middle area. The prior art has a strong power supply capability for other chips 12 except the top chip 11. However, the power supply bottleneck of the entire 3DIC chip lies in the top chip 11 connected to the outside through the wire 30 and the pad 40. This is due to limited Due to the thickness and area of the top chip 11, the winding resources on the top chip 11 are very limited, so that the power supply conditions of the top chip 11 are only similar to those of ordinary two-dimensional chips. For the top chip 11, which is responsible for the power supply of the entire 3DIC chip, such a design It may cause insufficient power supply and thus affect the performance of the entire 3DIC chip.

Contents of the invention

The purpose of the present invention is to provide a three-dimensional integrated circuit chip and its power supply network layout method, which can improve the power supply effect of the top chip and improve the power supply performance of the whole three-dimensional integrated circuit chip.

Based on the above considerations, one aspect of the present invention provides a power supply network layout method of a three-dimensional integrated circuit chip, including: providing at least two layers of chips connected to each other; setting a rewiring layer on the top chip of the at least two layers of chips, The redistribution layer communicates with the middle area of the top chip; connects the redistribution layer with an external power supply.

Preferably, the redistribution layer communicates with the middle area of the top chip through a through-silicon via or a non-through-silicon via located in the middle area.

Preferably, the redistribution layer communicates with the external power supply through pads located in the edge region.

Preferably, at least two redistribution layers connected to each other are arranged on the top chip.

Preferably, the at least two redistribution layers are connected through non-through-silicon vias.

Another aspect of the present invention provides a three-dimensional integrated circuit chip, including: at least two layers of chips connected to each other; a rewiring layer arranged on the top chip of the at least two layers of chips, the rewiring layer and the The middle area of the top chip is communicated; the redistribution layer is communicated with the external power supply.

Preferably, the redistribution layer communicates with the middle area of the top chip through a through-silicon via or a non-through-silicon via located in the middle area.

Preferably, the redistribution layer communicates with the external power supply through pads located in the edge region.

Preferably, at least two redistribution layers connected to each other are arranged on the top chip.

Preferably, the at least two redistribution layers are connected through non-through-silicon vias.

In the three-dimensional integrated circuit chip and its power supply network layout method of the present invention, a rewiring layer is arranged on the top chip, and an external power supply is introduced into the middle area of the top chip through the rewiring layer, and other chips pass through silicon holes located in the middle area from the top layer. The chip obtains power supply. Since it is not limited by the thickness and area of the top-layer chip itself, it does not occupy the winding resources of the top-layer chip. The thickness and width of the wire on the redistribution layer can be designed to be very large, thereby greatly reducing the resistance on the wire. In this way, the power supply effect of the top chip will be greatly improved, thereby improving the power supply performance of the entire 3DIC chip.

Description of drawings

Other features, objects and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a power supply network of an existing three-dimensional integrated circuit chip;

Fig. 2 is the schematic diagram of the power supply network of the three-dimensional integrated circuit chip of the present invention;

FIG. 3 is a schematic diagram of the redistribution layer of the three-dimensional integrated circuit chip of the present invention.

In the drawings, the same or similar reference numerals denote the same or similar means (modules) or steps throughout different views.

detailed description

In order to solve the above-mentioned problems in the prior art, the present invention provides a three-dimensional integrated circuit chip and its power supply network layout method. A redistribution layer is arranged on the top chip, and an external power supply is introduced into the middle area of the top chip through the redistribution layer. Other The chip then obtains power supply from the top chip through the TSV located in the middle area. Since it does not need to be limited by the thickness and area of the top chip itself, it does not occupy the winding resources of the top chip, and the thickness and width of the wire on the redistribution layer can be designed. It is very large, thereby greatly reducing the resistance on the wire, so that the power supply effect of the top chip will be greatly improved, thereby improving the power performance of the entire 3DIC chip.

In the following detailed description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof. The accompanying drawings show, by way of example, specific embodiments in which the invention can be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments in accordance with the invention. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Accordingly, the following detailed description is not limiting, and the scope of the invention is defined by the appended claims.

One aspect of the present invention provides a power supply network layout method of a three-dimensional integrated circuit chip, comprising: providing at least two layers of chips 110 connected to each other; setting a redistribution layer 150 on the top chip 111 of the at least two layers of chips 110, The redistribution layer 150 communicates with the middle area of the top chip 111 ; connects the redistribution layer 150 with an external power supply.

As shown in FIG. 2 , at least two layers (shown here as three layers) of chips 110 communicating with each other are provided, and the three layers of chips 110 are communicated with each other through silicon vias 120 . On top of the original top chip 111, a layer of RDL (redistribution layer) 150 is added, and the redistribution layer 150 is connected to the pad 140 located in the edge area through the wire 130, and the pad 140 is connected to an external power supply (not shown) connected so as to introduce external power into the middle area of the rewiring layer 150, and the rewiring layer 150 communicates with the top chip 111 through the through-silicon via or non-through-silicon via 160 in the middle area so as to supply the power on the rewiring layer 150 to the top layer The middle area of the chip 111 is not limited to the thickness and area of the top chip 111 itself, and does not occupy the wiring resources of the top chip 111. The thickness and width of the wire 130 on the redistribution layer 150 can be designed very large, for example, For the large-area power supply wiring shown in Figure 3, in the redistribution layer area except for the necessary signal lines, under the premise of complying with the design rules, all power supply lines are filled to reduce the resistance on the wire 130, so that the top layer The power supply effect of the chip 111 will be greatly improved, and the other chips 112 will obtain power supply from the top chip 111 through the TSV 120 located in the middle area, thereby improving the power performance of the entire 3DIC chip.

Those skilled in the art can understand that, according to actual needs, more than two redistribution layers 150 may be disposed on the top chip 111 , and each redistribution layer 150 is connected to each other through non-through-silicon vias.

The non-through-silicon via in the present invention refers to a through-hole (Via) that does not pass through silicon.

Another aspect of the present invention provides a three-dimensional integrated circuit chip, including: at least two layers of chips 110 connected to each other; The layer 150 communicates with the middle area of the top chip 111; the redistribution layer 150 communicates with the external power supply.

Preferably, the redistribution layer 150 communicates with the middle area of the top chip 111 through a through-silicon via or a non-through-silicon via 160 located in the middle area.

Preferably, the redistribution layer 150 communicates with the external power supply through the pad 140 located in the edge area.

Preferably, the top chip 111 is provided with at least two redistribution layers 150 connected to each other, and the at least two redistribution layers 150 are connected through non-through-silicon vias.

In the three-dimensional integrated circuit chip and its power supply network layout method of the present invention, a rewiring layer is arranged on the top chip, and an external power supply is introduced into the middle area of the top chip through the rewiring layer, and other chips pass through silicon holes located in the middle area from the top layer. The chip obtains power supply. Since it is not limited by the thickness and area of the top-layer chip itself, it does not occupy the winding resources of the top-layer chip. The thickness and width of the wire on the redistribution layer can be designed to be very large, thereby greatly reducing the resistance on the wire. In this way, the power supply effect of the top chip will be greatly improved, thereby improving the power supply performance of the entire 3DIC chip.

It will be apparent to those skilled in the art that the invention is not limited to the details of the above-described exemplary embodiments, but that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Accordingly, the embodiments should be regarded in all respects as exemplary and not restrictive. For example, according to different packaging methods, the top chip in a multi-layer chip may be located above or below the package, so the "top layer" does not define a specific direction. Furthermore, it is obvious that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude the plural. A plurality of elements recited in device claims may also be embodied by one element. The words first, second, etc. are used to denote names and do not imply any particular order.

Claims (10)

1. a power network path approach method for three dimensional integrated circuits chip, is characterized in that, comprising:

At least layers of chips communicated with each other is provided;

Top layer chip in described at least layers of chips is arranged and to reroute layer, described in the layer that reroutes be communicated with the zone line of described top layer chip;

The described layer that reroutes is communicated with external power source.

2. the power network path approach method of three dimensional integrated circuits chip as claimed in claim 1, is characterized in that, described in the layer that reroutes be communicated with the zone line of described top layer chip by the silicon through hole or non-silicon through hole being positioned at zone line.

3. the power network path approach method of three dimensional integrated circuits chip as claimed in claim 1, is characterized in that, described in the layer that reroutes be communicated with described external power source by the pad being positioned at fringe region.

4. the power network path approach method of three dimensional integrated circuits chip as claimed in claim 1, is characterized in that, arranges at least two-layer layer that reroutes communicated with each other on described top layer chip.

5. the power network path approach method of three dimensional integrated circuits chip as claimed in claim 4, it is characterized in that, described at least two-layer rerouting between layer is communicated with by non-silicon through hole.

6. a three dimensional integrated circuits chip, is characterized in that, comprising:

At least layers of chips communicated with each other;

The layer that reroutes on top layer chip described in being arranged at least in layers of chips, described in the layer that reroutes be communicated with the zone line of described top layer chip;

The described layer that reroutes is communicated with external power source.

7. three dimensional integrated circuits chip as claimed in claim 6, is characterized in that, described in the layer that reroutes be communicated with the zone line of described top layer chip by the silicon through hole or non-silicon through hole being positioned at zone line.

8. three dimensional integrated circuits chip as claimed in claim 6, is characterized in that, described in the layer that reroutes be communicated with described external power source by the pad being positioned at fringe region.

9. three dimensional integrated circuits chip as claimed in claim 6, is characterized in that, described top layer chip is provided with at least two-layer layer that reroutes communicated with each other.

10. three dimensional integrated circuits chip as claimed in claim 9, it is characterized in that, described at least two-layer rerouting between layer is communicated with by non-silicon through hole.