CN105573951A - AHB interface system for stream data transmission - Google Patents

Abstract

An AHB bus interface system aimed at data stream transmission, the invention relates to an AHB bus interface system aimed at data stream transmission. The invention aims to solve the problem that the IP module cannot match the on-chip bus of the SOC because the existing method fails to provide a general interface, and provides an AHB bus interface system for data stream transmission. An AHB bus interface system for data stream transmission, which includes: a main control module, a register group module, a decoding control module, an abnormality detection module, a burst transmission monitoring module, an early termination judgment module, a block transmission processing module, and Rd_FIFO The module is the read FIFO module and the Wr_FIFO module is the write FIFO module. The invention is applied to the field of integrated circuits.

Description

An AHB bus interface system for data stream transmission

technical field

The invention relates to an AHB bus interface system for data flow transmission.

Background technique

With the development of integrated circuit technology, SOC (System On Chip, System on Chip) has gradually become the focus of IC design. There are two main methods of SOC design: one is based on functional design, that is, the modules are divided and designed according to requirements, and then integrated into a system; the other is based on assembly design, that is, composed of multiplexed IP design system. At present, the second design method has gradually become the mainstream. This method can achieve advantages such as larger scale and easier operation, and is more in line with the design requirements of SOC.

The most critical problem in the design of SOC system based on IP multiplexing is the IP interface. Since the IP module is provided by a third party, it cannot be guaranteed to match the on-chip bus of the SOC. Therefore, a design specification for a general interface standard has become a solution to this problem. Core. At present, the buses that are widely used on the chip are mainly AMBA series bus, AVALON bus, IBMCoreConnect bus, OCP bus, etc. Different buses have their own characteristics and applicable fields.

Contents of the invention

The invention aims to solve the problem that the IP module cannot match the on-chip bus of the SOC because the existing method fails to provide a general interface, and provides an AHB bus interface system for data stream transmission.

An AHB bus interface system for data stream transmission, which includes:

Main control module, register group module, decoding control module, anomaly detection module, burst transmission monitoring module, early termination judgment module, block transmission processing module, Rd_FIFO module is read FIFO module and Wr_FIFO module is write FIFO module;

Wherein, the main control module sends control signals to each module, coordinates the communication between each module and the communication with the AHB bus;

Wherein, the register group module is composed of a series of registers for AHB bus to read and write, and is used to store the data required for AHB bus transmission;

Wherein, the decoding control module decodes the read-write request and address information sent by the main control module, and controls the data access of the register group module;

Wherein, the abnormal detection module detects the FIFO state, judges whether the slave meets the transmission requirements, monitors the state of the Rd_FIFO module, the Wr_FIFO module and the read and write signals of the AHB bus, and indicates whether the current transmission meets the read and write requirements;

Wherein, the burst transmission monitoring module records the number of data of each burst transmission as a basis for judging whether the burst is terminated in advance or the burst transmission is completed;

Wherein, the early termination judging module detects whether the burst transmission is forced to be terminated, the host loses the possession of the AHB bus if the transmission is not completed, and when the AHB bus is handed over to other masters for use, according to the judging result of the early termination judging module, the slave stops the transmission data or establish communications with other hosts;

Wherein, the block transfer processing module detects whether the slave machine has the ability to perform a block transfer to the master, and notifies the master control module to send a signal requesting to complete the block transfer to the AHB bus, so that the master can continue to control the AHB bus.

Invention effect:

The present invention is developed aiming at the AHB (Advanced High-performance Bus) bus in the AMBA series bus developed by ARM company. The AHB bus is a bus standard designed for high performance and high clock frequency modules, and is mainly used for bus hosts, on-chip storage modules, belt High-speed modules such as peripherals of the FIFO (First in first output, first in first out queue) interface. The present invention is a simple and convenient implementation of high-performance data transmission based on the AHB bus. FIFO is used as a bridge for data transmission between the bus and the slave, which simplifies the interface and timing problems faced by the slave and the bus communication. It can be used as a A general AHB bus data stream transmission method, and this method is also applicable to slaves that support block transfer.

The main purpose of this system is to design a standardized and convenient interface for the AHB bus slave. This interface can meet the timing requirements of the AHB bus protocol and has certain versatility. It is especially suitable for processing data stream transmission.

The design scheme of this system chooses FIFO as the general interface for data transmission. FIFO has the advantages of simple timing, less signals, and strong configurability, which simplifies the interface design of the user module mounted on the AHB bus.

Description of drawings

Figure 1 is a diagram illustrating the communication mechanism of the host and slave;

Fig. 2 is the working schematic diagram of the present invention to slave system;

Fig. 3 is that the present invention is the design structural diagram to slave machine interface;

Fig. 4 is a design diagram of the main control module in the slave machine interface structure diagram.

detailed description

Specific implementation mode 1: As shown in Figure 1, the AHB bus protocol is designed based on the central multiplexer interconnection scheme, and the interconnection modules include a master, a slave, an arbiter, and a decoder. The structural diagram of the system is shown in Figure 1 shown. The AHB bus supports the communication mode of multi-master and multi-slave. The arbiter determines the master that has obtained the ownership of the AHB bus, and sends control signals and writes data to the slave by controlling the multiplexer. The decoder determines that a certain slave data is valid, and sends the valid data to the master through the multiplexer.

As shown in Figure 2, for the schematic diagram of the slave system description in this design, FIFO is selected as the general interface for data transmission. The bus selects the slave and the transmission mode between the slave and the slave by sending control signals. Rd_FIFO writes data to some registers, if the transfer is a read transfer, the bus reads the data stored in these registers; Wr_FIFO reads the data in some registers, if the transfer is a write transfer, the bus writes the data in these registers. The user module can only read the state in the FIFO, control the signal of the corresponding FIFO, and realize the reading and writing of data, which simplifies the interface relationship between the slave and the AHB bus.

As shown in Figure 3, an AHB bus interface system for data stream transmission includes a main control module, a register group module, a decoding control module, an abnormality detection module, a burst transmission monitoring module, an early termination judgment module, and a block The transmission processing module, the Rd_FIFO module is the read FIFO module and the Wr_FIFO module is the write FIFO module;

Wherein, the main control module sends control signals to each module, coordinates the communication between each module and the communication with the AHB bus;

Wherein, the register group module is composed of a series of registers for AHB bus to read and write, and is used to store the data required for AHB bus transmission;

Wherein, the decoding control module decodes the read-write request and address information sent by the main control module, and controls the data access of the register group module;

Wherein, the abnormal detection module detects the FIFO state, judges whether the slave meets the transmission requirements, monitors the state of the Rd_FIFO module, the Wr_FIFO module and the read and write signals of the AHB bus, and indicates whether the current transmission meets the read and write requirements;

Wherein, the burst transmission monitoring module records the number of data of each burst transmission as a basis for judging whether the burst is terminated in advance or the burst transmission is completed;

Wherein, the early termination judging module detects whether the burst transmission is forced to be terminated, the host loses the possession of the AHB bus if the transmission is not completed, and when the AHB bus is handed over to other masters for use, according to the judging result of the early termination judging module, the slave stops the transmission data or establish communications with other hosts;

Wherein, the block transmission processing module is for a slave with block transfer capability, if the slave is not ready to transmit data, the communication between a certain master and the slave is notified that block transfer is required, and the master is suspended, No longer control the AHB bus; detect whether the slave has the ability to perform a block transmission on the master, and notify the master control module to send a signal to the AHB bus to request the completion of the block transfer, so that the master can continue to control the AHB bus;

Wherein, the slave machine refers to any user module and its interface with independent functions, and the exchange of its data is carried out directly through two FIFO modules, that is, the Rd_FIFO module and the Wr_FIFO module. If the Wr_FIFO module is not empty, then read the Data, if the Rd_FIFO module is not full, the result processed by the user module is written into the Rd_FIFO module;

Wherein, the Rd_FIFO module stores the data processed by the user module, and the signal of its empty and full state is sent to the abnormal detection module and the user module, and the user module judges whether to write data according to whether it is full, and the main control module controls whether to read its Data to the register bank module;

Wherein, the Wr_FIFO module stores data that needs to be processed by the user module, and its empty and full state signal is sent to the abnormal detection module and the user module, and the user module judges whether to read data according to whether it is empty, and the main control module controls whether it writes Output data for the register file block.

Wherein, the control signal sent by the AHB bus to the slave includes: Hsel, HADDR, Hwrite, Htrans, Hsize, Hburst, Hmaster, Hmasterlock, because there are too many signals and the above signals have the same timing, here use Hctrl as the above control signal representation. The response signals sent from the slave to the AHB bus include: Hsplit, Hready, and Hresp. Table 1 briefly introduces the control signals of the interface between the AHB bus and the slave, and will not explain the subsequent AHB bus control signals.

Table 1. AHB bus control signal description

First, the AHB bus sends a control signal to the slave, indicating that the slave is selected to perform data transmission. The AHB bus communicates with the register group module. The main control module sends control to the corresponding FIFO according to the status of the slave and the control information sent by the AHB bus. Read and write signals, if the slave machine meets the communication requirements, the main control module sends the slave machine ready indication to the AHB bus, and the corresponding FIFO reads or writes data to the register group module and the user module, and a data transmission can be completed , the slave sends a successful response. The timing of AHB stipulates that the address and control signals are sent before the data, so the control information corresponding to each data appears in the previous clock cycle.

If the slave does not meet the communication requirements, the abnormal detection module sends an interrupt request to the main control module. The request can be divided into two types: one indicates the current transmission error, the master fails to transmit, the master cancels the remaining transmission, and the error type is stored in the register group In the middle, it can be viewed by the host; if one indicates block transmission, the host loses the right to use the AHB bus, and waits for the slave to be ready to continue the transmission before restoring it;

The main control module sends a slave response to the AHB bus according to the judgment result of the abnormality detection module. If the slave sends a block transmission signal, the block transmission processing module records this, and detects in real time whether the slave is ready to transmit to the master OK, if it is ready and there is no new transmission in progress, the block module will send to the main control module to prepare to resume the unfinished transmission of the host, if it is ready but there are other transmissions in progress, the block module will wait for the end of the transmission before sending Request to restore the signal transmitted by the host, the main control module sends a block request signal to the bus according to the recovery signal, and then continue to complete the transmission of the remaining data of the host;

When a host occupies the bus for transmission, the burst may end prematurely. When the trans signal is idle or nonseq, it indicates that a new transmission starts. Each burst transmission can be divided according to this signal. When a If the number of data transmitted in a burst is less than the number of bursts indicated by the burst signal, it means that the transmission is terminated early, and the counting module records the number of data transmitted in each burst, and the early termination judgment module judges accordingly , and send the result to the main control module, and the main control module also needs to perform timing control according to the records of the data volume.

Based on the above design ideas, as shown in Figure 2, the specific design scheme of the interface circuit is described. In this structure diagram, all signals connected to the user module use usr as the suffix, and all signals connected to the bus use H as the initial letter.

Specific implementation mode two: the difference between this implementation mode and specific implementation mode one is:

Figure 4 is the design of the main control module of the system. The jump conditions between the states in the figure can be queried in Table 2 according to the labels.

The input of the main control module is the control signal sent by the AHB bus to the slave and the detection results of each module, and the output is the response of the slave and the control signal of each module;

The main control module is in the idle state, waiting for transmission; if the slave is selected for transmission and the transmission type is nonseq and indicates read/write and the slave is ready, then jump to the trans state; if the slave is ready to complete the block For transmission, jump to the hsplit state; if the Rd_FIFO module and the Wr_FIFO module are both empty during the read transmission, or if the Wr_FIFO module and the Rd_FIFO module are both full during the write transmission, then jump to the error state; if the Rd_FIFO module is empty during the read transmission And the Wr_FIFO module is not empty, or the Wr_FIFO module is full and the Rd_FIFO module is not full during the write transmission, then jump to the split state;

Described master control module carries out data transmission in trans state, reads and transmits then reads the data in the Rd_FIFO module, and writes and transmits and then writes data in the Wr_FIFO module; If in the process of reading and transmitting, the Rd_FIFO module appears to be empty but the Wr_FIFO module is not Empty, or, during the write transmission process, if the Wr_FIFO module is full and the Rd_FIFO module is not full, then jump to the split state; if the read transmission process shows that both the Rd_FIFO module and the Wr_FIFO module are empty, or, during the write transmission process, If the Wr_FIFO module and the Rd_FIFO module are both full, jump to the error state; if the control signal of a locked transmission is sent, jump to the wait state; if the transmission is completed, the slave is abandoned and the non-locked transmission, then jump Go to the idle state; if the transmission is completed, the slave is abandoned and the slave is ready to complete the block transfer, then jump to the hsplit state;

The main control module is in the wait state, waiting for the slave to be ready to complete the data of the last locked transmission; if the slave is ready, then jump to idle; otherwise, continue to wait in the wait;

In the hsplit state, the main control module sends a signal Hsplit that completes the block request to the AHB bus, and after only one cycle, it jumps to the idle state;

In the error state, the main control module sends Hresp to the AHB bus as an error response, and Hready is set low, that is, the slave is not ready, this state is a cycle, and jumps to the sec_error state;

The sec_error state of the main control module keeps sending Hresp to the AHB bus as an error response, but Hready is set high to indicate that the slave is ready. This state lasts for one cycle and completes the double-cycle response of the error signal, which is convenient for the host to cancel the remaining transmission. Go to idle state;

In the split state, the main control module sends Hresp to the AHB bus as a block response, and Hready is set low, that is, the slave is not ready, and the signal will hang up the host that performs this transmission, and no longer controls the AHB bus. Continue to transmit the remaining data until the slave requests to complete the block transmission. This state lasts for one cycle and jumps to the sec_split state;

The main control module keeps sending Hresp as a block response to the AHB bus in the sec_split state, and Hready is set high to indicate that the slave is ready. This state lasts for one cycle and completes the double-cycle response of the block signal, which is convenient for the host to cancel the remaining Transmit, jump to idle state.

Table 2. Description of jump conditions

Other steps and parameters are the same as those in Embodiment 1.

Specific embodiment three: the difference between this embodiment and specific embodiment one or two is: the input of the register group module is the data, error information, register read enable signal and Rd_FIFO module sent by the AHB bus to the slave. Read data, the output data is the data sent by the slave to the AHB bus and the data to be written sent by the register group module to the Wr_FIFO module; the control information is defined as the error response of the slave, so that the host can make the correct response according to the type of error transmission;

The register group module controls the read and write operations of the register group according to the address signal: when performing a write operation, the address can be used as the enable information of the register group, so that the corresponding register can be written into data; when performing a read operation, the address indicates the register location information , the corresponding register is read out;

The size of the register group is determined according to the transmission requirements of the slave and the specific data bit width. If the AHB bus transmission data bit width is greater than the user module data bit width, the data needs to be divided into user modules when the host writes. The bit width required by the module is then stored in the register group. When the host reads, the data needs to be spliced to form the required bit width of the AHB bus and then stored in the register group; vice versa; the register group should be divided into It is divided into three parts, one part stores AHB bus input data, one part stores AHB bus read data, and one part stores information data.

Other steps and parameters are the same as those in Embodiment 1 or Embodiment 2.

Embodiment 4: This embodiment differs from Embodiment 1 to Embodiment 3 in that the main function of the decoding control module is to decode the read-write request and address information sent by the main control module, and to control the operation of the register group module. data access;

The input of the decoding control module is the read and write request and address information of the main control module, and the output is the read and write address signal of the register group module;

The decoding control module decodes the address information of the main control module, sends read and write address signals to the register group module, and controls the read and write operations of the corresponding registers.

Other steps and parameters are the same as those in Embodiments 1 to 3.

Specific embodiment five: this embodiment is different from one of specific embodiments one to four: the abnormal detection module detects the state of the slave, judges whether the slave meets the transmission requirements, and checks the state of the Rd_FIFO module, the Wr_FIFO module and the AHB bus The read and write signals are monitored to indicate whether the current transmission meets the read and write requirements;

The input of this module is the state of the Rd_FIFO module and Wr_FIFO module, the read and write signals controlled by the AHB bus, and the output is the abnormal state indication signal;

If the Rd_FIFO module and the Wr_FIFO module are both empty when the AHB bus is performing read transmission, or the Wr_FIFO module and the Rd_FIFO module are both full when the AHB bus is performing write transmission, the abnormal detection module detects a transmission error and sends it to the main control module. If the control module receives this signal and it is valid, it will send an error response to the AHB bus and terminate this transmission; if the AHB bus is reading and transmitting, the Rd_FIFO module is empty and the Wr_FIFO module is not empty, or the Wr_FIFO module is full and the Rd_FIFO module is not empty during the write transmission. If it is full, the module indicates block transmission and sends it to the main control module. The main control module sends a block response to the AHB bus and terminates this transmission until the FIFO, that is, the Rd_FIFO module and the Wr_FIFO module The status meets the transmission conditions, and then complete the rest of the transmission. The block transfer is only for the slave with the block transfer capability. If the slave does not have the block transfer capability, this signal is invalid.

Other steps and parameters are the same as in one of the specific embodiments 1 to 4.

Specific embodiment six: this embodiment is different from one of specific embodiments one to five in that: the burst transmission monitoring module records the number of data transmitted in each burst, as a judgment whether the burst is terminated in advance or the burst transmission is completed basis;

The input of the burst transmission monitoring module is a part of the AHB bus control signal (comprising: Htrans, Hready, Hsel), and the output is the result of a burst data volume record;

Hsel is used as the signal to start the module. The module judges whether the new transmission is started by monitoring the type of Htrans. If the type of Htrans is idle or nonseq, it means that the new transmission starts, the last burst transmission ends, and the data is recorded in the next cycle. At the beginning of reappearance, every time the transmitted data should be checked whether Hready is set high, that is, a valid data record is performed only after the slave is ready, and the output result is given to the early termination judgment module and the main control module, and the main control module is based on the signal Send read and write signals to the Wr_FIFO module and Rd_FIFO module. Other steps and parameters are the same as one of the specific embodiments 1 to 5.

Embodiment 7: This embodiment differs from Embodiments 1 to 6 in that: the early termination judging module detects whether the burst transmission is forced to be terminated, and the host loses the possession of the AHB bus before completing the transmission, and the AHB bus exchanges When used by other hosts, according to the judgment result of this module, the slave stops transmitting data or establishes communication with other hosts;

The input of the early termination judgment module is a part of the AHB bus control signal (comprising: Hburst, Htrans) and the output result of the burst transmission monitoring module, and the judgment result of the early termination of the output burst is given to the main control module;

Determine whether the new transmission is enabled according to the type of Htrans, and record the data volume Hburst required by the burst transmission. When the new transmission starts, compare whether the data volume is consistent with the transmission volume recorded by the counting module. If they are consistent, it means that there is no advance Termination, otherwise, it means that the burst transmission is terminated in advance; the main control module judges whether the slave continues to transmit data according to the type of Htrans at this time, if it is terminated in advance and the Htrans type is idle, the slave stops transmitting data and enters the waiting state, if Early termination and the Htrans type is nonseq, the slave continues to communicate with the new master.

Other steps and parameters are the same as one of the specific embodiments 1 to 6.

Embodiment 8: This embodiment is different from one of Embodiments 1 to 7 in that: for a slave with block transfer capability, if the slave is not ready to transmit data, a host and The communication of the slave is told that it needs to transfer in blocks, then the master is suspended and no longer controls the AHB bus; the function of this module is to detect whether the slave has the ability to perform a block transfer on the master, and notify the main control module The host can continue to control the AHB bus by sending a signal requesting to complete the block transfer to the AHB bus;

The input of the block transmission processing module is a part of the AHB bus control signal (comprising: Hmaster, Hwrite), block record signal, Wr_FIFO module and the empty and full signal of the Rd_FIFO module, and the output is a block ready signal to the main control module, If the signal is valid, the main control module sends a response to the AHB bus to request to complete the block transmission; when the master and the slave are in the process of transmitting, if the slave does not meet the transmission conditions, it sends a block response to the master, and the master does not Communicate again, wait for the slave to meet the transmission conditions and send a request to complete the block transmission; the block transmission processing module records the block record signal sent by the main control module, the read and write signal sent by the AHB bus and the host number, and simultaneously detects the Wr_FIFO module and The empty and full signal of the Rd_FIFO module, when the two FIFOs meet the transmission conditions required by the host, send a block ready signal to the main control module. After the main control module receives this signal, the main control module receives this signal at an appropriate time Finally, if the slave is transmitting data at this time, it needs to wait until the end of the transmission, and then send a request to the AHB bus to complete the block transfer response. If the slave is in an idle state, it will directly send a request to the AHB bus to complete the block transfer response. The response lasts for one clock cycle and sends a response to the AHB bus to request the completion of the block transfer, which lasts for one clock cycle.

Other steps and parameters are the same as one of the specific embodiments 1 to 7.

Claims (8)

1. a kind of AHB bus interface system for data flow transmission, it is characterized in that it comprises: Main control module, register group module, decoding control module, anomaly detection module, burst transmission monitoring module, early termination judgment module, block transmission processing module, Rd_FIFO module is read FIFO module and Wr_FIFO module is write FIFO module; Wherein, the main control module sends control signals to each module, coordinates the communication between each module and the communication with the AHB bus; Wherein, the register group module is composed of a series of registers for AHB bus to read and write, and is used to store the data required for AHB bus transmission; Wherein, the decoding control module decodes the read-write request and address information sent by the main control module, and controls the data access of the register group module; Wherein, the abnormal detection module detects the FIFO state, judges whether the slave meets the transmission requirements, monitors the state of the Rd_FIFO module, the Wr_FIFO module and the read and write signals of the AHB bus, and indicates whether the current transmission meets the read and write requirements; Wherein, the burst transmission monitoring module records the number of data of each burst transmission as a basis for judging whether the burst is terminated in advance or the burst transmission is completed; Wherein, the early termination judging module detects whether the burst transmission is forced to be terminated, the host loses the possession of the AHB bus if the transmission is not completed, and when the AHB bus is handed over to other masters for use, according to the judging result of the early termination judging module, the slave stops the transmission data or establish communications with other hosts; Wherein, the block transfer processing module detects whether the slave machine has the ability to perform a block transfer to the master, and notifies the master control module to send a signal requesting to complete the block transfer to the AHB bus, so that the master can continue to control the AHB bus. 2. a kind of AHB bus interface system for data flow transmission according to claim 1, is characterized in that: The input of the main control module is the control signal sent by the AHB bus to the slave and the detection results of each module, and the output is the response of the slave and the control signal of each module; The main control module is in the idle state, waiting for transmission; if the slave is selected for transmission and the transmission type is nonseq and indicates read/write and the slave is ready, then jump to the trans state; if the slave is ready to complete the block For transmission, jump to the hsplit state; if the Rd_FIFO module and the Wr_FIFO module are both empty during the read transmission, or if the Wr_FIFO module and the Rd_FIFO module are both full during the write transmission, then jump to the error state; if the Rd_FIFO module is empty during the read transmission And the Wr_FIFO module is not empty, or the Wr_FIFO module is full and the Rd_FIFO module is not full during the write transmission, then jump to the split state; Described master control module carries out data transmission in trans state, reads and transmits then reads the data in the Rd_FIFO module, and writes and transmits and then writes data in the Wr_FIFO module; If in the process of reading and transmitting, the Rd_FIFO module appears to be empty but the Wr_FIFO module is not Empty, or, during the write transmission process, if the Wr_FIFO module is full and the Rd_FIFO module is not full, then jump to the split state; if the read transmission process shows that both the Rd_FIFO module and the Wr_FIFO module are empty, or, during the write transmission process, If the Wr_FIFO module and the Rd_FIFO module are both full, jump to the error state; if the control signal of a locked transmission is sent, jump to the wait state; if the transmission is completed, the slave is abandoned and the non-locked transmission, then jump Go to the idle state; if the transmission is completed, the slave is abandoned and the slave is ready to complete the block transfer, then jump to the hsplit state; The main control module is in the wait state, waiting for the slave to be ready to complete the data of the last locked transmission; if the slave is ready, then jump to idle; otherwise, continue to wait in the wait; In the hsplit state, the main control module sends a signal Hsplit that completes the block request to the AHB bus, and after only one cycle, it jumps to the idle state; In the error state, the main control module sends Hresp to the AHB bus as an error response, and Hready is set low, that is, the slave is not ready, this state is a cycle, and jumps to the sec_error state; The sec_error state of the main control module keeps sending Hresp to the AHB bus as an error response, but Hready is set high to indicate that the slave is ready. This state lasts for one cycle and completes the double-cycle response of the error signal, which is convenient for the host to cancel the remaining transmission. Go to idle state; In the split state, the main control module sends Hresp to the AHB bus as a block response, and Hready is set low, that is, the slave is not ready, and the signal will hang up the host that performs this transmission, and no longer controls the AHB bus. Continue to transmit the remaining data until the slave requests to complete the block transmission. This state lasts for one cycle and jumps to the sec_split state; The main control module keeps sending Hresp as a block response to the AHB bus in the sec_split state, and Hready is set high to indicate that the slave is ready. This state lasts for one cycle and completes the double-cycle response of the block signal, which is convenient for the host to cancel the remaining Transmit, jump to idle state. 3. a kind of AHB bus interface system for data stream transmission according to claim 1, is characterized in that: The input of the register group module is the data to be read sent by the AHB bus to the slave, error information, register read enable signal and Rd_FIFO module, and the output data is the data and the register group module sent by the slave to the AHB bus The data to be written sent to the Wr_FIFO module; the control information is defined as the error response of the slave, so that the host can make correct transmission according to the type of error; The register group module controls the read and write operations of the register group according to the address signal: when performing a write operation, the address can be used as the enable information of the register group, so that the corresponding register can be written into data; when performing a read operation, the address indicates the register location information , the corresponding register is read out; The size of the register group is determined according to the transmission requirements of the slave and the specific data bit width. If the AHB bus transmission data bit width is greater than the user module circuit data bit width, the data needs to be divided into The bit width required by the user module is then stored in the register group. When the host reads, the data needs to be spliced to form the required bit width of the AHB bus and then stored in the register group; vice versa; the register group should be Divided into three parts, one part stores AHB bus input data, one part stores AHB bus read data, and one part stores information data. 4. a kind of AHB bus interface system for data flow transmission according to claim 1, is characterized in that: The main function of the decoding control module is to decode the read-write request and address information sent by the main control module to control the data access of the register group module; The input of the decoding control module is the read and write request and address information of the main control module, and the output is the read and write address signal of the register group module; The decoding control module decodes the address information of the main control module, sends read and write address signals to the register group module, and controls the read and write operations of the corresponding registers. 5. a kind of AHB bus interface system for data flow transmission according to claim 1, is characterized in that: The abnormal detection module detects the state of the slave, judges whether the slave meets the transmission requirements, and monitors the state of the Rd_FIFO module, the Wr_FIFO module and the read and write signals of the AHB bus to indicate whether the current transmission meets the read and write requirements; The input of this module is the state of the Rd_FIFO module and Wr_FIFO module, the read and write signals controlled by the AHB bus, and the output is the abnormal state indication signal; If the Rd_FIFO module and the Wr_FIFO module are both empty when the AHB bus is performing read transmission, or the Wr_FIFO module and the Rd_FIFO module are both full when the AHB bus is performing write transmission, the abnormal detection module detects a transmission error and sends it to the main control module. If the control module receives this signal and it is valid, it will send an error response to the AHB bus and terminate this transmission; if the AHB bus is reading and transmitting, the Rd_FIFO module is empty and the Wr_FIFO module is not empty, or the Wr_FIFO module is full and the Rd_FIFO module is not empty during the write transmission. If it is full, the module indicates block transmission and sends it to the main control module. The main control module sends a block response to the AHB bus when the signal is valid, and terminates the transmission until the FIFO status meets the transmission conditions. Complete the rest of the transmission, the block transfer is only for the slave with the block transfer capability, if the slave does not have the block transfer capability, this signal is invalid. 6. a kind of AHB bus interface system for data flow transmission according to claim 1, is characterized in that: The burst transmission monitoring module records the number of data transmitted in each burst as a basis for judging whether the burst is terminated in advance or the burst transmission is completed; The input of the burst transmission monitoring module is a part of the AHB bus control signal, and the output is the result of a burst data volume record; Hsel is used as the signal to start the module. The module judges whether the new transmission is started by monitoring the type of Htrans. If the type of Htrans is idle or nonseq, it means that the new transmission starts, the last burst transmission ends, and the data is recorded in the next cycle. At the beginning of reappearance, every time the transmitted data should be checked whether Hready is set high, that is, a valid data record is performed only after the slave is ready, and the output result is given to the early termination judgment module and the main control module, and the main control module is based on the signal Send read and write signals to the Wr_FIFO module and Rd_FIFO module. 7. a kind of AHB bus interface system for data stream transmission according to claim 1, is characterized in that: The early termination judging module detects whether the burst transmission is forced to terminate, and the master loses the possession of the AHB bus before completing the transmission. When the AHB bus is handed over to other masters, according to the judgment result of this module, the slave stops transmitting data or communicates with the AHB bus. Establish communication with other hosts; The input of the early termination judgment module is part of the AHB bus control signal and the output result of the burst transmission monitoring module, and the judgment result of the early termination of the output burst is given to the main control module; Determine whether the new transmission is enabled according to the type of Htrans, and record the data volume Hburst required by the burst transmission. When the new transmission starts, compare whether the data volume is consistent with the transmission volume recorded by the counting module. If they are consistent, it means that there is no advance Termination, otherwise, it means that the burst transmission is terminated in advance; the main control module judges whether the slave continues to transmit data according to the type of Htrans at this time, if it is terminated in advance and the Htrans type is idle, the slave stops transmitting data and enters the waiting state, if Early termination and the Htrans type is nonseq, the slave continues to communicate with the new master. 8. a kind of AHB bus interface system for data flow transmission according to claim 1, is characterized in that: The block transmission processing module has block transfer capability for the slave, if the slave is not ready to transmit data, then the communication between a certain master and the slave is notified that block transmission is required, then the master is suspended, no longer Control the AHB bus; the function of this module is to detect whether the slave has the ability to perform a block transmission on the master, and notify the master control module to send a signal to the AHB bus to complete the block transfer, so that the master can continue to control the AHB bus; The input of the block transmission processing module is part of the AHB bus control signal, the block recording signal, the empty and full signal of the Wr_FIFO module and the Rd_FIFO module, and the output is the block ready signal to the main control module. If the signal is valid, the main control The module sends a request to the AHB bus to complete the block transmission response; when the master and the slave are transmitting, if the slave does not meet the transmission conditions, it will send a block response to the master, and the master will no longer communicate and wait for the slave. After satisfying the transmission conditions, a request is sent to complete the block transmission; the block transmission processing module records the block record signal sent by the main control module, the read and write signal sent by the AHB bus and the host number, and simultaneously detects the empty and full signals of the Wr_FIFO module and the Rd_FIFO module, When the two FIFOs meet the transmission conditions required by the master, they will send a block ready signal to the master control module. After the master control module receives this signal, that is, after the master control module receives this signal at an appropriate time, if the slave In the process of data transmission, you need to wait until the end of the transmission, and send a request to the AHB bus to complete the block transfer response. If the slave is in an idle state, it will directly send a request to the AHB bus to complete the block transfer response. The response lasts for one clock cycle to the AHB The bus issues a response requesting the completion of the block transfer, which lasts for one clock cycle.