CN105630054B - Hysteresis voltage comparator - Google Patents
Hysteresis voltage comparator Download PDFInfo
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- CN105630054B CN105630054B CN201410612343.3A CN201410612343A CN105630054B CN 105630054 B CN105630054 B CN 105630054B CN 201410612343 A CN201410612343 A CN 201410612343A CN 105630054 B CN105630054 B CN 105630054B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 238000010586 diagram Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
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- 102100037224 Noncompact myelin-associated protein Human genes 0.000 description 1
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- 238000001514 detection method Methods 0.000 description 1
- 230000000979 retarding effect Effects 0.000 description 1
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Abstract
The invention discloses a kind of hysteresis voltage comparator, including：First and two PMOSs, two grids are input into a pair of differential signals, drain electrode the first and two load of connection metal-oxide-semiconductor respectively；The electric current of the 3rd PMOS and the load metal-oxide-semiconductor of the first NMOS tube respectively with the first and two is in mirror；The drain electrode of the 3rd PMOS and the first NMOS tube links together and as the first output end；First output end is sequentially connected first and two and CMOS inverter and forms the second output end and the 3rd output end respectively；4th PMOS switch pipe is connected between the drain electrode of the second current source and the first PMOS and grid connects the second output end；5th PMOS switch pipe is connected between the 3rd current source and the drain electrode of the second PMOS and grid connects the 3rd output end.The present invention can realize threshold voltage adjustments using on-off circuit, not only have and utilize integrated, and sluggish width adjusting is convenient, using convenient.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of hysteresis voltage comparator.
Background technology
Voltage comparator can be compared to two level and export high level or low level, so voltage comparator is general
For level detection.Single voltage limit comparator only one of which threshold voltage, then exports more than incoming level more than the threshold voltage
High level, otherwise exports low level.The advantage of this single voltage limit comparator is simple structure, but if the ring of input signal
When having more noise in border, the output of single voltage limit comparator can frequently beat between low and high level, voltage detecting
Problem occurs.As shown in Figure 1A, it is input of the existing single voltage limit comparator when input signal has more noise and defeated
Go out curve；Single voltage limit comparator only one of which threshold V T RP, input signal is superimposed with noise near threshold voltage
Output signal can be made frequently to beat after signal.
In order to eliminate influence of the noise to output signal, prior art is generally required and uses hysteresis voltage comparator, and
Single voltage limit comparator is different, and hysteresis voltage comparator has two threshold voltages, exports from low transition to high level
Threshold voltage with to jump to low level threshold voltage from high level different, the two formed one it is sluggish interval, can avoid making an uproar
The influence of sound.As shown in Figure 1B, it is input and output of the existing hysteresis voltage comparator when input signal has more noise
Curve；It can be seen that threshold V T RP+ is greater than threshold V T RP-, both differences are greater than the excursion of noise,
Therefore the influence of noise can be eliminated.
Existing hysteresis voltage comparator is typically connected by non-essential resistance and to form positive feedback and form two different threshold values
Voltage, be unfavorable for it is integrated, range of application be limited.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of hysteresis voltage comparator, can realize threshold using on-off circuit
Threshold voltage is adjusted, and is not only had and is utilized integrated, and sluggish width adjusting is convenient, using convenient.
In order to solve the above technical problems, the hysteresis voltage comparator that the present invention is provided includes：
The source electrode of the first PMOS and the second PMOS, first PMOS and second PMOS links together
And connected with the first current source；The grid of first PMOS and second PMOS is used as a pair of inputs of differential signal
End.
The drain electrode of first PMOS and the first load metal-oxide-semiconductor connection, the drain electrode of second PMOS and second negative
Carry metal-oxide-semiconductor connection.
The electric current of the 3rd PMOS and the first NMOS tube, the 3rd PMOS and the first load metal-oxide-semiconductor is in mirror image
The electric current of relation, first NMOS tube and the second load metal-oxide-semiconductor is in mirror；The drain electrode of the 3rd PMOS and
The drain electrode of first NMOS tube links together and as the first output end, and the source electrode of the 3rd PMOS connects power supply electricity
Pressure, the source ground of first NMOS tube.
First CMOS inverter and the second CMOS inverter, the input connection described first of first CMOS inverter
Output end, the output end of first CMOS inverter is the second output end；The input connection of second CMOS inverter
Second output end, the output end of second CMOS inverter is the 3rd output end.
4th PMOS switch pipe is connected between the drain electrode of the second current source and first PMOS, the 4th PMOS
The grid of switching tube connects second output end.
5th PMOS switch pipe is connected between the drain electrode of the 3rd current source and second PMOS, the 5th PMOS
The grid of switching tube connects the 3rd output end.
The 4th PMOS switch pipe is opened when first output end exports high level and increases by first load
The electric current of metal-oxide-semiconductor simultaneously forms positive feedback structure, and the first load metal-oxide-semiconductor is input to by adjusting the 4th PMOS switch pipe
In electric current regulation hysteresis voltage comparator output voltage by step-down high first threshold voltage.
The 5th PMOS switch pipe is opened when first output end exports low level and increases by second load
The electric current of metal-oxide-semiconductor simultaneously forms positive feedback structure, and the second load metal-oxide-semiconductor is input to by adjusting the 5th PMOS switch pipe
In electric current adjust the output voltage of the hysteresis voltage comparator by the low second threshold voltage for uprising.
Further improvement is that the first load metal-oxide-semiconductor includes the second NMOS tube, the 3rd NMOS tube and the 6th PMOS
Pipe；The drain electrode of second NMOS tube and the drain electrode of first PMOS are connected, the source ground of second NMOS tube；Institute
The grid for stating the 3rd NMOS tube connects grid and the drain electrode of second NMOS tube, the source ground of the 3rd NMOS tube；Institute
The drain and gate for stating the 6th PMOS connects the drain electrode of the 3rd NMOS tube and the grid of the 3rd PMOS, described
The source electrode of the 6th PMOS connects supply voltage.
Further improvement be, the second load metal-oxide-semiconductor includes the 4th NMOS tube, the grid of the 4th NMOS tube and
The drain electrode of drain electrode connection second PMOS and the grid of first NMOS tube, the source electrode of the 4th NMOS tube connect
Ground.
Further improvement is that second current source and the 3rd current source are using same current source.
It is defeated that the present invention is input to corresponding difference by output signal control MOS switch pipe and by MOS switch management and control system
Enter the load current size of transistor, positive feedback can be formed and adjust hysteresis voltage comparator output voltage change two
Threshold voltage size, and can easily condition sluggishness width, the present invention need not using resistance but use on-off circuit with regard to energy
Threshold voltage adjustments are realized, is not only had and is utilized integrated, and sluggish width adjusting is convenient, using convenient and low cost.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Figure 1A is input and curve of output of the existing single voltage limit comparator when input signal has more noise；
Figure 1B is input and curve of output of the existing hysteresis voltage comparator when input signal has more noise；
Fig. 2 is embodiment of the present invention hysteresis voltage comparator circuit diagram；
Fig. 3 is present pre-ferred embodiments hysteresis voltage comparator circuit diagram；
Input and output simulation curve when Fig. 4 A are present pre-ferred embodiments removal switch-mode regulation threshold voltages；
Fig. 4 B are input and the output simulation curve of present pre-ferred embodiments.
Specific embodiment
As shown in Fig. 2 being embodiment of the present invention hysteresis voltage comparator circuit diagram；Embodiment of the present invention hysteresis voltage compares
Device includes：
The source of the first PMOS MP1 and the second PMOS MP2, the first PMOS MP1 and the second PMOS MP2
Pole links together and is connected with the first current source I1；The grid of the first PMOS MP1 and the second PMOS MP2 is made
It is a pair of inputs of differential signal Vinn and Vinp.
The drain electrode of the first PMOS MP1 and first load metal-oxide-semiconductor 1 connect, the drain electrode of the second PMOS MP2 and
Second load metal-oxide-semiconductor 2 is connected.
3rd PMOS MP3 and the first NMOS tube MN1, the 3rd PMOS MP3 and described first load metal-oxide-semiconductor 1
Electric current is in mirror, and the electric current that the first NMOS tube MN1 and described second loads metal-oxide-semiconductor 2 is in mirror；Described 3rd
The drain electrode of PMOS MP3 and the drain electrode of the first NMOS tube MN1 link together and as the first output end vo ut1, described
The source electrode of the 3rd PMOS MP3 meets supply voltage VDD, the source ground GND of the first NMOS tube MN1.
First CMOS inverter 3 and the second CMOS inverter 4, the input connection of first CMOS inverter 3 are described
First output end vo ut1, the output end of first CMOS inverter 3 is the second output end vo ut2；2nd CMOS is anti-phase
The input of device 4 connects the second output end vo ut2, and the output end of second CMOS inverter 4 is the 3rd output end
Vout3。
4th PMOS switch pipe MP4 is connected between the drain electrode of the second current source I2 and the first PMOS MP1, described
The grid of the 4th PMOS switch pipe MP4 connects the second output end vo ut2.
5th PMOS switch pipe MP5 is connected between the drain electrode of the 3rd current source I2 and the second PMOS MP2, described
The grid of the 5th PMOS switch pipe MP5 connects the 3rd output end vo ut3.Second current source I2 described in the embodiment of the present invention
Same current source is used with the 3rd current source I2.
The 4th PMOS switch pipe MP4 is opened when the first output end vo ut1 exports high level and is increased described
The electric current of the first load metal-oxide-semiconductor 1 simultaneously forms positive feedback structure, namely can mirror image after the electric current increase of the first load metal-oxide-semiconductor 1
To the 3rd PMOS MP3 and increase the electric current of the 3rd PMOS MP3, make the first output end vo ut1 more
Easily reach or remain high level, form the relation of a positive feedback；It is input to by adjusting the 4th PMOS switch pipe MP4
Electric current in the first load metal-oxide-semiconductor 1 adjusts the output voltage of hysteresis voltage comparator by the first threshold voltage of step-down high,
In the embodiment of the present invention, the electric current in the first load metal-oxide-semiconductor 1 is increased more, and first threshold voltage can be smaller.
The 5th PMOS switch pipe MP5 is opened when the first output end vo ut1 exports low level and is increased described
The electric current of the second load metal-oxide-semiconductor 2 simultaneously forms positive feedback structure, namely can mirror image after the electric current increase of the second load metal-oxide-semiconductor 2
To the first NMOS tube MN1 and increase the electric current of the first NMOS tube MN1, make the first output end vo ut1 more
Easily reach or remain low level, form the relation of a positive feedback；It is input to by adjusting the 5th PMOS switch pipe MP5
Electric current in the second load metal-oxide-semiconductor 2 adjusts the output voltage of the hysteresis voltage comparator by the low Second Threshold for uprising
Voltage；In the embodiment of the present invention, the electric current in the second load metal-oxide-semiconductor 2 is increased more, and second threshold voltage can be bigger.
As shown in figure 3, being present pre-ferred embodiments hysteresis voltage comparator circuit diagram；It is real in the present invention shown in Fig. 2
Apply on the basis of example, present pre-ferred embodiments have done following improvement：
The first load metal-oxide-semiconductor 1 includes the second NMOS tube MN2, the 3rd NMOS tube MN3 and the 6th PMOS MP6；It is described
The drain electrode of the second NMOS tube MN2 and the drain electrode of the first PMOS MP1 are connected, the source ground of the second NMOS tube MN2
GND；The grid of the 3rd NMOS tube MN3 connects grid and the drain electrode of the second NMOS tube MN2, the 3rd NMOS tube
The source ground GND of MN3；The drain and gate of the 6th PMOS MP6 connect the 3rd NMOS tube MN3 drain electrode and
The grid of the 3rd PMOS MP3, the source electrode of the 6th PMOS MP6 meets supply voltage VDD.
The second load metal-oxide-semiconductor 2 includes the 4th NMOS tube, the grid of the 4th NMOS tube and drain electrode connection described the
The drain electrode of two PMOS MP2 and the grid of the first NMOS tube MN1, the source ground GND of the 4th NMOS tube.
The first current source I1 is formed by current source I3 by PMOS MP7 and MP8 mirror image, the second current source I2
Formed by PMOS MP7 and MP9 mirror image by current source I3.
First CMOS inverter 3 is connected and formed by PMOS MP10 and NMOS tube MN5；Second CMOS inverter
4 are connected and are formed by PMOS MP11 and NMOS tube MN6.
As shown in Figure 4 A, the input and output emulation when being present pre-ferred embodiments removal switch-mode regulation threshold voltage are bent
Line；The drain electrode of i.e. described 4th PMOS MP4 is not connected to the drain electrode of the first PMOS MP1 and the 5th PMOS
Input and curve of output when the drain electrode of MP5 is not connected to the drain electrode of the second PMOS MP2, input signal Vinn keep not
Become, input signal Vinp is initially from low toward from past sinking high, output signal Vout3 is in input signal Vinp from low after promotion
During toward promotion during arrival threshold V T RP from low transition to high level, output signal Vout3 is in input signal
Vinp jumps to low level during arrival threshold V T RP toward during sinking from high from high level, the threshold value electricity shown in Fig. 4 A
Pressure VTRP is 1.5V.
As shown in Figure 4 B, it is input and the output simulation curve of present pre-ferred embodiments.Input signal Vinn keeps not
Become, input signal Vinp is initially from low toward from past sinking high, output signal Vout3 is in input signal Vinp from low after promotion
During toward promotion during arrival second threshold voltage VTRP+ from low transition to high level, output signal Vout3 believes in input
Number Vinp jumps to low level during arrival first threshold voltage VTRP- toward during sinking from high from high level, it can be seen that the
Two threshold V T RP+ are more than 1.5V, and first threshold voltage VTRP- is less than 1.5V, second threshold voltage VTRP+ and first threshold
A retarding window is formd between voltage VTRP-.
The present invention has been described in detail above by specific embodiment, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (2)
1. a kind of hysteresis voltage comparator, it is characterised in that including：
The source electrode of the first PMOS and the second PMOS, first PMOS and second PMOS link together and and
First current source is connected；The grid of first PMOS and second PMOS is used as a pair of inputs of differential signal；
The drain electrode of first PMOS and the first load metal-oxide-semiconductor connection, the drain electrode of second PMOS and the second load MOS
Pipe is connected；
The electric current of the 3rd PMOS and the first NMOS tube, the 3rd PMOS and the first load metal-oxide-semiconductor is in mirror,
The electric current of first NMOS tube and the second load metal-oxide-semiconductor is in mirror；The drain electrode of the 3rd PMOS and described
The drain electrode of the first NMOS tube links together and as the first output end, and the source electrode of the 3rd PMOS connects supply voltage, institute
State the source ground of the first NMOS tube；
First CMOS inverter and the second CMOS inverter, input connection first output of first CMOS inverter
End, the output end of first CMOS inverter is the second output end；The input connection of second CMOS inverter is described
Second output end, the output end of second CMOS inverter is the 3rd output end；
4th PMOS switch pipe is connected between the drain electrode of the second current source and first PMOS, the 4th PMOS switch
The grid of pipe connects second output end；
5th PMOS switch pipe is connected between the drain electrode of the 3rd current source and second PMOS, the 5th PMOS switch
The grid of pipe connects the 3rd output end；
The 4th PMOS switch pipe is opened when first output end exports high level and increases the first load metal-oxide-semiconductor
Electric current and form positive feedback structure, by adjust the 4th PMOS switch pipe be input to it is described first load metal-oxide-semiconductor in
Electric current adjusts the output voltage of hysteresis voltage comparator by the first threshold voltage of step-down high；
The 5th PMOS switch pipe is opened when first output end exports low level and increases the second load metal-oxide-semiconductor
Electric current and form positive feedback structure, by adjust the 5th PMOS switch pipe be input to it is described second load metal-oxide-semiconductor in
Electric current adjusts the output voltage of the hysteresis voltage comparator by the low second threshold voltage for uprising；
The first load metal-oxide-semiconductor includes the second NMOS tube, the 3rd NMOS tube and the 6th PMOS；The leakage of second NMOS tube
The drain electrode connection of pole and first PMOS, the source ground of second NMOS tube；
The grid of the 3rd NMOS tube connects grid and the drain electrode of second NMOS tube, and the source electrode of the 3rd NMOS tube connects
Ground；
The drain and gate of the 6th PMOS connects the drain electrode of the 3rd NMOS tube and the grid of the 3rd PMOS
Pole, the source electrode of the 6th PMOS connects supply voltage；
The second load metal-oxide-semiconductor includes the 4th NMOS tube, the grid of the 4th NMOS tube and drain electrode connection described second
The drain electrode of PMOS and the grid of first NMOS tube, the source ground of the 4th NMOS tube.
2. hysteresis voltage comparator as claimed in claim 1, it is characterised in that：Second current source and the 3rd electric current
Source is using same current source.
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| CN201410612343.3A CN105630054B (en) | 2014-11-04 | 2014-11-04 | Hysteresis voltage comparator |
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| CN201410612343.3A CN105630054B (en) | 2014-11-04 | 2014-11-04 | Hysteresis voltage comparator |
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| CN105630054B true CN105630054B (en) | 2017-06-06 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107196629B (en) * | 2017-05-04 | 2020-10-23 | 深圳大学 | A Discrete Threshold Voltage Comparator with Zero Static Power |
| CN108649934A (en) * | 2018-05-31 | 2018-10-12 | 成都锐成芯微科技股份有限公司 | A kind of hysteresis comparator circuit |
| CN110233612B (en) * | 2019-07-09 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | A single-input current-mode hysteretic comparator |
| CN110824230A (en) * | 2019-11-27 | 2020-02-21 | 珠海复旦创新研究院 | A hysteresis signal detection circuit |
| CN116886091B (en) * | 2023-06-28 | 2024-06-07 | 江苏帝奥微电子股份有限公司 | Logic threshold judging circuit and judging method thereof |
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| CN1949668A (en) * | 2006-10-25 | 2007-04-18 | 华中科技大学 | Retarding comparator circuit of single terminal input |
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| CN102025352A (en) * | 2010-11-08 | 2011-04-20 | 中国兵器工业集团第二一四研究所苏州研发中心 | Hysteresis voltage comparator |
| US20120049892A1 (en) * | 2010-08-26 | 2012-03-01 | Kabushiki Kaisha Toshiba | Hysteresis comparator |
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- 2014-11-04 CN CN201410612343.3A patent/CN105630054B/en active Active
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| JP2005101696A (en) * | 2003-09-22 | 2005-04-14 | Sharp Corp | Hysteresis comparator circuit |
| CN1949668A (en) * | 2006-10-25 | 2007-04-18 | 华中科技大学 | Retarding comparator circuit of single terminal input |
| CN201018463Y (en) * | 2006-11-24 | 2008-02-06 | 华中科技大学 | Single Sided Hysteretic Comparator |
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