CN105630698A - Extension cache configuration method and device and extension cache - Google Patents

Abstract

The invention discloses a method and device for configuring an extended cache, and relates to the field of information technology, which can reduce the time delay for accessing data in the extended cache. The method includes: firstly, the extended cache receives a write identification command, the write identification command carries an identification of a storage access address, then stores the identification of the storage access address, and finally compares the identification of the storage access address with each stored identification to obtain Determine if the memory fetch address hits. The present invention is suitable for caching part of the data in the internal memory.

Description

Method and device for configuring extended cache and extended cache

technical field

The invention relates to the field of information technology, in particular to a method and device for configuring an extended cache and an extended cache.

Background technique

Cache refers to a high-speed small-capacity memory between the CPU (Central Processing Unit, central processing unit) and the memory, which can cache part of the data stored in the memory, and when the CPU needs to access these data, directly provide these data to the CPU, so as to Solve the problem of mismatching transfer speed between CPU and memory. Since the transmission speed between the cache and the memory does not match, in order to further improve the system performance, an extended cache can be added between the cache and the memory to solve the problem of the transmission speed mismatch between the cache and the memory.

Generally, the process of accessing the extended cache is as follows: first, the row decoder in the extended cache receives the ACTIVATE (activation) command initiated by the memory controller, and decodes the row address according to the ACTIVATE command, so that the extended cache Select the row corresponding to the data to be accessed, and write it into the row cache; then the column decoder receives the read (READ) command or write (WRITE) command initiated by the memory controller, and according to the read command or write command The column address is decoded to select the column corresponding to the data to be accessed in the row cache, and read or write it to the bus.

At present, a method for configuring an extended cache is to configure M DATA (data) data blocks and N TAG (identification) data blocks for each line of the extended cache, the DATA data blocks are used to store data, and the TAG data blocks are used to store The identifier corresponding to the data in the DATA data. When accessing the extended cache, first read N TAG data blocks in the row cache, and then compare the identification of the data to be accessed with each identification in the N TAG data blocks, so as to realize the correspondence between the selected data to be accessed column.

However, when the extended cache is configured in the above manner, before each access to the extended cache, it is necessary to read N TAG data blocks used to store each identifier in the row cache, resulting in the data in the extended cache The access delay is large.

Contents of the invention

The invention provides a method and device for configuring an extended cache and the extended cache, which can reduce the time delay for accessing data in the extended cache.

The technical scheme adopted in the present invention is:

In a first aspect, the present invention provides a method for configuring an extended cache, which is applied to a storage system. The storage system includes a cache, a memory, and an extended cache. The extended cache communicates with the cache, and the extended cache communicates with the cache. Communication between the memories, the extended cache is used to cache data stored in the memory, and provide the data to the cache; the method includes:

The extended cache receives a write identification command, and the write identification command carries an identification of a memory access address, and the memory access address is an address corresponding to a space storing data to be accessed;

The extended cache stores the identifier of the access address;

The extended cache compares the identifier of the memory access address with each stored identifier to determine whether the memory access address is a hit.

With reference to the first aspect, in a first possible implementation manner of the first aspect, the extended cache includes at least one identification TAG data block and at least one data DATA data block, and the at least one TAG data block is used to store the For each identifier, the at least one DATA data block is used to store data corresponding to each identifier.

With reference to the first possible implementation of the first aspect, in a second possible implementation of the first aspect, the extended cache stores the identifier of the access address, specifically including:

If there is a reserved space in the at least one TAG data block, the extended cache stores the identifier of the access address in the reserved space of the at least one TAG data block; or,

If there is no reserved space in the at least one TAG data block, the extended cache stores the identifier of the access address in any one of the at least one DATA data block.

With reference to the first possible implementation of the first aspect, or the second possible implementation of the first aspect, in a third possible implementation of the first aspect, the extended cache includes a comparison circuit, and the The comparison circuit is composed of a preset number of comparison modules, the preset number is the same as the number of tags stored in the at least one tag TAG data block;

The extended cache compares the identifier of the memory access address with each stored identifier, specifically including:

The extended cache uses the preset number of comparing modules to simultaneously compare the identifier of the memory access address with the respective identifiers.

In combination with the first aspect or the first possible implementation of the first aspect, or the second possible implementation of the first aspect, or the third possible implementation of the first aspect, in the fourth possible implementation of the first aspect In a possible implementation manner, after the extended cache compares the identifier of the memory access address with each stored identifier, it further includes:

If there is an identifier identical to the identifier of the memory access address among the respective identifiers, the extended cache determines that the memory access address hits; or,

If there is no identifier identical to the identifier of the memory access address among the respective identifiers, the extended cache determines that the memory access address is a miss.

With reference to the fourth possible implementation of the first aspect, in the fifth possible implementation of the first aspect, after the extended cache determines that the memory access address hits, it further includes:

The extended cache encodes the same identifier as the identifier of the memory access address, so that the DATA data block corresponding to the memory access address is determined in at least one DATA data block.

In a second aspect, the present invention provides a device for configuring an extended cache, which is used in an extended cache. The extended cache is located in a storage system, and the storage system also includes a cache and a memory. Communication, communication between the extended cache and the memory, the extended cache is used to cache data stored in the memory, and provide the data to the cache; the device includes:

The receiving unit is configured to receive a write identification command, the write identification command carries an identification of a memory access address, and the memory access address is an address corresponding to a space storing data to be accessed;

a storage unit, configured to store the identifier of the memory access address received by the receiving unit;

A comparing unit, configured to compare the identifier of the memory access address stored by the storage unit with each stored identifier, so as to determine whether the memory access address is a hit.

In combination with the second aspect, in the first possible implementation of the second aspect,

The extended cache includes at least one identification TAG data block and at least one data DATA data block, the at least one TAG data block is used to store the respective identifications, and the at least one DATA data block is used to store the respective identifications corresponding to The data.

In combination with the first possible implementation of the second aspect, in the second possible implementation of the second aspect,

The storage unit is specifically configured to store the identifier of the access address in the reserved space of the at least one TAG data block when there is a reserved space in the at least one TAG data block; or,

The storage unit is specifically configured to store the identifier of the access address in any one of the at least one DATA data block when there is no reserved space in the at least one TAG data block.

With reference to the first possible implementation of the second aspect, or the second possible implementation of the second aspect, in a third possible implementation of the second aspect, the extended cache includes a comparison circuit, and the The comparison circuit is composed of a preset number of comparison modules, the preset number is the same as the number of tags stored in the at least one tag TAG data block;

The comparison unit is specifically configured to simultaneously compare the identifier of the memory access address with the respective identifiers through the preset number of comparison modules.

In combination with the second aspect or the first possible implementation of the second aspect, or the second possible implementation of the second aspect, or the third possible implementation of the second aspect, in the fourth possible implementation of the second aspect In a possible implementation manner, the device further includes: a determining unit;

The determining unit is configured to determine that the memory access address hits when the comparison result of the comparison unit is that there is an identifier identical to the identifier of the memory access address among the respective identifiers; or,

The determining unit is configured to determine that the memory access address is a miss when the comparison result of the comparison unit is that there is no identifier identical to the identifier of the memory access address among the respective identifiers.

With reference to the fourth possible implementation manner of the second aspect, in a fifth possible implementation manner of the second aspect, the device further includes: a coding unit;

The encoding unit is configured to encode the identifier identical to the identifier of the access address after the determining unit determines that the access address hits, so that the identifier is determined in at least one DATA data block. The DATA data block corresponding to the access address.

In a third aspect, the present invention provides an extended cache, the extended cache is located in a storage system, the storage system further includes a cache and a memory, the extended cache communicates with the cache, and the extended cache communicates with the cache The memory communicates, and the extended cache is used to cache data stored in the memory and provide the data to the cache; the extended cache includes:

The receiver is configured to receive a write identification command, where the write identification command carries an identification of a memory access address, and the memory access address is an address corresponding to a space storing data to be accessed;

a memory, configured to store the identifier of the access address received by the receiver;

A processor, configured to compare the identifier of the memory access address stored in the memory with each stored identifier, so as to determine whether the memory access address is a hit.

In combination with the third aspect, in the first possible implementation of the third aspect,

The extended cache includes at least one identification TAG data block and at least one data DATA data block, the at least one TAG data block is used to store the respective identifications, and the at least one DATA data block is used to store the respective identifications corresponding to The data.

In combination with the first possible implementation of the third aspect, in the second possible implementation of the third aspect,

The memory is specifically configured to store the identifier of the access address in the reserved space of the at least one TAG data block when there is a reserved space in the at least one TAG data block; or,

The memory is specifically configured to store the identifier of the access address in any one of the at least one DATA data block when there is no reserved space in the at least one TAG data block.

With reference to the first possible implementation of the third aspect, or the second possible implementation of the third aspect, in a third possible implementation of the third aspect, the extended cache includes a comparison circuit, and the The comparison circuit is composed of a preset number of comparison modules, the preset number is the same as the number of tags stored in the at least one tag TAG data block;

The processor is specifically configured to simultaneously compare the identifier of the memory access address with the respective identifiers through the preset number of comparison modules.

In combination with the third aspect or the first possible implementation of the third aspect, or the second possible implementation of the third aspect, or the third possible implementation of the third aspect, in the fourth Among the possible implementations,

The processor is further configured to determine that the memory access address hits when there is an identifier that is the same as the identifier of the memory access address among the respective identifiers; or,

The processor is further configured to determine that the memory access address is a miss when there is no identifier identical to the identifier of the memory access address among the respective identifiers.

In combination with the fourth possible implementation of the third aspect, in the fifth possible implementation of the third aspect,

The processor is further configured to encode the same identifier as the identifier of the memory access address, so that the DATA data block corresponding to the memory access address is determined in at least one DATA data block.

The method, device, and extended cache configuration provided by the present invention are applied to a storage system. The storage system includes a cache, a memory, and an extended cache. The extended cache is between the cache and the memory. The extended cache is used to cache data in the memory, and Provide the data to the cache; the extended cache first receives the write identification command, which carries the identification of the memory access address, then stores the identification of the memory access address, and finally compares the identification of the memory access address with the stored identifications, To determine whether the fetch address is hit. Compared with currently reading out the TAG data block used to store each identifier to determine whether the memory access address is hit, the present invention writes the identifier corresponding to the memory access address into the extended cache, and stores the memory access in the extended cache. The identifier of the address is compared with each identifier stored to determine whether the memory access address is a hit, and the smaller time for writing the identifier corresponding to the memory access address into the extended cache can be used to replace the larger one for storing each identifier. The time when the TAG data block is read from the extended cache, thereby avoiding the delay caused by reading the TAG data block; and, since the comparison is performed inside the extended cache, the extended cache can directly read the data to be accessed according to the comparison result, Therefore, the time for the extended cache to read the data to be accessed to the bus can be reduced, thereby reducing the time delay for accessing the data in the extended cache.

Description of drawings

In order to more clearly illustrate the present invention or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the present invention or the prior art will be briefly introduced below. Obviously, the accompanying drawings in the following description are only the present invention. For some embodiments of the present invention, those skilled in the art can also obtain other drawings according to these drawings without paying creative efforts.

FIG. 1 is a schematic diagram of a storage system in an embodiment of the present invention;

FIG. 2 is a schematic diagram of another storage system in an embodiment of the present invention;

FIG. 3 is a flowchart of a method for configuring an extended cache in an embodiment of the present invention;

FIG. 4 is a flow chart of another method for configuring an extended cache in an embodiment of the present invention;

FIG. 5 is a schematic diagram of lines of an extended cache in an embodiment of the present invention;

FIG. 6 is a schematic diagram of a line cache in an extended cache in an embodiment of the present invention;

FIG. 7 is a schematic diagram of time delay for reading data in the prior art;

FIG. 8 is a schematic diagram of a time delay for reading data in an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a device for configuring an extended cache in an embodiment of the present invention;

FIG. 10 is a schematic structural diagram of another device for configuring an extended cache in an embodiment of the present invention;

FIG. 11 is a schematic structural diagram of an extended cache in an embodiment of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The technical solution provided by the embodiment of the present invention can be applied to a storage system. As shown in FIG. 1, the storage system includes a cache, a memory, and an extended cache. The extended cache is used to cache data stored in memory and provide data to the cache. Specifically, as shown in FIG. 2 , the cache may specifically be a level 1 cache, level 2 cache, and level 3 cache, and the extended cache may specifically be a level 4 cache or level 5 cache between the level 3 cache and the internal memory. Specifically, the cache can be SRAM (Static Random Access Memory, static random access memory), and the extended cache can be specifically eDRAM (embedded Dynamic Random Access Memory, embedded dynamic random access memory), or 3D stacked DRAM (Die-stacked DRAM).

An embodiment of the present invention provides a method for configuring an extended cache, which can reduce the time delay for accessing data in the extended cache. As shown in FIG. 3 , the method includes:

301. The extended cache receives a write identification command.

Wherein, the write identification command carries the identification of the memory access address, and the memory access address is an address corresponding to the space storing the data to be accessed. In this embodiment of the present invention, the write tag command may specifically be referred to by WRITE_TAG.

For the embodiment of the present invention, the above step 301 is that the row decoder in the extended cache receives the ACTIVATE command initiated by the memory controller, decodes the row address according to the ACTIVATE command, and writes the row corresponding to the memory access address into Executed after the line cache.

302. The extended cache stores the identifier of the memory access address.

Wherein, the identifier of the memory access address refers to the identifier of the storage address of the data to be accessed.

For the embodiment of the present invention, the extended cache stores the memory access address in the line currently cached by the line cache.

303. The extended cache compares the identifier of the memory access address with each stored identifier.

Further, the identifier of the memory access address is compared with each stored identifier through the extended cache to determine whether the memory access address is a hit.

For the embodiment of the present invention, if there is an identifier identical to the identifier of the memory access address in each identifier stored in the line cache of the extended cache, the extended cache determines that the memory access address hits the line of the current cache of the line cache; if the extended cache If there is no identifier identical to the identifier of the memory access address among the identifiers stored in the row cache, the extended cache determines that the memory access address is a miss in the current cache line of the row cache.

The method for configuring the extended cache provided by the embodiment of the present invention is applied to a storage system. The storage system includes a cache, a memory, and an extended cache. The extended cache is between the cache and the memory. The extended cache is used to cache data in the memory, and provides to the cache; the extended cache first receives the write identification command, the write identification command carries the identification of the memory access address, then stores the identification of the memory access address, and finally compares the identification of the memory access address with each stored identification to determine the access Whether the storage address is hit. Compared with currently reading out the TAG data block used to store each identifier to determine whether the memory access address is hit, the embodiment of the present invention writes the identifier corresponding to the memory access address into the extended cache, and stores the The identifier of the memory access address is compared with each of the stored identifiers to determine whether the memory access address is a hit, and the smaller time for writing the identifier corresponding to the memory access address into the extended cache can be used to replace the larger time for storing each identifier. The time when the identified TAG data block is read from the extended cache, so that the time delay caused by reading the TAG data block can be avoided; and, since the comparison is performed inside the extended cache, the extended cache can directly read out the data to be accessed according to the comparison result. data, so that the time for the extended cache to read the data to be accessed to the bus can be reduced, thereby reducing the time delay for accessing the data in the extended cache.

As a specific description of the method shown in FIG. 3 , an embodiment of the present invention provides another method for configuring an extended cache, as shown in FIG. 4 , the method includes:

401. The extended cache receives a write identification command.

Wherein, the write identification command carries the identification of the memory access address, and the memory access address is the address corresponding to the space storing the data to be accessed. The write flag command carries the flag of the memory access address. In this embodiment of the present invention, the write tag command may specifically be referred to by WRITE_TAG.

For the embodiment of the present invention, the above step 401 is that the row decoder in the extended cache receives the ACTIVATE command initiated by the memory controller, decodes the row address according to the ACTIVATE command, and writes the row corresponding to the memory access address into Executed after the line cache.

402. The extended cache stores the identifier of the memory access address.

Optionally, before step 402, the method may further include: the extended cache determines whether there is reserved space in at least one TAG data block. As an alternative to step 402: if there is reserved space in at least one TAG data block, then the extended cache stores the identifier of the memory access address in the reserved space of at least one TAG data block; or, if there is no reserved space in at least one TAG data block If there is reserved space, the extended cache stores the identifier of the memory access address in any one of the at least one DATA data block.

For this embodiment of the present invention, the extended cache includes at least one TAG data block and at least one DATA data block. Wherein, at least one TAG data block is used to store each identifier, and at least one DATA data block is used to store data corresponding to each identifier.

For example, if the line size of the cache is 64B (bytes), and the line size of the extended cache is 2KB, each line of the extended cache can be divided into 32 64B, that is, each line of the extended cache can be composed of 32 64B composed of data blocks. As shown in Figure 5, among the 32 data blocks, 29 data blocks can store data, that is, 29 DATA data blocks, and the other 3 data blocks can store the identifiers of these 29 DATA data blocks, that is, 3 TAG data piece.

For example, if each line of the extended cache can be composed of 32 64B data blocks, including 29 DATA data blocks and 3 TAG data blocks, that is, the space that can be used to store tags is 192B, and each DATA The identifiers of data blocks all occupy 6B, that is, the identifiers of 29 DATA data blocks occupy 174B, then there is a reserved space of 18B in the TAG identifier of the extended cache, and further, the extended cache can be in the reserved space of 18B The identifier of the memory access address is stored, and the identifier of the memory access address occupies 6B.

For the embodiment of the present invention, the extended cache may specifically store the identification of the memory access address in the last 6B of the reserved space of 18B, so as to facilitate the reading of the memory access address.

For another example, if each line of the extended cache can be composed of 35 64B data blocks, including 32 DATA data blocks and 3 TAG data blocks, that is, the space that can be used to store tags is 192B, and each The identifiers of DATA data blocks all occupy 6B, that is, the identifiers of 32 DATA data blocks occupy 192B, then there is no reserved space in the TAG identifier of the extended cache, and further, the extended cache can be stored in these 32 DATA data blocks Select any DATA data block, the DATA data block no longer stores data, and store the identifier of the memory access address in the DATA data block.

It should be noted that the above manner of judging whether there is reserved space in at least one TAG data block can only be performed when the extended cache is initially configured.

403. The extended cache uses a preset number of comparison modules to simultaneously compare the identifier of the memory access address with each identifier.

Further, by expanding the cache, the identifier of the memory access address is compared with each identifier at the same time, so as to determine whether the memory access address is a hit.

Optionally, the extended cache includes a comparison circuit, and the comparison circuit is composed of a preset number of comparison modules, and the preset number is the same as the number of tags stored in at least one tag TAG data block.

For the embodiment of the present invention, by expanding the cache and comparing the identification of the access address with each identification at the same time, the identification and identification of the access address can be completed within the time of comparing the access address with a certain identification in each address. The comparison of each identifier can reduce the time for comparing the identifier of the memory access address with each identifier, and further, can reduce the time delay of accessing the data in the extended cache.

For the embodiment of the present invention, a comparison circuit may be added in the extended cache to realize the comparison between the identifier of the memory access address and each identifier in the extended cache. Wherein, the comparison circuit may be composed of N comparison modules, where N is the number of tags stored in the TAG data block. In the embodiment of the present invention, through the comparison circuit composed of N comparison modules, the extended cache can be realized and the identifier of the memory access address can be compared with each identifier at the same time.

404a. If there is an identifier identical to the identifier of the memory access address among the identifiers, the extended cache determines that the memory access address hits.

In step 405a after step 404a, the extended cache encodes the same identifier as that of the access address.

Further, the identifier identical to the identifier of the memory access address is encoded by the extended cache, so that the DATA data block corresponding to the memory access address can be determined in at least one DATA data block.

For the embodiment of the present invention, an encoding circuit may be added in the extended cache, so as to encode the same identifier as the identifier of the memory access address in the extended cache. In the embodiment of the present invention, the encoding circuit is composed of a preset number of encoding modules, the preset number is the same as the number of identifications in the TAG data block, wherein each encoding module can be used for a certain identification and memory access address IDs for comparison.

For example, as shown in Figure 6, it is a schematic diagram of the line cache of the extended cache. The line cache is composed of 32 data blocks of 64B, including 29 DATA data blocks and 3 TAG data blocks, and is stored in the reserved space of the TAG data block. The identification of the memory access address also includes a comparison circuit and an encoding circuit in the row cache, and the comparison circuit is composed of 29 comparison modules.

In step 404b parallel to step 404a, if there is no identifier identical to the identifier of the memory access address among the identifiers, the extended cache determines that the memory access address is a miss.

For the embodiment of the present invention, by storing the identifier of the access address in the extended cache, the time for reading each identifier in the TAG data block from the extended cache can be avoided; at the same time, by directly comparing the comparison results inside the extended cache Avoiding it can reduce the time to read the hit data to the bus.

For example, as shown in Figure 7, when the cache is configured in the way of the prior art, assuming that the line corresponding to the data to be accessed has been selected in the extended cache and read into the line cache of the extended cache, it will take 53 cycles (clock cycles) To finish reading the column corresponding to the data to be accessed in the row cache. Among them, as shown in Figure 7, the delay of 53 cycles specifically includes: it takes 18 cycles to select 3 TAG data blocks in the line cache, 12 cycles to read these 3 TAG data blocks from the line cache to the bus, and 12 cycles for 3 TAG data It takes 1 cycle to compare each identifier in the block with the identifier of the access address, 18 cycles to select the corresponding DATA data block in the row cache according to the comparison result, and 4 cycles to read the selected DATA data block from the row cache to the bus.

For another example as shown in FIG. 8, when the cache is configured in the manner provided by the embodiment of the present invention, assuming that the line corresponding to the data to be accessed has been selected in the extended cache and read into the line cache of the extended cache, 34 cycles ( clock cycle) to finish reading the column corresponding to the data to be accessed in the row cache. Among them, as shown in Figure 8, the delay of 34cycles specifically includes: it takes 18cycles to select 3 TAG data blocks in the line cache, 1cycle is required to write the identification of the memory access address into the line cache, and it takes 1cycle for each of the 3 TAG data blocks It takes 1 cycle to compare the identifier with the identifier of the access address, 10 cycles to select the corresponding DATA data block in the row cache according to the comparison result, and 4 cycles to read the selected DATA data block from the row cache to the bus.

For the embodiment of the present invention, according to the above description of Fig. 7 and Fig. 8, the difference between configuring the cache in the way of the prior art and configuring the cache in the way provided by the embodiment of the present invention is: on the one hand, through the embodiment of the present invention When configuring the cache in the provided method, there is no need to read the time delay required to read the 3 TAG data blocks from the row cache to the bus, and only need to write the identifier of the access address into the row cache, thus reducing the time spent in the row cache. The time delay required to read the DATA data block; on the other hand, when configuring the cache through the method provided by the existing technology, the identification is compared outside the extended cache, and after the comparison is completed, the comparison result needs to be transferred to the extended cache to select Corresponding DATA data blocks, when configuring the cache through the method provided by the embodiment of the present invention, the identifiers are compared inside the line cache of the extended cache, and after the comparison is completed, the corresponding DATA data blocks can be selected in the line cache directly according to the comparison result Therefore, when the cache is configured in the manner provided by the embodiment of the present invention, the time delay required to select the corresponding DATA data block in the line cache according to the comparison result is small, and further, the time required for reading the DATA data block in the line cache can be reduced. the required delay.

The method for configuring the extended cache provided by the embodiment of the present invention is applied to a storage system. The storage system includes a cache, a memory, and an extended cache. The extended cache is between the cache and the memory. The extended cache is used to cache data in the memory, and provides to the cache; the extended cache first receives the write identification command, the write identification command carries the identification of the memory access address, then stores the identification of the memory access address, and finally compares the identification of the memory access address with each stored identification to determine the access Whether the storage address is hit. Compared with currently reading out the TAG data block used to store each identifier to determine whether the memory access address is hit, the embodiment of the present invention writes the identifier corresponding to the memory access address into the extended cache, and stores the The identifier of the memory access address is compared with each of the stored identifiers to determine whether the memory access address is a hit, and the smaller time for writing the identifier corresponding to the memory access address into the extended cache can be used to replace the larger time for storing each identifier. The time when the identified TAG data block is read from the extended cache, so that the time delay caused by reading the TAG data block can be avoided; and, since the comparison is performed inside the extended cache, the extended cache can directly read out the data to be accessed according to the comparison result. data, so that the time for the extended cache to read the data to be accessed to the bus can be reduced, thereby reducing the time delay for accessing the data in the extended cache.

Further, as an implementation of the methods shown in FIG. 3 and FIG. 4 , an embodiment of the present invention also provides a device for configuring an extended cache. The device can be used in an extended cache. The extended cache is located in a storage system, and the storage system also includes Cache and memory, communication between the extended cache and the cache, communication between the extended cache and the memory, the extended cache is used to cache data stored in the memory, and provide the data to the cache; the device is used to reduce the impact on the extended cache As for the time delay of data access, as shown in FIG. 9 , the device includes: a receiving unit 91 , a storage unit 92 , and a comparing unit 93 .

The receiving unit 91 is configured to receive a write identification command.

Wherein, the write identification command carries the identification of the memory access address, and the memory access address is an address corresponding to the space storing the data to be accessed.

The storage unit 92 is configured to store the identification of the memory access address received by the receiving unit 91 .

The comparison unit 93 is configured to compare the identifier of the memory access address stored in the storage unit 92 with each of the stored identifiers, so as to determine whether the memory access address is a hit.

Optionally, the extended cache includes at least one identification TAG data block and at least one data DATA data block, at least one TAG data block is used to store each identification, and at least one DATA data block is used to store data corresponding to each identification.

The storage unit 92 is specifically configured to store the identifier of the access address in the reserved space of at least one TAG data block when there is reserved space in at least one TAG data block. or,

The storage unit 92 is specifically configured to store the identifier of the memory access address in any one of the at least one DATA data block when there is no reserved space in the at least one TAG data block.

Optionally, the extended cache includes a comparison circuit, and the comparison circuit is composed of a preset number of comparison modules, and the preset number is the same as the number of tags stored in at least one tag TAG data block.

The comparison unit 93 is specifically configured to simultaneously compare the identifier of the access address with each identifier through a preset number of comparison modules.

Further, as shown in FIG. 10 , the device further includes: a determining unit 101 .

The determining unit 101 is configured to determine that the memory access address hits when the comparison result of the comparison unit 93 is that there is an identifier identical to the identifier of the memory access address among the respective identifiers. or,

The determination unit 101 is configured to determine that the memory access address is a miss when the comparison result of the comparison unit 93 is that there is no identifier identical to the identifier of the memory access address among the respective identifiers.

Optionally, the apparatus further includes: an encoding unit 102 .

The coding unit 102 is configured to encode the same identifier as the identifier of the memory access address after the determining unit 101 determines that the memory access address is hit.

Further, by encoding the same identifier as the identifier of the memory access address, the DATA data block corresponding to the memory access address is determined in at least one DATA data block.

The device for configuring the extended cache provided by the embodiment of the present invention is used in the extended cache. The extended cache is located in the storage system. The storage system also includes a cache and a memory. The extended cache is located between the cache and the memory. The extended cache is used to cache memory. data, and provide the data to the cache; the extended cache first receives the write identification command, which carries the identification of the memory access address, then stores the identification of the memory access address, and finally combines the identification of the memory access address with the stored identification A comparison is made to determine whether the fetch address is a hit. Compared with currently reading out the TAG data block used to store each identifier to determine whether the memory access address is hit, the embodiment of the present invention writes the identifier corresponding to the memory access address into the extended cache, and stores the The identifier of the memory access address is compared with each of the stored identifiers to determine whether the memory access address is a hit, and the smaller time for writing the identifier corresponding to the memory access address into the extended cache can be used to replace the larger time for storing each identifier. The time when the identified TAG data block is read from the extended cache, so that the time delay caused by reading the TAG data block can be avoided; and, since the comparison is performed inside the extended cache, the extended cache can directly read out the data to be accessed according to the comparison result. data, so that the time for the extended cache to read the data to be accessed to the bus can be reduced, thereby reducing the time delay for accessing the data in the extended cache.

It should be noted that for other corresponding descriptions corresponding to each unit in the device for configuring an extended cache provided in the embodiment of the present invention, reference may be made to the corresponding descriptions in FIG. 3 and FIG. 4 , and details are not repeated here.

Furthermore, the embodiment of the present invention also provides an extended cache. The extended cache is located in the storage system. The storage system also includes a cache and a memory. The extended cache communicates with the cache, and the extended cache communicates with the memory. The extended cache Used to cache data stored in memory and provide data to the cache; as shown in Figure 11, the extended cache includes: a receiver 111, a memory 112, a processor 113, a transmitter 114, the transmitter 114 and The processor 113 is connected.

The receiver 111 is configured to receive a write mark command.

Wherein, the write identification command carries the identification of the memory access address, and the memory access address is an address corresponding to the space storing the data to be accessed.

The memory 112 is configured to store the identification of the memory access address received by the receiver 111 .

The processor 113 is configured to compare the identifier of the memory access address stored in the memory 112 with each stored identifier, so as to determine whether the memory access address is hit.

Optionally, the extended cache includes at least one identification TAG data block and at least one data DATA data block, at least one TAG data block is used to store each identification, and at least one DATA data block is used to store data corresponding to each identification.

The memory 112 is specifically configured to store an identifier of a memory access address in the reserved space of at least one TAG data block when there is reserved space in at least one TAG data block. or,

The memory 112 is specifically configured to store an identifier of a memory access address in any one of the at least one DATA data block when there is no reserved space in at least one TAG data block.

Optionally, the extended cache includes a comparison circuit, and the comparison circuit is composed of a preset number of comparison modules, and the preset number is the same as the number of tags stored in at least one tag TAG data block.

The processor 113, the extended cache includes a comparison circuit, the comparison circuit is composed of a preset number of comparison modules, the preset number is the same as the number of tags stored in at least one tag TAG data block.

The processor 113 is further configured to determine that the memory access address hits when there is an identifier identical to the identifier of the memory access address among the respective identifiers. or,

The processor 113 is further configured to determine that the memory access address misses when there is no identifier identical to the memory access address identifier among the respective identifiers.

The processor 113 is further configured to encode the same identifier as the identifier of the memory access address, so that the DATA data block corresponding to the memory access address is determined in at least one DATA data block.

In the extended cache provided by the embodiment of the present invention, the extended cache is located in a storage system, the storage system also includes a cache and a memory, the extended cache is located between the cache and the memory, and the extended cache is used to cache data in the memory and provide the data to the cache; The extended cache first receives the write identification command, which carries the identification of the memory access address, then stores the identification of the memory access address, and finally compares the identification of the memory access address with each stored identification to determine whether the access address is hit. Compared with currently reading out the TAG data block used to store each identifier to determine whether the memory access address is hit, the embodiment of the present invention writes the identifier corresponding to the memory access address into the extended cache, and stores the The identifier of the memory access address is compared with each identifier stored to determine whether the memory access address is a hit, which can avoid the process of reading the TAG data block used to store each identifier from the extended cache, thereby avoiding the process of reading the TAG data The delay caused by the block, which in turn can reduce the delay of accessing the data in the extended cache.

It should be noted that, for other corresponding descriptions corresponding to each device in the extended cache provided in the embodiment of the present invention, reference may be made to the corresponding descriptions in FIG. 3 or FIG. 4 , and details are not repeated here.

The device for configuring an extended cache and the extended cache provided by the embodiments of the present invention can implement the method embodiments provided above. For specific function realization, please refer to the descriptions in the method embodiments, which will not be repeated here. The method and device for configuring an extended cache and the extended cache provided by the embodiments of the present invention may be applicable to cache part of data in a memory, but are not limited thereto.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented through computer programs to instruct related hardware, and the programs can be stored in a computer-readable storage medium. During execution, it may include the processes of the embodiments of the above-mentioned methods. Wherein, the storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM) or a random access memory (Random Access Memory, RAM) and the like.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (18)

1. A method for configuring an extended cache is applied to a storage system, and is characterized in that the storage system comprises a cache, a memory and an extended cache, wherein the extended cache is communicated with the cache, the extended cache is communicated with the memory, and the extended cache is used for caching data stored in the memory and providing the data to the cache; the method comprises the following steps:

the extended cache receives a write identification command, wherein the write identification command carries an identification of a memory access address, and the memory access address is an address corresponding to a space for storing data to be accessed;

the extended cache stores the identification of the access address;

and the extended cache compares the identification of the access address with each stored identification to determine whether the access address is hit.

2. The method according to claim 1, wherein the extended cache comprises at least one TAG DATA block and at least one DATA block, the at least one TAG DATA block is used for storing the respective identifiers, and the at least one DATA block is used for storing DATA corresponding to the respective identifiers.

3. The method according to claim 2, wherein the step of storing the identifier of the access address in the extended cache includes:

if a reserved space exists in the at least one TAG data block, the expansion cache is stored in the reserved space of the at least one TAG data block, and the identification of the memory access address is stored; or,

and if the reserved space does not exist in the at least one TAG DATA block, the expansion is cached in any one DATA DATA block in the at least one DATA DATA block, and the identification of the access address is stored.

4. A method according to claim 2 or 3, wherein said extended cache comprises a comparison circuit, said comparison circuit consisting of a preset number of comparison modules, said preset number being the same as the number of TAGs stored in said at least one TAG data block;

the extended cache compares the identifier of the access address with each stored identifier, and specifically includes:

and the extended cache compares the identification of the memory access address with each identification at the same time through the comparison modules with preset numbers.

5. The method for configuring the extended cache according to any one of claims 1 to 4, wherein after the extended cache compares the identifier of the access address with the stored identifiers, the method further comprises:

if the identification which is the same as the identification of the access address exists in the identifications, the extended cache determines that the access address hits; or,

and if the identifier which is the same as the identifier of the access address does not exist in the identifiers, the extended cache determines that the access address is not hit.

6. The method of claim 5, wherein after the extended cache determines that the access address hits, the method further comprises:

the extended cache encodes the identifier which is the same as the identifier of the memory access address, so that the DATA block corresponding to the memory access address is determined in at least one DATA block.

7. A device for configuring an extended cache is used for the extended cache, the extended cache is located in a storage system, and the storage system is characterized by further comprising a cache and a memory, wherein the extended cache is communicated with the cache and the memory, and the extended cache is used for caching data stored in the memory and providing the data to the cache; the device comprises:

the device comprises a receiving unit, a storage unit and a processing unit, wherein the receiving unit is used for receiving a write identification command, and the write identification command carries an identification of a memory access address, and the memory access address is an address corresponding to a space for storing data to be accessed;

the storage unit is used for storing the identification of the memory access address received by the receiving unit;

and the comparison unit is used for comparing the identification of the memory access address stored in the storage unit with each stored identification to determine whether the memory access address is hit or not.

8. The apparatus for configuring an extended cache of claim 7,

the extended cache comprises at least one TAG DATA block and at least one DATA block, wherein the at least one TAG DATA block is used for storing each TAG, and the at least one DATA block is used for storing DATA corresponding to each TAG.

9. The apparatus for configuring an extended cache of claim 8,

the storage unit is specifically configured to store an identifier of the memory access address in a reserved space of the at least one TAG data block when the reserved space exists in the at least one TAG data block; or,

the storage unit is specifically configured to store, in any one DATA block of the at least one DATA block, an identifier of the memory access address when no reserved space exists in the at least one TAG DATA block.

10. The apparatus according to claim 8 or 9, wherein the extended cache comprises a comparison circuit, the comparison circuit is composed of a preset number of comparison modules, the preset number is the same as the number of TAGs stored in the at least one TAG data block;

the comparing unit is specifically configured to compare the identifier of the memory access address with each identifier simultaneously through the preset number of comparing modules.

11. The apparatus for configuring extended cache according to any one of claims 7 to 10, wherein the apparatus further comprises: a determination unit;

the determining unit is used for determining that the memory access address hits when the comparison result of the comparing unit shows that the identification which is the same as the identification of the memory access address exists in the identifications; or,

and the determining unit is used for determining that the memory access address is not hit when the comparison result of the comparing unit shows that the identifier which is the same as the identifier of the memory access address does not exist in the identifiers.

12. The apparatus for configuring an extended cache of claim 11, wherein the apparatus further comprises: an encoding unit;

the encoding unit is used for encoding the identifier which is the same as the identifier of the memory access address after the determining unit determines that the memory access address hits, so that a DATA block corresponding to the memory access address is determined in at least one DATA block.

13. An extended cache, the extended cache is located in a storage system, and the storage system is characterized by further comprising a cache and a memory, wherein the extended cache is in communication with the cache and the memory, and is used for caching data stored in the memory and providing the data to the cache; the extended cache includes:

the device comprises a receiver and a memory access control unit, wherein the receiver is used for receiving a write identification command, the write identification command carries an identification of a memory access address, and the memory access address is an address corresponding to a space for storing data to be accessed;

a memory for storing an identification of the memory address received by the receiver;

and the processor is used for comparing the identification of the memory access address stored in the memory with each stored identification to determine whether the memory access address is hit.

14. The extended cache of claim 13,

the extended cache comprises at least one TAG DATA block and at least one DATA block, wherein the at least one TAG DATA block is used for storing each TAG, and the at least one DATA block is used for storing DATA corresponding to each TAG.

15. The extended cache of claim 14,

the memory is specifically configured to store an identifier of the memory access address in a reserved space of the at least one TAG data block when the reserved space exists in the at least one TAG data block; or,

the memory is specifically configured to store an identifier of the memory address in any one DATA block of the at least one DATA block when no reserved space exists in the at least one TAG DATA block.

16. The extended cache of claim 14 or 15, comprising a comparison circuit, wherein the comparison circuit is comprised of a preset number of comparison modules, wherein the preset number is the same as the number of TAGs stored in the at least one TAG data block;

the processor is specifically configured to compare the identifier of the memory access address with each identifier simultaneously through the preset number of comparison modules.

17. The extended cache of any one of claims 13 to 16,

the processor is further configured to determine that the memory access address hits when the identifier that is the same as the identifier of the memory access address exists in the identifiers; or,

and the processor is further used for determining that the memory access address is not hit when the identifier which is the same as the identifier of the memory access address does not exist in the identifiers.

18. The extended cache of claim 17,

the processor is further used for encoding the identifier which is the same as the identifier of the memory access address, so that the DATA block corresponding to the memory access address is determined in at least one DATA block.