CN105632886B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN105632886B CN105632886B CN201410598410.0A CN201410598410A CN105632886B CN 105632886 B CN105632886 B CN 105632886B CN 201410598410 A CN201410598410 A CN 201410598410A CN 105632886 B CN105632886 B CN 105632886B
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Abstract
A kind of forming method of semiconductor structure, including：Substrate is provided, forms dielectric layer in substrate；Hard mask layer is formed on dielectric layer；Being formed on hard mask layer has the first photoresist layer of the first opening；Curing process is carried out to the first photoresist layer；Silanization treatment is carried out to the surface of the first photoresist layer, silanization layer is formed on the first photoresist layer surface；Form the filled layer of covering silanization layer；The second photoresist layer with first through hole is formed on filled layer；Filled layer is etched along first through hole, the second through-hole is formed in the filled layer in the first opening；Along hard mask layer and dielectric layer described in first through hole and the second via etch, third through-hole is formed；Second photoresist layer and filled layer are removed, the surface of silanization layer is exposed；Third opening is formed in hard mask layer；The dielectric layer is etched along third opening, forms the 4th opening in the dielectric layer.The method of the present invention simplifies the technological process of photoetching and etching, improves technology stability.
Description
Technical field
The present invention relates to field of semiconductor fabrication, more particularly to a kind of forming method of semiconductor structure.
Background technology
In semiconductor integrated circuit, the signal transmission between semiconductor devices needs highdensity metal interconnecting wires, so
And the big resistance and parasitic capacitance that these metal interconnecting wires are brought have become limitation RC (resistance capacitance)
Delay continues the principal element reduced.
In traditional semiconductor technology, metallic aluminium is typically used for the metal interconnecting wires between semiconductor devices, with
The development of semiconductor technology, part is substituted metal aluminum interconnecting by metal copper interconnecting line, this is because compared with aluminium, copper
With smaller resistance value, RC retardation ratio can be reduced using metal copper interconnecting line；On the other hand, low dielectric constant insulating material by with
The main component for making the dielectric layer between metal layer reduces the parasitic capacitance between metal layer, in practical applications, Wo Menyi
As low dielectric constant insulating material is known as low k dielectric.The damascene structure formed using Damascus technics is extensive
In semiconductor structure applied to production line back end (back end of line, BEOL).RC in order to reduce integrated circuit prolongs
Late, the RC performances for improving integrated circuit, with the development of semiconductor technology, dielectric layer material in damascene structure is from oxidation
Silicon replaces with a kind of low k (dielectric constant) dielectric material, and replaces with ultra low k dielectric materials from low k dielectric.
There are many production methods of existing damascene structure, and common method has：1. all-pass hole precedence method (full via
first)；2. partial through holes precedence method (partial via first)；3. full groove-priority method (full trench first)；
4. part of trench precedence method (partial trench first)；5. self aligned approach (self-alignment method).Below
With regard to the production method of one of which damascene structure --- partial through holes precedence method makees general description, and the production method includes：
Referring to FIG. 1, providing substrate 101, underlying metal interconnection structure 103 is formed in the substrate 101；In the base
Dielectric layer 102 is formed on bottom 101；Hard mask layer 104 is formed on the dielectric layer 102；It is formed on the hard mask layer 104
First photoresist layer 105 has the opening for exposing 104 surface of hard mask layer in first photoresist layer 105；
With reference to figure 2, it is mask with first photoresist layer 105, etches the hard mask layer 104, in hard mask layer 104
It is middle to form the first opening 106 for exposing 102 surface of dielectric layer.
With reference to figure 3, first photoresist layer (with reference to figure 2) is removed, forms the second light for covering the hard mask layer 104
Photoresist layer 107, and second photoresist layer 107 filling, 106 (with reference to figures 2) of full first opening, described first is open in 106
There is the first through hole 108 for exposing 102 surface of dielectric layer in second photoresist layer 107.
It is mask with second photoresist layer 107 with reference to figure 4, the dielectric layer 102 is etched along first through hole 108,
The second through-hole 109 is formed in the dielectric layer 102.
With reference to figure 5, second photoresist layer 107 (with reference to figure 4) is removed.
It is mask with the mask layer 104 with reference to figure 6, the dielectric layer 102 is etched along the first opening, in dielectric layer 102
It is middle to form the second opening 110, and the dielectric layer of 109 bottom of the second through-hole is etched simultaneously so that the second through-hole 109 exposes bottom
103 surface of underlying metal interconnection structure.
With reference to figure 7, the full metal of filling, forms metal in second opening 110 and the second through-hole 109 (with reference to figure 6)
Plug 111.
The formation process stability of existing damascene structure is still to be improved.
Invention content
Problems solved by the invention is how to improve the stability of Damascus technics.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided, in institute
It states and forms dielectric layer in substrate；Hard mask layer is formed on the dielectric layer；The first photoresist is formed on the hard mask layer
Layer, it is formed with the first opening in first photoresist layer；To the surface of first photoresist layer for being formed with the first opening
Silanization treatment is carried out, converts the Other substrate materials on the first photoresist layer surface to silanization layer；It is formed and covers the silane
Change the filled layer of layer and full first opening of filling；The second photoresist layer, second photoresist layer are formed on the filled layer
Middle formation first through hole, the first through hole are located at the first overthe openings；The in first opening is etched along first through hole
Two anti-reflecting layers and filled layer, first opening in filled layer in form the second through-hole；It is carved along first through hole and the second through-hole
First anti-reflecting layer, hard mask layer and dielectric layer are lost, third through-hole is formed in the hard mask layer and dielectric layer；Removal
Second photoresist layer and filled layer, expose the surface of silanization layer；The hard mask layer is etched along the first opening, hard
Third opening is formed in mask layer；Using the hard mask layer as mask, the dielectric layer is etched along third opening, in the dielectric layer
The 4th opening is formed, the 4th opening mutually runs through with third through-hole.
Optionally, the first photoresist layer material is negative photoresist or positive photoetching rubber.
Optionally, when the first photoresist layer material is positive photoetching rubber, carrying out, silanization treatment is front and back, further includes
Step, to be formed with the first opening the first photoresist layer carry out curing process, the curing process be UV photo-irradiation treatments or
Heat treatment.
Optionally, the temperature of the heat treatment is 100~250 degrees Celsius, and the time is 0.5~10 minute.
Optionally, there is resin, the resin includes hydroxyl functional group, carboxylic acid group in the first photoresist layer material
Functional group, amido functional group or mercapto functional group, when carrying out silanization treatment, the photoetching glue material on the surface of the first photoresist layer
The protium in functional group in material is substituted by silylation, forms silanization layer.
Optionally, the reactant that the silanization treatment uses is hexamethyldisilazane, tetramethyl-disilazane, double two
Methyaminomethyl silane dimethyl silicon substrate dimethylamine, dimethyl silicon substrate diethylamine, trimethylsilyl dimethylamine, trimethyl silane
Base diethylamine or dimethylamino pentamethyl disilane.
Optionally, when carrying out silanization treatment, the reactant feeds reaction chamber, silanization treatment in gaseous form
Temperature be 100~160 degrees Celsius, the time be 0.5~10 minute.
Optionally, the silanization layer includes oxygen element, element silicon, carbon and protium.
Optionally, the material of the filled layer is organic matter.
Optionally, carbon and protium content are more than 90% in the organic matter, and element silicon is free of in organic matter.
Optionally, the formation process of the filled layer is spin coating proceeding.
Optionally, the thickness of the filled layer is 100nm-300nm, and the thickness of the first photoresist layer is 50nm-150nm.
Optionally, further include：Before forming the first photoresist layer, the first anti-reflective coating is formed on the hard mask layer
Layer；Before forming the second photoresist layer, the second siliceous anti-reflection coating is formed on the filled layer.
Optionally, the first opening is formed in the first photoresist layer by exposed and developed technique.
Optionally, the exposed and developed technique, curing process and silanization treatment technique are in photoetching equipment
Middle progress.
Optionally, the dielectric layer material is low-K dielectric constant material.
Optionally, the hard mask layer is single-layer or multi-layer stacked structure.
Optionally, it is formed with underlying metal interconnection structure in the substrate.
Optionally, the bottom-exposed of third through-hole goes out the surface of underlying metal interconnection structure.
Optionally, further include：Metal is filled in the 4th opening and third through-hole, Damascus metal is formed and mutually links
Structure, Damascus metal interconnection structure are electrically connected with underlying metal interconnection structure.
Compared with prior art, technical scheme of the present invention has the following advantages：
The forming method of semiconductor structure forms the first photoresist layer, first photoresist on the hard mask layer
The first opening for exposing hard mask layer surface is formed in layer；The surface of first photoresist layer is carried out at silanization
Reason converts the Other substrate materials on the first photoresist layer surface to silanization layer, the property of silanization layer and the first photoresist layer
Property it is different, the hardness and density of silanization layer are more than the hardness and density of the first photoresist layer, silanization layer protection first
Photoresist layer will not be damaged, thus after formation silanization layer, hard mask layer can not directly be performed etching, in hard mask layer
The step of carrying out third opening, but carry out forming filled layer on silanization layer, the second photoresist layer is formed on filled layer,
The step of the second through-hole being formed in the second photoresist layer, thus in the present invention, it is described hard before forming the second photoresist layer
Mask layer is to maintain complete (there is no openings in hard mask layer), when being exposed technique to the second photoresist layer, exposure
The focal plane detecting step and alignment mark detection step carried out before technique will not be by the shadow of the imperfect state of hard mask layer
It rings, to improve the precision of focal plane detecting step and alignment mark detection step so that formed in the second photoresist layer
The precision of first through hole improves, in addition, the first photoresist layer can synchronize removal when etch media layer forms the 4th opening, because
First photoresist layer is removed without additional etch step, it is therefore prevented that the damage of dielectric layer in technical process.
Further, the photoetching glue victim layer material include hydroxyl functional group, carboxylic acid group's functional group, amido functional group or
Mercapto functional group, the protium in functional group in the photoetching glue victim layer material of part are substituted by silylation, thus can be compared with
The property of change photoetching glue victim layer surface portion material for convenience, by the side wall of photoetching glue victim layer and top section photoetching
Glue material is converted into silanization layer.
Further, it is formed before the second photoresist layer, is formed and cover filling out for full first opening of the silanization layer and filling
Fill layer so that with flat carrier surface when being subsequently formed the second photoresist layer so that the second photoresist layer of formation has
Higher thickness evenness.
Description of the drawings
Fig. 1~Fig. 7 is the cross-sectional view of prior art Damascus forming process；
Fig. 8~Figure 19 is the cross-sectional view of the forming process of semiconductor structure of the embodiment of the present invention.
Specific implementation mode
As described in the background art, the formation process stability of existing damascene structure is still to be improved.
The study found that having two step photoetching processes in the forming process of the damascene structure of the prior art, it is for the first time
The first photoresist layer is formed, then using the first photoresist layer as hard mask layer described in mask etching, forms in hard mask layer
One opening, second is the second photoresist layer of formation, then using the second photoresist layer as dielectric layer described in mask etching, in medium
The second through-hole is formed in layer.It after forming the first opening in hard mask layer, needs to remove the first photoresist layer, is removing the first light
During photoresist layer, it is easy that the dielectric layer of bottom is caused to damage, when especially dielectric layer is low-K dielectric constant material, this
Kind damage is particularly evident, further study show that, referring to FIG. 3, after forming the first opening in hard mask layer 104, then exist
The second photoresist layer 107 is formed, when being exposed technique to the second photoresist layer 107 (technique for forming first through hole 108),
Hard mask layer with the first opening can have an impact the precision of exposure technology, concrete reason：To the second photoresist layer 107
Before being exposed, need to carry out focal plane detecting step and alignment mark detection step, focal plane detecting step to be light source pair
Semiconductor substrate 101 is illuminated, and then judges whether the focal plane of semiconductor substrate 101 is good by receiving detection light, right
Fiducial mark remembers that detecting step is illuminated by the alignment mark in light source semiconductor substrate 101, then by receiving to fiducial mark
Alignment mark is identified in the reflected light or diffraction light of note, is carrying out focal plane detecting step and alignment mark detection step
When, since hard mask layer 104 is not complete (there are the first openings), the irradiation light of light source transmitting is through after hard mask layer 104
With the intensity of the different location after the first opening be different (reflectance factors of hard mask material layer and the second Other substrate materials and
Absorptivity is different), there is also differences in the light intensity for being radiated at semiconductor substrate back reflection for the different light of intensity, or
There is also differences in the intensity of irradiation alignment mark back reflection or the light of diffraction for the different light of intensity, thus focal plane is examined
The precision for surveying step and alignment mark detection step is affected so that focal plane detecting step and alignment mark detection step
Afterwards, the precision that step is exposed to the second photoresist layer is affected, the essence of the second through-hole formed in the second photoresist layer
Degree is restricted.
The present invention provides a kind of forming methods of semiconductor structure can not directly be carved after forming silanization layer
The step of losing hard mask layer, third opening carried out in hard mask layer, but carry out forming filled layer on silanization layer, it is filling out
The step of filling on layer and form the second photoresist layer, the second through-hole is formed in the second photoresist layer, thus in the present invention, formed
Before second photoresist layer, the hard mask layer is to maintain complete (there is no thirds to be open in hard mask layer), to second
When photoresist layer is exposed technique, focal plane detecting step and alignment mark detection step in exposure technology will not be by hard
The influence of the imperfect state of mask layer, to improve the precision of focal plane detecting step and alignment mark detection step so that
The precision of the first through hole formed in second photoresist layer improves, in addition, the first photoresist layer can be formed in etch media layer
Removal is synchronized when the 4th opening, because removing first photoresist layer without additional etch step, it is therefore prevented that technical process
In damage to dielectric layer.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, should not limit the scope of the invention herein.In addition, in reality
In making should include length, width and depth three-dimensional space.
Fig. 8~Figure 19 is the cross-sectional view of the forming process of semiconductor structure of the embodiment of the present invention.
With reference to figure 8, substrate 200 is provided, forms dielectric layer 203 in the substrate 200；The shape on the dielectric layer 203
At hard mask layer 204.
The substrate 200 includes semiconductor substrate 201 and the underlying dielectric layer 202 in semiconductor substrate 201, described
It is formed with semiconductor devices, such as transistor etc. in semiconductor substrate 201, bottom gold is formed in the underlying dielectric layer 202
Belong to interconnection structure 205, the underlying metal interconnection structure 205 can be electrically connected with the semiconductor devices in semiconductor substrate 201.
Material silicon (Si), germanium (Ge) or SiGe (GeSi), the silicon carbide (SiC) of the semiconductor substrate 201；It can also
It is silicon-on-insulator (SOI), germanium on insulator (GOI), the semiconductor devices can pass through existing MOS techniques or CMOS works
Skill is formed in semiconductor substrate 201.
The metal interconnection structure 205 can be metal plug or metal interconnecting wires or including metal plug and with gold
Belong to plug and connects metal interconnecting wires.
The underlying dielectric layer 202 can be single-layer or multi-layer (>=2 layers) stacked structure, 202 material of the underlying dielectric layer
Material is silica or low K (K≤3.5) dielectric constant material.
In other embodiments of the invention, the substrate can be the substrate of other structures, for example substrate can be to be situated between
Material bed of material etc..
Damascus metal interconnection structure is subsequently formed in the dielectric layer 203.In order to reduce posting between interconnection structure
Raw capacitance, in the present embodiment, the dielectric layer material is low K (K≤3.5) dielectric constant material, in a specific embodiment,
203 material of dielectric layer is SiCOH, and the thickness of dielectric layer is 2000~3000 angstroms.
The mask when hard mask layer 204 is as subsequent etching dielectric layer, the hard mask layer 204 can be single layer or
Multilayer (>=2 layers) stacked structure.
In the present embodiment, the hard mask layer 204 is three level stack structure, includes the first oxygen on dielectric layer 203
SiClx layer 21, the titanium nitride layer 22 on 21 surface of the first silicon oxide layer, the second silica on titanium nitride layer surface
Layer 23.Buffer layer of first silicon oxide layer 21 as dielectric layer 203 and titanium nitride layer 22, and can be used as and subsequently cover firmly
Stop-layer when third opening is formed in film layer, second silicon oxide layer 23 is as the first photoresist layer and nitrogen being subsequently formed
Change the buffer layer between titanium layer 22, hard mask layer 204 includes titanium nitride layer 22, when subsequent etching dielectric layer 203, improves Jie
The etching selection ratio of matter layer material and hard mask material layer
With reference to figure 9, the first photoresist layer 225 is formed on the hard mask layer 204.
First photoresist layer 225 is formed using spin coating proceeding, and the thickness of the first photoresist layer 225 is 50nm-
150nm。
Further include that the first bottom anti-reflective is formed on the hard mask layer 204 before forming the first photoresist layer 225
Coating, reflection of first bottom antireflective coating for reducing bottom light when being exposed to the first photoresist layer.
There is resin, the resin includes hydroxyl functional group, carboxylic acid group's function in first photoresist layer, 225 material
Group, amido functional group or mercapto functional group, when subsequently carrying out silanization treatment, protium is by silylation in the functional group
It substitutes, forms silanization layer, to realize the change to the property of 225 surfacing of the first photoresist layer.
First photoresist layer, 225 material can be negative photoresist or positive photoetching rubber.In this implementation, due to positive photoetching rubber
High resolution in the resolution ratio of stock photoresist, the precision for the figure that positive photoetching rubber is formed is higher than the figure that negative photoresist is formed
Precision, in the present embodiment, the material of first photoresist layer 225 is positive photoetching rubber, to form the higher Damascus of precision
Structure.
With reference to figure 10, the first opening for exposing 204 surface of hard mask layer is formed in first photoresist layer 225
210。
The first opening 210, first opening are formed in first photoresist layer 225 by exposed and developed technique
210 are located at the top of underlying metal interconnection structure 205.
In the present embodiment, the material of first photoresist layer 225 is positive photoetching rubber, the shape in the first photoresist layer 225
After the first opening 210, further include：Curing process is carried out to forming the first photoresist layer 225 after opening 210, to increase by the
The hardness and consistency of one photoresist layer 225, prevent the filled layer being subsequently formed and sovent diffusion in the second photoresist layer and
Dissolve part the first photoresist layer material.
In other embodiments of the invention, it if the material of first photoresist layer 225 is negative photoresist layer, is not necessarily to
Carry out curing process step.
The curing process is UV photo-irradiation treatments or heat treatment, when carrying out curing process, the first photoresist layer material hair
Raw cross-linking reaction so that the first photoresist layer cures.
The UV irradiations can be irradiated by the UV light sources in exposure device.
The heat treatment can be carried out by the thermal processing chamber in gluing or developing apparatus, and the temperature of the heat treatment is
100~250 degrees Celsius, the time is 0.5~10 minute.
With reference to figure 11, silanization treatment 31 is carried out to the surface of the first photoresist layer 225 after the curing process, will be consolidated
The Other substrate materials for changing treated 225 surface of the first photoresist layer are converted into silanization layer 206.
When carrying out silanization treatment 31, the functional group in the Other substrate materials on the surface of the first photoresist layer 225 is by silane
Base substitutes, and forms silanization layer.
The reactant that the silanization treatment 31 uses is hexamethyldisilazane, tetramethyl-disilazane, double diformazan ammonia
Butyldimethylsilyl, dimethyl silicon substrate dimethylamine, dimethyl silicon substrate diethylamine, trimethylsilyl dimethylamine, trimethylsilyl
Diethylamine or dimethylamino pentamethyl disilane.
In one embodiment, when carrying out silanization treatment, the reactant feeds reaction chamber, silane in gaseous form
The temperature for changing processing is 100~160 degrees Celsius, and the time is 0.5~10 minute, improves the efficiency of silanization treatment, and shape
It is uniform at 206 thickness of silanization layer, and there is preferable surface topography.
In one embodiment, when carrying out silanization treatment, 20 in the Other substrate materials on the surface of the first photoresist layer~
80% functional group is substituted by silylation.
The silanization layer 206 after silanization treatment includes oxygen element, element silicon, carbon and protium so that
The characteristic of silanization layer 206 and the characteristic completion of Other substrate materials change, if the functional group in photoresist expendable material
Further include nitrogen or element sulphur, the property of silanization layer in the silanization layer 206 for amido functional group or mercapto functional group
Matter is different from the property of the first photoresist layer, and the hardness and density of silanization layer are more than the hardness and density of the first photoresist layer,
Silanization layer can protect the first photoresist layer not to be damaged, and can prevent the filled layer being subsequently formed and the second photoresist layer
Diffusion of the middle solvent to the first photoresist layer 225, and when can improve subsequent etching hard mask layer 204 and dielectric layer 203, firmly
The etching selection ratio of mask material and dielectric layer material relative to the first photoresist layer material.
In other embodiments of the invention, if the material of first photoresist layer 225 is negative photoresist layer, directly
The first photoresist layer 225 to being formed with the first opening 210 carries out curing process.
In the embodiment of the present invention, the spin coating proceeding of the first photoresist layer 225 is formed, is formed in the first photoresist layer 225
The exposed and developed technique of first opening 210, and cured technique and silanization treatment are carried out to the first photoresist layer 225
Technique all carries out in a photoetching equipment, improves the efficiency of technique, saves the time of technique.
In other embodiments of the invention, after carrying out silanization treatment, further include：The silanization layer is aoxidized
Processing, converts silanization layer to hardness and the higher silicon oxide layer of compactness.
The oxidation processes are the processing of oxygen-containing plasma oxidation, when carrying out oxidation processes, remove the carbon in silanization layer
Element and protium so that remaining oxygen element and element silicon are cross-linked to form silicon oxide layer in silanization layer.
With reference to figure 12, the filled layer for covering the silanization layer 206 and filling 210 (with reference to figures 11) of full first opening is formed
207。
The purpose for forming filled layer 207 is made so that with flat carrier surface when being subsequently formed the second photoresist layer
The second photoresist layer that must be formed has higher thickness evenness.
The material of the filled layer 207 is organic matter.In one embodiment, the organic matter is carbon elements and protium
Organic matter, carbon and protium content are more than 90% in organic matter, and element silicon is free of in organic matter.
The formation process of the filled layer 207 is spin coating proceeding, and the thickness of the filled layer is 100nm-300nm.
With reference to figure 13, the second photoresist layer 208 is formed on the filled layer 207, shape in second photoresist layer 208
It is located at the first 210 (with reference to figures 11) of opening at having the first through hole 209 for exposing 207 surface of filled layer, the first through hole 209
Top.
It forms second photoresist layer 208 and uses spin coating proceeding, by exposed and developed technique in second photoetching
First through hole 209 is formed in glue-line 208.
In the present embodiment, when being exposed technique to the second photoresist layer 208, the hard mask layer 204 has been to maintain
Whole (there is no openings in hard mask layer 204), the focal plane detecting step and alignment mark detection that exposure technology carries out before
Step will not be influenced by the imperfect state of hard mask layer, and (focal plane detecting step and alignment mark detection step light carry out
When irradiation, by the way that the light intensity of different location after hard mask layer 204 is equal or gap very little), to improve focal plane inspection
Survey the precision of step and alignment mark detection step so that the precision of the first through hole formed in the second photoresist layer 208 improves.
Before forming the second photoresist layer 208, the second anti-reflection coating is formed on the filled layer 207 (in figure not
Show), a part of second anti-reflection coating as the second photoresist layer 208, first through hole part is located at the second anti-reflective coating
Layer.Second anti-reflective coating layer material is siliceous anti-reflective coating layer material, and the filled layer and when dielectric layer in subsequent etching increases
The etching selection ratio of dielectric layer material and filling layer material relative to Other substrate materials so that the size of first through hole is etched
It will not change in journey.
In other embodiments, before forming the second photoresist layer, silicon oxide layer is formed on the filled layer, in oxygen
The second anti-reflection coating is formed on SiClx layer.
With reference to figure 14, the filled layer 207 in first opening, 210 (with reference to figures 11) is etched along first through hole 209, the
The second through-hole 211 is formed in filled layer 207 in one opening 210.
It etches the filled layer 207 and uses anisotropic dry etch process, for example can be plasma etching industrial.
When etching filled layer 207, using hard mask layer 204 as stop-layer.
With reference to figure 15, the hard mask layer 204 and dielectric layer 203 are etched along first through hole 209 and the second through-hole 211,
Third through-hole 212 is formed in the hard mask layer 204 and dielectric layer 203.
The hard mask layer 204 and dielectric layer 203 are etched using anisotropic dry etch process, for example can be etc.
Ion etch process.
With reference to figure 16, second photoresist layer 208 (with reference to figure 15) and filled layer 207 (with reference to figure 15), exposure are removed
Go out the surface of silanization layer 206.
It removes second photoresist layer 208 (with reference to figure 15) and plasma may be used (with reference to figure 15) in filled layer 207
Body cineration technics.
Third opening is formed in hard mask layer 204 along the 210 etching hard mask layer 204 of the first opening with reference to figure 17
213。
It etches the hard mask layer 204 and uses anisotropic dry etch process, for example can be plasma etching work
Skill.
When forming third opening 213, it can be stop-layer with the first silicon oxide layer 21 or with the surface of dielectric layer 203 be
Stop-layer.
It is mask with the hard mask layer 204 with reference to figure 18, along the 213 etching dielectric layer 203 of third opening, is being situated between
The 4th opening 214 is formed in matter layer 203, the 4th opening 214 mutually runs through with third through-hole 212.
During etching dielectric layer 203 of 213 bottoms of third opening, while 212 bottom of third through-hole can be etched
The depth of dielectric layer, third through-hole 212 increases, and the bottom-exposed of third through-hole 212 goes out the table of underlying metal interconnection structure 205
Face.
During etch media layer 203, while removal silanization layer 206 (with reference to figure 17) and the first photoetching can be etched
Glue-line 225 (with reference to figure 17).
With reference to figure 19, the full gold of filling in the 4th 214 (with reference to the figures 18) of opening and third through-hole 212 (with reference to figure 18)
Belong to, forms Damascus metal interconnection structure 215, Damascus metal interconnection structure 215 and underlying metal interconnection structure
205 electrical connections.
Metal interconnection structure 215 forming process in Damascus is：It is formed and covers described 204 (with reference to figure 18) table of hard mask layer
The metal layer in face, and the full third of metal layer filling be open 213 (with reference to figures 18), the 4th be open 214 (with reference to figures 18) and the
Three through-holes 212 (with reference to figure 18)；Metal layer described in chemical-mechanical planarization is stop-layer with the first silicon oxide layer 21, and formation is filled out
Damascus metal interconnection structure full of the 4th opening 214 (with reference to the figures 18) and third through-hole 212 (with reference to figure 18)
215。
The material of the metal layer can be W, Al, Cu, Ti, Ag, Au, Pt, Ni one of which or several.
It, can also be in 213 (with reference to figures 18) of third opening, the 4th 214 (reference charts of opening before forming metal layer
18) diffusion impervious layer is formed with (with reference to the figure 18) side wall of third through-hole 212 and bottom surface, the diffusion impervious layer is for preventing
Metallic atom in Damascus metal interconnection structure 215 is spread into dielectric layer 203.
The material of the diffusion impervious layer is one kind or several in Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN, TiAlN
Kind.In a specific embodiment, the diffusion impervious layer is Ti layers and TiN double stackeds structure or Ta layers and TaN of pair
Layer heap stack structure.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided, forms dielectric layer on the substrate；
Hard mask layer is formed on the dielectric layer；
The first photoresist layer is formed on the hard mask layer, and the first opening is formed in first photoresist layer；
Silanization treatment is carried out to the surface of first photoresist layer for being formed with the first opening, by the first photoresist layer surface
Other substrate materials be converted into silanization layer；
Form the filled layer for covering the silanization layer and full first opening of filling；
The second photoresist layer is formed on the filled layer, forms first through hole in second photoresist layer, and described first is logical
Hole is located at the first overthe openings；
The filled layer in first opening is etched along first through hole, the second through-hole is formed in the filled layer in the first opening；
Along hard mask layer and dielectric layer described in first through hole and the second via etch, formed in the hard mask layer and dielectric layer
Third through-hole；
Second photoresist layer and filled layer are removed, the surface of silanization layer is exposed；
The hard mask layer is etched along the first opening, forms third opening in hard mask layer；
Using the hard mask layer as mask, the dielectric layer is etched along third opening, forms the 4th opening in the dielectric layer, it is described
4th opening mutually runs through with third through-hole.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the first photoresist layer material is
Negative photoresist or positive photoetching rubber.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the first photoresist layer material is
When positive photoetching rubber, carrying out, silanization treatment is front and back, further includes step, to be formed with the first photoresist layer of the first opening into
Row curing process, the curing process are UV photo-irradiation treatments or heat treatment.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that the temperature of the heat treatment is 100
~250 degrees Celsius, the time is 0.5~10 minute.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that in the first photoresist layer material
With resin, the resin includes hydroxyl functional group, carboxylic acid group's functional group, amido functional group or mercapto functional group, is carried out
When silanization treatment, the protium in functional group in the Other substrate materials on the surface of the first photoresist layer is substituted by silylation,
Form silanization layer.
6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the silanization treatment uses anti-
It is hexamethyldisilazane, tetramethyl-disilazane, double dimethylamino methyl silane dimethyl silicon substrate dimethylamine, dimethyl to answer object
Silicon substrate diethylamine, trimethylsilyl dimethylamine, trimethylsilyl diethylamine or dimethylamino pentamethyl disilane.
7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that described when carrying out silanization treatment
Reactant feeds reaction chamber in gaseous form, and the temperature of silanization treatment is 100~160 degrees Celsius, and the time is 0.5~10
Minute.
8. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the silanization layer includes oxygen member
Element, element silicon, carbon and protium.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the filled layer is organic
Object.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that in the organic matter carbon and
Protium content is more than 90%, and element silicon is free of in organic matter.
11. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the formation process of the filled layer
For spin coating proceeding.
12. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the thickness of the filled layer is
The thickness of 100nm-300nm, the first photoresist layer are 50nm-150nm.
13. the forming method of semiconductor structure as described in claim 1, which is characterized in that further include：Forming the first photoetching
Before glue-line, the first anti-reflection coating is formed on the hard mask layer；Before forming the second photoresist layer, in the filling
The second siliceous anti-reflection coating is formed on layer.
14. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that existed by exposed and developed technique
The first opening is formed in first photoresist layer.
15. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that the exposed and developed technique,
Curing process and silanization treatment technique are carried out in photoetching equipment.
16. the forming method of semiconductor structure as described in claim 1, which is characterized in that the dielectric layer material is situated between for low K
Permittivity material.
17. the forming method of semiconductor structure as described in claim 1, which is characterized in that the hard mask layer be single layer or
Multilayer lamination structure.
18. the forming method of semiconductor structure as described in claim 1, which is characterized in that be formed with bottom in the substrate
Metal interconnection structure.
19. the forming method of semiconductor structure as claimed in claim 18, which is characterized in that the bottom-exposed of third through-hole goes out
The surface of underlying metal interconnection structure.
20. the forming method of semiconductor structure as claimed in claim 19, which is characterized in that further include：The 4th opening and
Metal is filled in third through-hole, forms Damascus metal interconnection structure, Damascus metal interconnection structure and bottom gold
Belong to interconnection structure electrical connection.
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