CN105680864B - Successive approximation analog-to-digital converter, analog-to-digital conversion method, and sensing signal processing device - Google Patents
Successive approximation analog-to-digital converter, analog-to-digital conversion method, and sensing signal processing device Download PDFInfo
- Publication number
- CN105680864B CN105680864B CN201511032799.3A CN201511032799A CN105680864B CN 105680864 B CN105680864 B CN 105680864B CN 201511032799 A CN201511032799 A CN 201511032799A CN 105680864 B CN105680864 B CN 105680864B
- Authority
- CN
- China
- Prior art keywords
- digital
- analog
- voltage
- zero
- sampling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000012545 processing Methods 0.000 title claims abstract description 17
- 239000003990 capacitor Substances 0.000 claims abstract description 173
- 238000005070 sampling Methods 0.000 claims description 135
- 238000001514 detection method Methods 0.000 claims description 17
- 230000001133 acceleration Effects 0.000 claims description 3
- 230000011664 signaling Effects 0.000 claims description 2
- 230000035945 sensitivity Effects 0.000 abstract description 5
- 101100015484 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GPA1 gene Proteins 0.000 description 13
- 238000010586 diagram Methods 0.000 description 9
- 101100067427 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FUS3 gene Proteins 0.000 description 8
- 230000001276 controlling effect Effects 0.000 description 8
- 102100031577 High affinity copper uptake protein 1 Human genes 0.000 description 7
- 101710196315 High affinity copper uptake protein 1 Proteins 0.000 description 7
- 101100464779 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CNA1 gene Proteins 0.000 description 6
- 101100115778 Caenorhabditis elegans dac-1 gene Proteins 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- ORKBYCQJWQBPFG-WOMZHKBXSA-N (8r,9s,10r,13s,14s,17r)-13-ethyl-17-ethynyl-17-hydroxy-1,2,6,7,8,9,10,11,12,14,15,16-dodecahydrocyclopenta[a]phenanthren-3-one;(8r,9s,13s,14s,17r)-17-ethynyl-13-methyl-7,8,9,11,12,14,15,16-octahydro-6h-cyclopenta[a]phenanthrene-3,17-diol Chemical compound OC1=CC=C2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1.O=C1CC[C@@H]2[C@H]3CC[C@](CC)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 ORKBYCQJWQBPFG-WOMZHKBXSA-N 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/0607—Offset or drift compensation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a successive approximation analog-to-digital converter, a successive approximation analog-to-digital conversion method and a sensing signal processing device. The first compensation capacitor is added on the output end of the first digital-to-analog converter, the second digital-to-analog converter applies compensation voltage to the first compensation capacitor, meanwhile, the adjustable second compensation capacitor is connected between the output end of the existing successive approximation type first digital-to-analog converter and a zero voltage end, and the reference voltage actually subjected to analog-to-digital conversion can be adjusted by adjusting the second compensation capacitor. Therefore, the zero drift voltage can be compensated in the analog-to-digital converter, and the reference voltage of the analog-to-digital converter can be adjusted according to the requirement. The residual zero drift voltage of the amplifying circuit and the zero drift voltage of the device of the analog-digital converter can be further adjusted, and the reference voltage of the analog-digital converter can be adjusted to enable the sensors with different sensitivities to obtain the same output value under the condition of the same sensing input quantity, so that the sensing quantity input of the sensors can be correctly reflected.
Description
Technical Field
The invention relates to the integrated circuit technology, in particular to a successive approximation analog-to-digital converter, an analog-to-digital conversion method and a sensing signal processing device.
Background
In a general sensor signal conditioning system, as shown in fig. 1, an output signal of a sensor 1 is amplified by an amplifying circuit 2, the amplified signal is collected by an analog-to-digital converter 3(ADC) and converted into a digital signal, and the digital signal is sent to a digital signal processor 4(DSP) for data processing. The analog-to-digital converter 3 is an important component in the system and the successive approximation analog-to-digital converter is one of the types commonly used. The output value of the analog-to-digital converter 3 reflects the ratio and polarity relationship of the input voltage to its reference voltage.
Because of the difference in the sensitivity of the sensors, the output voltages obtained by different sensors when the same sensing quantity is input are not equal, and the input voltages input to the analog-to-digital converter 3 are also not equal after being amplified by the amplifying circuit with the same gain, which may also result in that the input signal finally input to the digital signal processor 4 may not correctly reflect the detection value of the sensor. Usually, a gain adjustment circuit is added in the amplifying circuit 2, so that the sensors with different sensitivities can obtain the same input voltage of the analog-to-digital converter under the condition of the same sensing quantity input. However, the gain adjustment in the amplifier circuit 2 often fails to meet the accuracy requirement, and further adjustment is required. Furthermore, the output signal of the sensor 1 contains, in addition to the useful signal portion, an unusable voltage signal, which is generally referred to as the null-shift voltage. The zero drift voltage is also amplified by the amplifying circuit 2 and collected by the analog-to-digital converter 3, which also causes the output of the analog-to-digital converter 3 to be inaccurate. And, the input-output dynamic range of the amplifying circuit 2 will be reduced due to the existence of the zero-shift voltage. In the prior art, a zero-drift voltage regulating circuit is usually added in the amplifying circuit 2, but the zero-drift voltage cannot be completely eliminated due to the limitation of precision. The amplifier circuit 2 and the analog-to-digital converter 3 also have zero drift voltage, and if the adjustment is not performed, the dynamic range of the sensor detection is reduced.
Disclosure of Invention
In view of this, the present invention provides a successive approximation analog-to-digital converter, an analog-to-digital conversion method, and a sensing signal processing apparatus, so as to compensate for a zero-drift voltage in the analog-to-digital converter and adjust a reference voltage of the analog-to-digital converter according to a requirement.
In a first aspect, a successive approximation analog-to-digital converter is provided, including:
the first digital-to-analog converter outputs corresponding analog output voltage according to the input digital signal and the voltage of the sampling end;
the return-to-zero switch is connected between the sampling end of the first digital-to-analog converter and the zero voltage end;
the sampling switch is connected between the sampling end of the first digital-to-analog converter and the analog signal input end;
a comparator having a first input terminal connected to an output terminal of the first digital-to-analog converter and a second input terminal connected to a zero-voltage terminal;
a second digital-to-analog converter for outputting an analog compensation voltage;
a first compensation capacitor connected between the output terminal of the second digital-to-analog converter and the output terminal of the first digital-to-analog converter;
the second compensation capacitor is connected between the output end of the first digital-to-analog converter and a zero voltage end; and the number of the first and second groups,
and the control circuit is connected with the first digital-to-analog converter and the comparator and is used for determining a digital signal corresponding to the analog input signal of the analog signal input end bit by bit in a successive approximation mode according to the output signal of the comparator.
Preferably, the control circuit is configured to control the sampling end of the first digital-to-analog converter to be connected to a zero voltage end for return to zero in a first mode, control the sampling end of the first digital-to-analog converter to be connected to an analog signal input end for sampling an analog input signal in a second mode, control the sampling switch and the return-to-zero switch to be turned off in a third mode, and determine a digital signal corresponding to the analog input signal at the analog signal input end in a successive approximation manner according to the comparator output signal control in a fourth mode;
the second digital-to-analog converter is used for outputting the analog compensation voltage without the zero drift voltage compensation value superposed in the first mode and the second mode, and outputting the analog compensation voltage superposed with the zero drift voltage compensation value in the third mode and the fourth mode.
Preferably, the second compensation capacitor is an adjustable capacitor for adjusting the reference voltage.
Preferably, the second compensation capacitor includes a plurality of capacitor units connected in parallel with each other, and each of the capacitor units includes:
a first switch connected between the first terminal and the middle terminal of the capacitor unit;
a sub-capacitor and a second switch connected in parallel between the intermediate terminal and the second terminal of the capacitor unit;
wherein the control signals of the first switch and the second switch are opposite.
Preferably, the first digital-to-analog converter includes:
the first end of each sampling capacitor is connected with the common end, and the second end of the (N + 1) th sampling capacitor is connected with the zero-voltage end;
the N control switches are respectively connected with the second ends of the 1 st to Nth sampling capacitors and used for connecting the second ends of the corresponding sampling capacitors to a reference voltage end or a zero voltage end, and the control ends of the N control switches are connected with the input end of the first digital-to-analog converter;
the common terminal is connected with the sampling terminal and the output terminal of the first digital-to-analog converter, and the capacitance value of the ith sampling capacitor is 2 of that of the 1 st sampling capacitori-1X, i ═ 1,2, …, N. The capacitance value of the (N + 1) th capacitor is equal to the capacitance value of the first sampling capacitor.
Preferably, the first digital-to-analog converter includes:
the sampling capacitors are connected between the first common end and a zero voltage end, the (N + 1) th sampling capacitor is connected between the first common end and the zero voltage end, and the (N + 2) th sampling capacitor is connected between the first common end and the second common end, wherein M is an integer larger than 1 and smaller than N;
the N control switches are respectively connected with the second ends of the 1 st to Nth sampling capacitors and used for connecting the second ends of the corresponding sampling capacitors to a reference voltage end or a zero voltage end, and the control ends of the N control switches are connected with the input end of the first digital-to-analog converter;
the first common end is connected with the sampling end of the first digital-to-analog converter, the second common end is connected with the output end of the first digital-to-analog converter, and the capacitance value of the ith sampling capacitor is 2 of that of the 1 st sampling capacitori-1X, i ═ 1,2, …, M; the capacitance value of the jth sampling capacitor is 2 of the capacitance value of the 1 st sampling capacitorj-M-1X, j ═ M +1, …, N-1, N; the capacitance values of the (N + 1) th and (N + 2) th sampling capacitors are equal to the capacitance value of the 1 st sampling capacitor.
Preferably, the control circuit is configured to control the return-to-zero switch to be turned on and the sampling switch to be turned off in a first mode, control the nth bit of the input digital signal of the first digital-to-analog converter to be 0 and the 1 st to N-1 bits to be 1, control the sampling switch to be turned on and the return-to-zero switch to be turned off in a second mode, keep the input digital signal of the first digital-to-analog converter unchanged, control the sampling switch and the return-to-zero switch to be turned off in a third mode, keep the input digital signal of the first digital-to-analog converter unchanged, keep the sampling switch and the return-to-zero switch to be turned off in a fourth mode, traverse from the nth bit to the 1 st bit of the input digital signal bit by bit, set the current bit to 0 for each current bit, change the current bit to 1 when the output signal of the comparator indicates that the voltage of the first input terminal is greater than the voltage of the second, otherwise, determining the current bit of the input digital signal as 0 until all bits of the input digital signal are determined;
the digital-to-analog converter is used for outputting analog compensation voltage without a zero drift voltage compensation value superposed in a first mode and a second mode, and outputting analog compensation voltage superposed with the zero drift voltage compensation value in a third mode and a fourth mode.
Preferably, the first compensation capacitor, the second compensation capacitor, and the zero-shift voltage compensation value and the zero-shift voltage satisfy the following relationship:
wherein, VzIs zero drift voltage, CosIs the capacitance value of the first compensation capacitor, CGIs the capacitance value of the second compensation capacitor, C0The capacitance value of the (N + 1) th sampling capacitor.
Preferably, the relation between the reference voltage of the successive approximation analog-to-digital converter and the voltage of the reference voltage terminal satisfies the following relation:
wherein, VR' is a reference voltage, V, of the successive approximation analog-to-digital converterRIs the voltage of the reference voltage terminal, CosIs as followsA capacitance value of a compensation capacitor, CGIs the capacitance value of the second compensation capacitor, C0Is the capacitance value of the 1 st sampling capacitor.
In a second aspect, a successive approximation analog-to-digital conversion method is provided, which is applied to a successive approximation digital-to-analog converter, where the successive approximation digital-to-analog converter includes a first digital-to-analog converter, and outputs a corresponding output analog voltage according to an input digital signal and an analog signal at a sampling end; the return-to-zero switch is connected between the sampling end of the first digital-to-analog converter and the zero voltage end; the sampling switch is connected between the sampling end of the first digital-to-analog converter and the analog signal input end; a comparator having a first input terminal connected to an output terminal of the first digital-to-analog converter and a second input terminal connected to a zero-voltage terminal; a second digital-to-analog converter for outputting an analog compensation voltage; a first compensation capacitor connected between the output of the digital-to-analog converter and the output of the capacitive switching network; the second compensation capacitor is connected between the output end of the first digital-to-analog converter and the zero voltage end; the control circuit is used for determining digital signals corresponding to the analog input signals of the analog signal input end bit by bit in a successive approximation mode according to the output signals of the comparator;
the method comprises the following steps:
in a first mode, controlling a sampling end of the first digital-to-analog converter to be connected to a zero voltage end for zeroing, and controlling a second digital-to-analog converter to apply analog compensation voltage which is not superposed with a zero drift voltage compensation value to a first compensation capacitor;
in a second mode, controlling a sampling end of the first digital-to-analog converter to be connected to an analog signal input end to sample an analog input signal, and controlling a second digital-to-analog converter to apply analog compensation voltage without a zero drift voltage compensation value to the first compensation capacitor;
in a third mode, the sampling switch and the return-to-zero switch are controlled to be turned off, and the second digital-to-analog converter is controlled to apply analog compensation voltage superposed with a null shift voltage compensation value to the first compensation capacitor;
and in a fourth mode, controlling the second digital-to-analog converter to keep applying the analog compensation voltage superposed with the null shift voltage compensation value to the first compensation capacitor, adjusting the input digital signal of the first digital-to-analog converter according to the output signal of the comparator, and determining the digital signal corresponding to the analog input signal of the analog signal input end in a successive approximation manner.
Preferably, adjusting the input digital signal to the first digital-to-analog converter according to the comparator output signal, determining the digital signal corresponding to the analog input signal at the analog signal input terminal in a successive approximation manner includes:
keeping the sampling switch and the return-to-zero switch off, controlling the input digital signal of the first digital-to-analog converter to traverse from the highest bit to the lowest bit, setting the current bit to 0 for each current bit, changing the current bit to 1 when the output signal of the comparator indicates that the voltage of the first input end is greater than the voltage of the second input end, and otherwise determining the current bit of the input digital signal to be 0 until all bits of the input digital signal are determined.
Preferably, the first compensation capacitor, the second compensation capacitor, and the zero-shift voltage compensation value and the zero-shift voltage satisfy the following relationship:
wherein, VzIs zero drift voltage, CosIs the capacitance value of the first compensation capacitor, CGIs the capacitance value of the second compensation capacitor, C0Is the minimum capacitance value of the sampling capacitor of the first digital-to-analog converter.
Preferably, the relation between the reference voltage of the successive approximation analog-to-digital converter and the voltage of the reference voltage terminal satisfies the following relation:
wherein, VR' is a reference voltage, V, of the successive approximation analog-to-digital converterRIs the voltage of the reference voltage terminal, CosIs the capacitance value of the first compensation capacitor, CGFor the second compensationCapacitance value of the capacitor, C0Is the capacitance value of the 1 st sampling capacitor.
In a third aspect, a sensing signal processing apparatus is provided, including:
the sensor is used for sensing the physical quantity and outputting an analog detection signal;
an amplifying circuit for amplifying the analog detection signal;
the analog-to-digital converter is used for converting the amplified analog detection signal into a digital detection signal; and
a digital signal processor for processing the digital detection signal;
wherein the analog-to-digital converter is a successive approximation analog-to-digital converter as described above.
Preferably, the sensor is at least one of a magnetometer, an acceleration sensor, a temperature sensor, and a humidity sensor.
The first compensation capacitor is added on the output end of the first digital-to-analog converter, the second digital-to-analog converter applies compensation voltage to the first compensation capacitor, meanwhile, an adjustable second compensation capacitor is connected between the first input end and the zero voltage end of the comparator of the existing successive approximation type analog-to-digital converter, and the reference voltage actually subjected to analog-to-digital conversion can be adjusted by adjusting the second compensation capacitor. Therefore, the zero drift voltage can be compensated in the analog-to-digital converter, and the reference voltage of the analog-to-digital converter can be adjusted according to the requirement. The residual zero drift voltage of the amplifying circuit and the zero drift voltage of the device of the analog-digital converter can be further adjusted, and the reference voltage of the analog-digital converter can be adjusted to enable the sensors with different sensitivities to obtain the same output value under the condition of the same sensing input quantity, so that the sensing quantity input of the sensors can be correctly reflected.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a prior art sensor signal processing apparatus;
fig. 2 is a circuit diagram of a conventional successive approximation analog-to-digital converter;
FIG. 3 is a circuit diagram of a successive approximation analog to digital converter of an embodiment of the present invention;
FIG. 4 is a circuit diagram of an adjustable capacitor according to an embodiment of the present invention;
FIG. 5 is a flow chart of a successive approximation analog-to-digital conversion method of an embodiment of the present invention;
fig. 6 is a circuit diagram of a successive approximation analog-to-digital converter according to another embodiment of the present invention;
fig. 7 is a sensor signal processing apparatus to which a successive approximation analog-to-digital converter according to an embodiment of the present invention is applied.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
Fig. 2 is a circuit diagram of a conventional successive approximation analog-to-digital converter.
As shown in fig. 2, the conventional successive approximation analog-to-digital converter includes a digital-to-analog converter DAC, a comparator CMP, and a control circuit CTR. The successive approximation analog-to-digital converter further comprises a return-to-zero switch SWZEROAnd a sampling switch SWIN. Wherein the first input terminal of the comparator CMP is connected to the output terminal of the digital-to-analog converter DAC and the second input terminal is connected to the zero level terminal 0. The input of the digital-to-analog converter DAC, i.e. the port for inputting the digital signal, is connected to the control circuit CTR. The DAC further comprises a sampling terminal r connected to a return-to-zero switch SWZEROAnd a sampling switch SWINAnd (4) connecting. Wherein, the return-to-zero switch SWZEROConnected between a sampling terminal r and a zero level terminal 0, a sampling switch SWINConnected between the sampling terminal r and the analog input signal terminal which can pass through the sampling switch SWINInput analog signal V of input successive approximation analog-to-digital converteri。
In particular, the digital-to-analog converter DAC of the successive approximation analog-to-digital converter may comprise N +1 capacitors C0To CNThe positive terminals (i.e. the first terminals) are connected to a common terminal c, which is connected to the sampling terminal r and the output terminal of the digital-to-analog converter DAC. Wherein the DAC further comprises N control switches K0To KN-1Which are respectively connected to the capacitor C0To CN-1Is connected to the negative terminal of the corresponding capacitor CiIs connected to a reference voltage terminal VROr zero voltage terminal 0.
The control circuit CTR implements the analog-to-digital conversion by three steps:
the first step isZero process, zero switch SWZEROConducting and sampling switch SWINAnd (6) turning off. The control circuit CTR outputs to the switch KN-1Control signal BN-1Is 0, capacitance CN-1The negative terminal is connected to the reference voltage terminal VRSwitch KN-2Control signals B of …, K1, K0N-2…, B1 and B0 are 1, the capacitance C isN-2,…,C1And the negative terminal of C0 is connected to 0.
The second step is a sampling process, the control circuit CTR controls the switch state of the DAC to be unchanged and simultaneously controls the return-to-zero switch SWZEROSwitch off, sample switch SWINAnd conducting. The first input A of the comparator is connected to an input analog signal Vi. The charge on the first input terminal a capacitor at this time is:
Q＝(Vi-VR)·CN-1+Vi·(CN-2+......+C1+C0)＝2N·C0·Vi-2N-1·C0·VR
the third step is the conversion process. The control circuit CTR first keeps the switch state of the DAC unchanged, at which time the voltage V at the first input a of the comparatorAIs equal to the input analogue signal Vi. Judgment of V by comparator CMPAPositive and negative polarities of (1).
During the conversion, the charge on the capacitor remains unchanged, and the voltage at the input terminal a of the comparator CMP satisfies:
i.e. the voltage V of the first input AACan characterize the difference between the input analog signal and the analog signal corresponding to the digital signal currently input to the digital-to-analog converter DAC by the control circuit CTR, if VAIf it is greater than zero, it indicates that the analog signal corresponding to the current digital signal is smaller than the analog input signal, and if V is greater than zero, it indicates that the analog signal corresponding to the current digital signal is smaller than the analog input signalAIf the analog signal is smaller than zero, the analog signal corresponding to the current digital signal is larger than the analog input signal.
According to comparator CMPComparing the result to determine whether to change the switch K corresponding to the most significant bit of the digital signalN-1The state of (1). If the comparison result is high (i.e., V)ALess than zero), switch K will be switched onN-1The state of (2) is kept unchanged; if the comparison result is low (i.e., V)AGreater than zero), then V is connectedRInstead, 0 is connected.
Next, the switches with lower bits are connected to V in turn according to the same method of the highest bitR(the corresponding digital bit is 0) and then it is decided whether the state of the current switch is changed according to the comparison result of the comparator CMP. Thus, the digital signal is determined bit by bit until the state of all N switches (i.e., N bits) is determined.
As described above, although the conventional successive approximation analog-to-digital converter can perform analog-to-digital conversion, it is not possible to effectively adjust the voltage V at the sampling end depending on the sensor connected at the preceding stageRThus, the analog-to-digital conversion may be rendered inaccurate in some cases. Meanwhile, the conventional successive approximation analog-to-digital converter cannot solve the negative influence of the zero drift voltage.
Fig. 3 is a circuit diagram of a successive approximation analog-to-digital converter according to an embodiment of the present invention.
As shown in fig. 3, the successive approximation analog-to-digital converter according to the embodiment of the present invention includes a first digital-to-analog converter DAC1, a comparator CMP1, a control circuit CTR1, and a return-to-zero switch SWZEROSampling switch SWINA first compensation capacitor COSA second compensation capacitor CGAnd a second digital-to-analog converter DAC 2. Wherein the comparator CMP1 has a first input a connected to the output of the first digital-to-analog converter DAC1 and a second input connected to the zero level terminal 0. An input terminal (i.e., a port for inputting a digital signal) of the first digital-to-analog converter DAC1 is connected to the control circuit CTR 1. The control circuit CTR1 inputs the digital signal B to the first digital-to-analog converter DAC1N- 1BN-2……B1B0To control its output. The first DAC1 also includes a sampling terminal r coupled to a return-to-zero switch SWZEROAnd a sampling switch SWINAnd (4) connecting. Wherein, the return-to-zero switch SWZEROConnected at the sampling terminal r and at zero levelBetween terminals 0, sampling switch SWINConnected between the sampling terminal r and the analog input signal terminal which can pass through the sampling switch SWINInput analog signal V of input successive approximation analog-to-digital converteri。
The first DAC1 outputs a corresponding first analog voltage V according to the input digital signal and the analog signal at the sampling endA。
The comparator CMP1 has a first input a (inverting input) connected to the output of the first digital-to-analog converter DAC1, and a second input (non-inverting input) connected to the zero voltage terminal 0.
The second DAC2 is used for providing a first compensation capacitor C according to the input digital signalOSOutputting an analog compensation voltage VC。
First compensation capacitor COSConnected between the output of the second digital to analog converter DAC2 and the output of the capacitor switching network. In particular, a first compensation capacitor COSIs connected to the output of the second digital to analog converter DAC2 and the positive terminal is connected to the output of the first digital to analog converter DAC 1.
Second compensation capacitor CGConnected between the output of the first digital-to-analog converter and the zero voltage terminal. Preferably, the second compensation capacitor CGIt is an adjustable capacitor that can be used to adjust the actual reference voltage for analog to digital conversion. In particular, the second compensation capacitor CGThe capacitance value can be adjusted based on the control of a plurality of switches. Second compensation capacitor CGA circuit diagram of a preferred embodiment of the present invention is shown in fig. 4.
Second compensation capacitor CGComprising a plurality of capacitor units G connected in parallel1～GNEach of the capacitor cells GiComprises a first switch KiASub-capacitor CGiAnd a second switch KiB。
First switch KiAConnected between the first terminal p and the middle terminal m of the capacitive unit. Sub-capacitor CGiAnd a second switch KiBA second capacitor unit connected in parallel to the intermediate terminal mBetween two ends n. First switch KiAAnd a second switch KiBThe control signals of (1) are opposite. In FIG. 4, the first switch K is turned oniAAnd a second switch KiBThe NOT gate is connected between the control ends to ensure that the control signals are opposite. Of course, those skilled in the art will readily appreciate that other implementations may be used. Thereby, the first switch KiAWhen conducting, the second switch KiBOff, sub-capacitance CGiIs switched into a first terminal p and a second terminal n. At the first switch KiAWhen turned off, the second switch KiBOn the one hand, a sub-capacitor CGiIs disconnected from the first terminal p and simultaneously passes through the second switch KiBThe stored charge is discharged to zero. Through different capacitor units GiThe capacitance between the first end p and the second end n can be changed, and the capacitance can be adjusted.
More preferably, the sub-capacitances C of the different capacitive unitsGiMay have different capacitance values, e.g. may be arranged such that CGi＝CG1·2i-1。
The control circuit CTR1 is used to determine a digital signal corresponding to the analog input signal at the analog signal input terminal bit by bit in a successive approximation manner from the output signal of the comparator CMP 1.
In particular, in the present embodiment, the first digital-to-analog converter DAC1 includes N +1 sampling capacitors C0To CNN control switches K0To KN-1. Wherein, N +1 sampling capacitors C0To CNAre connected to a common terminal c which is connected to the sampling terminal r and to the output terminal a of the first digital-to-analog converter DAC 1. Wherein, the N +1 th sampling capacitor CNIs connected to the zero level terminal 0, i.e., the second terminal. N control switches K0To KN-1Respectively connected with a sampling capacitor C0To CN-1Is connected to the negative terminal of the corresponding capacitor CiIs connected to a reference voltage terminal VROr zero voltage terminal 0. Specifically, at control signal BiWhen 1, the switch K is controllediConnected to the zero voltage terminal 0 at the control signal BiIs 0 atControl switch KiConnected to a reference voltage terminal VR. Wherein, the ith sampling capacitor Ci-1The capacitance value of (1) is the capacitance value C of the 1 st sampling capacitor 02 of (2)i-1X, i ═ 1,2, …, N, i.e., Ci-1＝2i-1·C0,i＝1,......,N
In the embodiment of the present invention, the control circuit CTR1 adds a compensation process by changing the first compensation capacitor COSThe voltage value of the upper voltage is used for compensating the zero drift voltage.
The control flow of the control circuit CTR1 is shown in fig. 5.
In the first mode, in step S510, the sampling terminal r of the first DAC1 is controlled to be connected to the zero voltage terminal 0 for zeroing, and the second DAC2 is controlled to supply the first compensation capacitor COSApplying the analog compensation voltage Vc ═ V of the compensation value of the non-superimposed zero drift voltageOS_INT。
In particular by controlling the return-to-zero switch SWZEROConducting and sampling switch SWINThe zeroing is accomplished by simultaneously inputting a digital signal 0111 ….111 (i.e., the most significant bit is 0 for all remaining bits) to the first digital-to-analog converter DAC 1.
In the second mode, in step S520, the sampling terminal r of the first DAC1 is controlled to be connected to the analog signal input terminal for the analog input signal ViSampling, and controlling the second DAC2 to transfer the sample to the first compensation capacitor COSAnalog compensation voltage V for applying non-superimposed zero-shift voltage compensation valueC＝VOS_INT. That is, in both the first mode and the second mode, the digital signal input to the second digital-to-analog converter DAC2 is the same, being an initial signal.
After step 520, the voltage V at the output terminal a of the first DAC1ASatisfies the following conditions:
Q＝(Vi-VR)·CN-1+Vi·(CN-2+......+C1+C0)+Vi·(CG+COS)-COS·VOS_INIT
＝(2N·C0+CG+COS)·Vi-2N-1·C0·VR-COS·VOS_INIT
in the third mode, the sampling switch SW is controlled in step S530INAnd a zero switch SWZEROIs turned off and controls the second digital-to-analog converter DAC2 to feed the first compensation capacitor COSApplying an analog compensation voltage Vc-V superimposed with a zero-shift voltage compensation valueOS_INT-VOS。
Due to the sampling switch SWINAnd a zero switch SWZEROAll are turned off, all sampling capacitors and the first compensation capacitor COSAnd a second compensation capacitor CG(second compensating capacitor CGThe capacitance value is adjusted before work, and the capacitance value is not changed during work) is changed only by introducing the zero-shift voltage compensation value, so that the zero-shift voltage is compensated.
At this time, due to the second compensation capacitor COSVoltage V at the output terminal a of the first digital-to-analog converter DAC1AThe change is as follows:
in the fourth mode, step 540, the second digital-to-analog converter DAC2 is controlled to remain on the first compensation capacitor COSApplying an analog compensation voltage V superimposed with a zero-drift voltage compensation valueC＝VOS_INT-VOSThe input digital signal to the first DAC1 is controlled and adjusted according to the output signal of the comparator CMP1, and a digital signal corresponding to the analog input signal at the analog signal input terminal is determined in a successive approximation manner.
Specifically, in the fourth mode, the control circuit CTR1 holds the sampling switch SWINAnd a zero switch SWZEROOff, controls the input digital signal to the first DAC1 to traverse from the most significant bit to the least significant bit, and for each current bit, keeps the current bit set constant, and the output signal at the comparator indicates that the voltage at the first input terminal is greater than the voltage at the second input terminalAnd when the voltage of the terminal is input, the current bit is changed into 1, otherwise, the current bit of the input digital signal is determined to be 0 until all bits of the input digital signal are determined.
Correspondingly, in the first DAC1, the capacitor C is sampled from the Nth oneN-1And the Nth control switch KN-1Start (Nth control switch K)N-10) is detected, the input of the current 0111 … … 111 is kept unchanged, the output of the comparator CMP1 is determined, if the output of CMP1 is indicative of the voltage V at the first input terminalAIf the voltage is greater than 0, it indicates that the analog signal corresponding to the current digital signal is smaller than the analog input signal, and the current bit needs to be set to 1 (i.e., the state of the control switch corresponding to the current bit needs to be changed). Otherwise, the current bit of the input digital signal should be set to 0. The next digital signal is then determined in the same way (i.e. the state of the next control switch is determined in the same way), whereby until all bits of the input digital signal have been determined.
During the conversion, the charge on the capacitor remains unchanged, and the voltage at the input terminal a of the comparator CMP satisfies:
as can be seen from the above formula, compared to the voltage at the input terminal a in the prior art:
voltage V of the inventionAIs added with one item
Which can compensate ViThe zero drift voltage carried in the analog-to-digital converter and caused by the device of the analog-to-digital converter is compensated, and the superposed zero drift voltage compensation value-V is changedOSThe zero drift adjustment can be carried out. The relevant parameters may be obtained by experimental or computational measurements. At the same time, reference voltage VRAdding a gain factor
Varying the variable capacitance CGReference voltage adjustment can be performed, so that the term-by-term approximation type analog-to-digital converter provided by the embodiment of the invention can be suitable for different sensors, and the conversion precision and the dynamic range are improved.
The first compensation capacitor is added on the output end of the first digital-to-analog converter, the compensation voltage for the zero drift voltage is applied to the first compensation capacitor through the second digital-to-analog converter, meanwhile, the adjustable second compensation capacitor is connected between the input ends of the comparator of the existing analog-to-digital converter, and the reference voltage actually subjected to analog-to-digital conversion can be adjusted through adjusting the second compensation capacitor. Therefore, the zero drift voltage can be compensated in the analog-to-digital converter, and the reference voltage of the analog-to-digital converter can be adjusted according to the requirement. The residual zero drift voltage of the amplifying circuit and the zero drift voltage of the device of the analog-digital converter can be further adjusted, and the reference voltage of the analog-digital converter can be adjusted to enable the sensors with different sensitivities to obtain the same output value under the condition of the same sensing input quantity, so that the sensing quantity input of the sensors can be correctly reflected.
Fig. 6 is a circuit diagram of a successive approximation analog-to-digital converter according to another embodiment of the present invention. The successive approximation analog-to-digital converter shown in fig. 6 has the same structure as fig. 3, and the principle of compensating the zero drift voltage and adjusting the reference voltage is the same. In contrast, the first digital-to-analog converter DAC 1' of the successive approximation analog-to-digital converter shown in fig. 6 has a different structure.
The first DAC 1' includes N +2 sampling capacitors C0To CN+1. In FIG. 6, the 1 st to Mth sampling capacitors C0To C3Is connected to the first common terminal x1, where M is an integer greater than 1 and less than N. In fig. 6, N is 8, M is 4, M +1 to nth sampling capacitors C4To C7Is connected to a second common terminal x 2. N +1 th sampling capacitor C8Connected between the first common terminal and the zero voltage terminal. N +2 th sampling capacitor C9Connection ofBetween the first common terminal x1 and the second common terminal x 2. It should be understood that although in fig. 6, M is equal to N/2, M may also be other values, for example, when N is equal to 8, M may be 3 or 5.
N control switches K0To KN-1Respectively connected with the second ends (negative ends) of the 1 st to Nth sampling capacitors for connecting the second ends of the corresponding sampling capacitors to the reference voltage end VROr zero voltage terminal 0, the N control switches K0To KN-1The control end of the first digital-to-analog converter is connected with the input end of the first digital-to-analog converter;
the first common end is connected with the sampling end of the first digital-to-analog converter, the second common end is connected with the output end of the first digital-to-analog converter, and the capacitance value of the ith sampling capacitor is 2 of that of the 1 st sampling capacitori-1X, i ═ 1,2, …, M; the capacitance value of the jth sampling capacitor is 2 of the capacitance value of the 1 st sampling capacitorj-M-1X, j ═ M +1, …, N-1, N; the capacitance values of the (N + 1) th and (N + 2) th sampling capacitors are equal to the capacitance value of the 1 st sampling capacitor.
Therefore, the first digital-to-analog converter of this embodiment can reduce the requirement for the range of capacitance values by adding one capacitor, and can achieve the same charge property and characteristics as the digital-to-analog converter DAC1 shown in fig. 3 in a smaller capacitance value range.
On the basis, the control circuit CTR1 can control the successive approximation analog-to-digital converter to perform analog-to-digital conversion and compensate the null-shift voltage at the same time based on the same control manner as the previous embodiment. Meanwhile, the actual reference voltage can be adjusted by adjusting the second compensation capacitor so as to adapt to different sensors.
Fig. 7 is a sensing signal processing apparatus to which a successive approximation analog-to-digital converter according to an embodiment of the present invention is applied. As shown in fig. 7, the sensing signal processing apparatus includes a sensor 1, an amplifying circuit 2, an analog-to-digital converter 3', and a digital signal processor 4.
The sensor 1 is used for sensing a physical quantity and outputting an analog detection signal. The sensor is at least one of a magnetometer, an acceleration sensor, a temperature sensor and a humidity sensor.
The amplifying circuit 2 is used for amplifying the analog detection signal.
The analog-to-digital converter 3' is a successive approximation analog-to-digital converter according to an embodiment of the present invention, and is configured to convert the amplified analog detection signal into a digital detection signal.
The digital signal processor 4 is used for processing the digital detection signal.
Due to the application of the successive approximation analog-to-digital converter with adjustable reference voltage and zero drift voltage compensation, the sensing signal processing device shown in fig. 7 can more accurately obtain and process the physical quantity detected by the sensor.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (14)
1. A successive approximation analog-to-digital converter comprising:
the first digital-to-analog converter outputs corresponding analog output voltage according to the input digital signal and the voltage of the sampling end;
the return-to-zero switch is connected between the sampling end of the first digital-to-analog converter and the zero voltage end;
the sampling switch is connected between the sampling end of the first digital-to-analog converter and the analog signal input end;
a comparator having a first input terminal connected to an output terminal of the first digital-to-analog converter and a second input terminal connected to a zero-voltage terminal;
the first compensation capacitor is connected between the output end of the second digital-to-analog converter and the output end of the first digital-to-analog converter;
the second compensation capacitor is connected between the output end of the first digital-to-analog converter and a zero voltage end; and the number of the first and second groups,
the control circuit is connected with the first digital-to-analog converter and the comparator and used for controlling the sampling end of the first digital-to-analog converter to be connected to a zero voltage end to return to zero in a first mode, controlling the sampling end of the first digital-to-analog converter to be connected to an analog signal input end to sample an analog input signal in a second mode, controlling the sampling switch and the return-to-zero switch to be switched off in a third mode, and determining a digital signal corresponding to the analog input signal of the analog signal input end bit by bit in a successive approximation mode according to an output signal of the comparator in a fourth mode;
and the second digital-to-analog converter is used for outputting the analog compensation voltage without the zero drift voltage compensation value superposed in the first mode and the second mode, and outputting the analog compensation voltage superposed with the zero drift voltage compensation value in the third mode and the fourth mode.
2. The successive approximation analog-to-digital converter of claim 1, wherein the second compensation capacitor is an adjustable capacitor for adjusting a reference voltage.
3. The successive approximation analog-to-digital converter of claim 2, wherein the second compensation capacitor comprises a plurality of capacitor units connected in parallel with each other, each of the capacitor units comprising:
a first switch connected between the first terminal and the middle terminal of the capacitor unit;
a sub-capacitor and a second switch connected in parallel between the intermediate terminal and the second terminal of the capacitor unit;
wherein the control signals of the first switch and the second switch are opposite.
4. The successive approximation analog-to-digital converter of claim 1, wherein the first digital-to-analog converter comprises:
the first end of each sampling capacitor is connected with the common end, and the second end of the (N + 1) th sampling capacitor is connected with the zero-voltage end;
the N control switches are respectively connected with the second ends of the 1 st to Nth sampling capacitors and used for connecting the second ends of the corresponding sampling capacitors to a reference voltage end or a zero voltage end, and the control ends of the N control switches are connected with the input end of the first digital-to-analog converter;
the common terminal is connected with the sampling terminal and the output terminal of the first digital-to-analog converter, and the capacitance value of the ith sampling capacitor is 2 of that of the 1 st sampling capacitori-1Multiple, i =1,2, …, N; the capacitance value of the (N + 1) th capacitor is equal to the capacitance value of the 1 st sampling capacitor.
5. The successive approximation analog-to-digital converter of claim 1, wherein the first digital-to-analog converter comprises:
the sampling capacitors are connected between the first common end and a zero voltage end, the (N + 1) th sampling capacitor is connected between the first common end and the zero voltage end, and the (N + 2) th sampling capacitor is connected between the first common end and the second common end, wherein M is an integer larger than 1 and smaller than N;
the N control switches are respectively connected with the second ends of the 1 st to Nth sampling capacitors and used for connecting the second ends of the corresponding sampling capacitors to a reference voltage end or a zero voltage end, and the control ends of the N control switches are connected with the input end of the first digital-to-analog converter;
the first common end is connected with the sampling end of the first digital-to-analog converter, the second common end is connected with the output end of the first digital-to-analog converter, and the capacitance value of the ith sampling capacitor is 2 of that of the 1 st sampling capacitori-1Multiple, i =1,2, …, M; the capacitance value of the jth sampling capacitor is 2 of the capacitance value of the 1 st sampling capacitorj-M-1Multiple, j = M +1, …, N-1, N; the capacitance values of the (N + 1) th and (N + 2) th sampling capacitors are equal to the capacitance value of the 1 st sampling capacitor.
6. The successive approximation analog-to-digital converter according to claim 4 or 5, wherein the control circuit is configured to control the return-to-zero switch to be turned on and the sampling switch to be turned off in a first mode, and to control the Nth bit of the input digital signal of the first digital-to-analog converter to be 0 and the 1 st to N-1 st bits to be 1, and to control the sampling switch to be turned on and the return-to-zero switch to be turned off in a second mode, and to keep the input digital signal of the first digital-to-analog converter unchanged, and to control the sampling switch and the return-to-zero switch to be turned off in a third mode, and to keep the sampling switch and the return-to-zero switch turned off in a fourth mode, and to traverse bit by bit from the Nth bit to the 1 st bit of the input digital signal, and to set the current bit to 0 for each current bit, when the output signal of the comparator indicates that the voltage of the first input terminal is greater than the voltage of, changing the current bit to 1, otherwise determining the current bit of the input digital signal to be 0 until all bits of the input digital signal are determined;
the second digital-to-analog converter is used for outputting the analog compensation voltage without the zero drift voltage compensation value superposed under the first mode and the second mode, and outputting the analog compensation voltage superposed with the zero drift voltage compensation value under the third mode and the fourth mode.
7. The successive approximation analog-to-digital converter of claim 4 or 5, wherein the first compensation capacitor, the second compensation capacitor and the zero-drift voltage compensation value satisfy the following relation with the zero-drift voltage:
wherein,V z the voltage is the zero-drift voltage, and the voltage is the zero-drift voltage,C os is the capacitance value of the first compensation capacitor,C G is the capacitance value of the second compensation capacitor,C 0 the capacitance value of the (N + 1) th sampling capacitor.
8. The successive approximation analog-to-digital converter of claim 4 or 5, wherein the relation of the reference voltage of the successive approximation analog-to-digital converter and the voltage of the reference voltage terminal satisfies the following relation:
wherein,V R ’for the reference voltage of the successive approximation analog to digital converter,V R is the voltage at the reference voltage terminal,C os is the capacitance value of the first compensation capacitor,C G is the capacitance value of the second compensation capacitor,C 0 is the capacitance value of the 1 st sampling capacitor.
9. A successive approximation analog-to-digital conversion method is applied to a successive approximation digital-to-analog converter, wherein the successive approximation digital-to-analog converter comprises a first digital-to-analog converter and outputs corresponding output analog voltage according to an input digital signal and an analog signal of a sampling end; the return-to-zero switch is connected between the sampling end of the first digital-to-analog converter and the zero voltage end; the sampling switch is connected between the sampling end of the first digital-to-analog converter and the analog signal input end; a comparator having a first input terminal connected to an output terminal of the first digital-to-analog converter and a second input terminal connected to a zero-voltage terminal; a second digital-to-analog converter for outputting an analog compensation voltage; a first compensation capacitor connected between the output terminal of the second digital-to-analog converter and the output terminal of the first digital-to-analog converter; the second compensation capacitor is connected between the output end of the first digital-to-analog converter and the zero voltage end; the control circuit is used for determining digital signals corresponding to the analog input signals of the analog signal input end bit by bit in a successive approximation mode according to the output signals of the comparator;
the method comprises the following steps:
in a first mode, controlling a sampling end of the first digital-to-analog converter to be connected to a zero voltage end for zeroing, and controlling a second digital-to-analog converter to apply analog compensation voltage which is not superposed with a zero drift voltage compensation value to a first compensation capacitor;
in a second mode, controlling a sampling end of the first digital-to-analog converter to be connected to an analog signal input end to sample an analog input signal, and controlling a second digital-to-analog converter to apply analog compensation voltage without a zero drift voltage compensation value to the first compensation capacitor;
in a third mode, the sampling switch and the return-to-zero switch are controlled to be turned off, and the second digital-to-analog converter is controlled to apply analog compensation voltage superposed with a null shift voltage compensation value to the first compensation capacitor;
and in a fourth mode, controlling the second digital-to-analog converter to keep applying the analog compensation voltage superposed with the null shift voltage compensation value to the first compensation capacitor, adjusting the input digital signal of the first digital-to-analog converter according to the output signal of the comparator, and determining the digital signal corresponding to the analog input signal of the analog signal input end in a successive approximation manner.
10. The successive approximation analog-to-digital conversion method according to claim 9, wherein the input digital signal to the first digital-to-analog converter is adjusted according to the comparator output signal, and the determining the digital signal corresponding to the analog input signal of the analog signal input terminal in the successive approximation manner includes:
keeping the sampling switch and the return-to-zero switch off, controlling the input digital signal of the first digital-to-analog converter to traverse from the highest bit to the lowest bit, setting the current bit to 0 for each current bit, changing the current bit to 1 when the output signal of the comparator indicates that the voltage of the first input end is greater than the voltage of the second input end, and otherwise determining the current bit of the input digital signal to be 0 until all bits of the input digital signal are determined.
11. The successive approximation analog-to-digital conversion method according to claim 9, wherein the first compensation capacitor, the second compensation capacitor and the zero drift voltage compensation value satisfy the following relationship with the zero drift voltage:
wherein,V z the voltage is the zero-drift voltage, and the voltage is the zero-drift voltage,C os is the capacitance value of the first compensation capacitor,C G is the capacitance value of the second compensation capacitor,C 0 is the minimum capacitance of the sampling capacitor of the first digital-to-analog converterThe value is obtained.
12. The successive approximation analog-to-digital conversion method according to claim 9, wherein a relation of a reference voltage of the successive approximation analog-to-digital converter and a voltage of a reference voltage terminal satisfies a relation of:
wherein,V R ’for the reference voltage of the successive approximation analog to digital converter,V R is the voltage at the reference voltage terminal,C os is the capacitance value of the first compensation capacitor,C G is the capacitance value of the second compensation capacitor,C 0 is the capacitance value of the 1 st sampling capacitor.
13. A sensor signal processing apparatus comprising:
the sensor is used for sensing the physical quantity and outputting an analog detection signal;
an amplifying circuit for amplifying the analog detection signal;
the analog-to-digital converter is used for converting the amplified analog detection signal into a digital detection signal; and
a digital signal processor for processing the digital detection signal;
wherein the analog-to-digital converter is a successive approximation analog-to-digital converter as claimed in any one of claims 1 to 8.
14. The sensor signal processing device of claim 13, wherein the sensor is at least one of a magnetometer, an acceleration sensor, a temperature sensor, and a humidity sensor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511032799.3A CN105680864B (en) | 2015-12-31 | 2015-12-31 | Successive approximation analog-to-digital converter, analog-to-digital conversion method, and sensing signal processing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511032799.3A CN105680864B (en) | 2015-12-31 | 2015-12-31 | Successive approximation analog-to-digital converter, analog-to-digital conversion method, and sensing signal processing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105680864A CN105680864A (en) | 2016-06-15 |
| CN105680864B true CN105680864B (en) | 2020-03-31 |
Family
ID=56190001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511032799.3A Active CN105680864B (en) | 2015-12-31 | 2015-12-31 | Successive approximation analog-to-digital converter, analog-to-digital conversion method, and sensing signal processing device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105680864B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106569162B (en) * | 2016-10-17 | 2019-04-02 | 深圳市鼎阳科技有限公司 | A kind of the analog bandwidth measurement method and device of logic analyser probe |
| EP3514963A1 (en) * | 2018-01-19 | 2019-07-24 | Socionext Inc. | Processing circuitry |
| CN108512543B (en) * | 2018-04-02 | 2021-08-31 | 中国电子科技集团公司第二十四研究所 | A low-power high-speed successive approximation logic circuit |
| CN108983413A (en) * | 2018-07-25 | 2018-12-11 | 宁波大学 | Multichannel piezoelectric deforming mirror driving power based on charge driving |
| CN111835350B (en) * | 2020-07-22 | 2021-05-04 | 珠海智融科技有限公司 | Current steering DAC buck-boost correction method and circuit |
| CN113381758B (en) * | 2021-06-18 | 2024-11-12 | 东莞市敏动电子科技有限公司 | A compensation circuit and a digital-to-analog conversion device |
| CN117439604B (en) * | 2023-12-18 | 2024-04-09 | 杭州晶华微电子股份有限公司 | Analog-to-digital converter, fully differential analog-to-digital converter and sensor measurement system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102111156A (en) * | 2011-02-18 | 2011-06-29 | 深圳市锐能微科技有限公司 | Successive approximation register analog-to-digital conversion circuit for realizing minimal dynamic range |
| CN103036564A (en) * | 2011-10-07 | 2013-04-10 | Nxp股份有限公司 | Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter |
| CN103152046A (en) * | 2012-12-27 | 2013-06-12 | 中国航空工业集团公司第六三一研究所 | Successive approximation register (SAR) analog-to-digital converter (ADC) trimming method based on charge compensation and trimming circuit |
| US8854085B1 (en) * | 2013-05-08 | 2014-10-07 | Texas Instruments Incorporated | Method and apparatus for cancellation of the second harmonic in a differential sampling circuit |
| CN205510016U (en) * | 2015-12-31 | 2016-08-24 | 杭州士兰微电子股份有限公司 | Successive approximation adc and sensor signal processing apparatus |
-
2015
- 2015-12-31 CN CN201511032799.3A patent/CN105680864B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102111156A (en) * | 2011-02-18 | 2011-06-29 | 深圳市锐能微科技有限公司 | Successive approximation register analog-to-digital conversion circuit for realizing minimal dynamic range |
| CN103036564A (en) * | 2011-10-07 | 2013-04-10 | Nxp股份有限公司 | Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter |
| CN103152046A (en) * | 2012-12-27 | 2013-06-12 | 中国航空工业集团公司第六三一研究所 | Successive approximation register (SAR) analog-to-digital converter (ADC) trimming method based on charge compensation and trimming circuit |
| US8854085B1 (en) * | 2013-05-08 | 2014-10-07 | Texas Instruments Incorporated | Method and apparatus for cancellation of the second harmonic in a differential sampling circuit |
| CN205510016U (en) * | 2015-12-31 | 2016-08-24 | 杭州士兰微电子股份有限公司 | Successive approximation adc and sensor signal processing apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105680864A (en) | 2016-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105680864B (en) | Successive approximation analog-to-digital converter, analog-to-digital conversion method, and sensing signal processing device | |
| KR101354080B1 (en) | A wide dynamic range electrometer with a fast response | |
| TWI509997B (en) | Data conversion circuitry and method therefor | |
| EP0809889B1 (en) | Analog-to-digital conversion with multiple charge redistribution conversions | |
| CN107994903B (en) | Analog-to-digital conversion circuit and pipeline analog-to-digital converter | |
| US5426431A (en) | Analog/digital converter | |
| US6414619B1 (en) | Autoranging analog to digital conversion circuitry | |
| US20130249723A1 (en) | Method and apparatus for self-test of successive approximation register (sar) a/d converter | |
| CN107346975B (en) | SAR type ADC's high accuracy calibrating device | |
| CN205510016U (en) | Successive approximation adc and sensor signal processing apparatus | |
| KR101299215B1 (en) | Method for correcting mismatch of capacitors and analog to digital converter using thereof | |
| CN109654125A (en) | Displacement correction device, magnetic suspension bearing system and displacement correction method thereof | |
| CN113970671B (en) | Capacitance detection circuit, detection method and electronic equipment | |
| CN106571824A (en) | Signal processing circuit | |
| KR20080034687A (en) | Lamp generator and its lamp signal generation method | |
| US10725118B2 (en) | Floating input detection | |
| US7030801B2 (en) | Device and method for low non-linearity analog-to-digital converter | |
| US20140035651A1 (en) | Sensor Circuit for Detecting the Setting of an Integrated Circuit | |
| CN108141219B (en) | Method for analog-to-digital conversion and analog-to-digital converter | |
| CN115361018B (en) | ADC correction circuit | |
| CN108693407B (en) | Reference resistance pair optimal impedance spectrum measurement method with minimum error | |
| CN117375621A (en) | Successive approximation analog-to-digital converter and its working method | |
| CN113064524A (en) | Touch detection system and method and display module | |
| JP2023509668A (en) | Pin strap detection circuit | |
| CN110071720B (en) | Self-calibrating full-capacitance successive approximation digital-to-analog conversion circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |