CN105704417A - Device and method of converting V-by-One image signals into LVDS (Low-Voltage Differential Signaling) image signals - Google Patents
Device and method of converting V-by-One image signals into LVDS (Low-Voltage Differential Signaling) image signals Download PDFInfo
- Publication number
- CN105704417A CN105704417A CN201610151583.7A CN201610151583A CN105704417A CN 105704417 A CN105704417 A CN 105704417A CN 201610151583 A CN201610151583 A CN 201610151583A CN 105704417 A CN105704417 A CN 105704417A
- Authority
- CN
- China
- Prior art keywords
- data
- module
- lvds
- signal
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 13
- 230000011664 signaling Effects 0.000 title abstract description 6
- 230000005540 biological transmission Effects 0.000 claims abstract description 73
- 238000006243 chemical reaction Methods 0.000 claims description 30
- 238000001514 detection method Methods 0.000 claims description 22
- 238000004458 analytical method Methods 0.000 claims description 9
- 238000011084 recovery Methods 0.000 claims description 8
- 230000011218 segmentation Effects 0.000 claims description 8
- 230000003139 buffering effect Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The invention discloses a device and a method of converting V-by-One image signals into LVDS (Low-Voltage Differential Signaling) image signals. The method comprises steps: 1) V-by-One data signals are received, and the V-by-One data signals are analyzed to obtain a V-by-One data transmission rate and information of the V-by-One data lane number; 2) according to the V-by-One data transmission rate, a receive clock for a V-by-One data lane is restored, and corrected V-by-One data signals are outputted; 3) according to the information of the V-by-One data lane number, the corrected V-by-One data signals are converted into RGB signals; 4) according to an LVDS configuration command, the RGB signals are split into multi-link RGB signals; and 5) the multi-link RGB signals are converted into multi-link LVDS image signals. Input of V-by-One signals of all specifications and standards can be supported, output of LVDS signals in multiple link transmission modes can be supported, and electrical parameters of the outputted LVDS signals are not influenced by the V-by-One signals.
Description
Technical Field
The invention relates to the technical field of image signal processing, in particular to a device and a method for converting a V-by-One image signal into an LVDS (Low Voltage differential Signaling) image signal.
Background
The V-by-One interface (mobile industry processor interface) is a novel mobile equipment display interface capable of supporting 4K, even 8K and 10K resolutions, and the interface consists of a lane (channel) data signal for transmitting image data and an auxiliary channel signal for transmitting image related state and control information (HDP hot plug information, LOCK information and the like).
However, currently, the mainstream display module in the market still stays in the interface standard of the LVDS (Low-voltage differential signaling) for various reasons such as production, technology, price, consumer acceptance, because the LVDS standard is already mature, the display effect of the image is good, and the operation is stable, and the image with various high-definition resolutions can be displayed by adopting a single link, a double link, a four link, an eight link and other multi-link transmission modes. The novel display module with the function of receiving the V-by-One signal is high in selling price, few in variety and manufacturer, and poor in display effect and stability.
Therefore, a device is needed to convert various input V-by-One image signals into LVDS image signals capable of transmitting different characteristics for displaying images on the LVDS display module.
Disclosure of Invention
Aiming at the defects of the prior art, the invention discloses a device and a method for converting a V-by-One image signal into an LVDS (Low Voltage differential Signaling) image signal, the device and the method can support the input of V-by-One signals with all specifications and standards, can output LVDS signals with various link transmission modes, and the electrical parameters of the output LVDS signals are not influenced by the V-by-One signals.
The technical scheme adopted for achieving the purpose of the invention is as follows: a device for converting a V-by-One image signal into an LVDS image signal comprises a control module, a V-by-One data signal analysis module, a V-by-OneLINK conversion module, an RGB signal conversion module, an LVDS transmission link segmentation module and an LVDS image signal conversion module, wherein the control module, the V-by-One data signal analysis module, the V-by-OneLINK conversion module, the RGB signal conversion module, the LVDS transmission link segmentation module and the LVDS image signal conversion module are arranged in a; wherein,
the V-by-One data signal analysis module is used for receiving a V-by-One data signal and analyzing the V-by-One data signal to obtain a V-by-One data transmission rate and V-by-One data channel quantity information;
the V-by-OneLINK conversion module is used for recovering a receiving clock of a V-by-One data channel according to the V-by-One data transmission rate and outputting a corrected V-by-One data signal;
the RGB signal conversion module is used for converting the corrected V-by-One data signal into an RGB signal according to the V-by-One data channel quantity information;
the LVDS transmission link division module is used for dividing the RGB signals into multilink RGB signals;
the LVDS image signal conversion module is used for converting the multilink RGB signals into multilink LVDS image signals;
the control module is used for realizing the transmission and the issuing of the control instructions of all the functional modules in the programmable logic device.
Preferably, in the above scheme, the LVDS image signal conversion module configures the output multi-link LVDS image signal according to configuration parameters such as the number of links, a transmission coding mode, a color level bit, a transmission driving capability, pre-emphasis and the like issued by the control module.
In addition, the invention also provides a method for converting the V-by-One image signal into the LVDS image signal, which comprises the following steps:
step 1: receiving a V-by-One data signal, and analyzing the V-by-One data signal to obtain a V-by-One data transmission rate and V-by-One data channel quantity information;
step 2: recovering a receiving clock of a V-by-One data channel according to the V-by-One data transmission rate, and outputting a corrected V-by-One data signal;
and step 3: converting the corrected V-by-One data signal into an RGB signal according to the V-by-One data channel quantity information;
and 4, step 4: dividing the RGB signals into multilink RGB signals according to LVDS configuration commands;
and 5: and converting the multilink RGB signals into multilink LVDS image signals.
The invention has the following advantages:
(1) the invention can convert the input V-by-One image signal into LVDS image signals in various link transmission modes.
(2) The invention can support the input of all standard V-by-One image signals with all specifications and can automatically identify the data channel number and the data transmission rate of the V-by-One image signals.
(3) Relevant control parameters (such as LVDSlink number, VESAIDA transmission coding mode, LVDS color level bit, transmission driving capability, pre-emphasis and the like) of the LVDS image signals output by the invention can be set by upper-layer software, are irrelevant to the input V-by-One image signals, and the electrical parameters of the output LVDS image signals are not influenced by the input V-by-One image signals.
Drawings
FIG. 1 is a block diagram of a device for converting V-by-One image signals into LVDS image signals according to the present invention.
FIG. 2 is a flowchart of a method for converting a V-by-One image signal into an LVDS image signal according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the specific embodiments.
The programmable logic device of the embodiment adopts an FPGA.
As shown in FIG. 1, the device for converting a V-by-One image signal into an LVDS image signal disclosed by the invention comprises a control module (1), a V-by-One auxiliary signal analysis module (2), a V-by-One data signal analysis module (3), a V-by-OneLINK conversion module (4), an RGB signal conversion module (5), an LVDS transmission link segmentation module (6), an LVDS image signal conversion module (7), a V-by-One hot plug detection module (8) and a transmission sequence synchronization module (9) which are arranged in an FPGA chip, the V-by-One hot plug detection module (8) is connected with an external V-by-One image signal source, the LVDS image signal conversion module (7) is connected with the LVDS module to be detected, and the control module (1) is connected with the upper computer.
In the above embodiment, the V-by-One auxiliary signal parsing module (2) includes a V-by-One auxiliary channel termination matching module, a physical layer transmission decoding module, and an information decoding module; the V-by-One data signal analysis module (3) comprises a V-by-One data channel termination matching module, a data channel number detection module and a transmission rate detection module; the V-by-OneLINK conversion module (4) comprises a data channel clock recovery module and a serial-to-parallel processing module; the RGB signal conversion module (5) comprises an image data decoding module, an image packet header analyzing module, an RGB image data packet decoding module, an RGB image time sequence generating module, an RGB image data caching module and an RGB image generating module; the LVDS transmission link segmentation module (6) comprises an RGB signal buffer module, an LVDS data link segmentation module and an LVDS image transmission coding module; the LVDS image signal conversion module (7) comprises an LVDS image transmission serialization module and an LVDS image signal output module; the transmission sequence synchronization module (9) comprises an image transmission synchronization sequence detection module and an image receiving synchronization module.
The signal conversion process of the above embodiment is further described with reference to fig. 2.
In the above embodiment, the upper computer issues the LVDS transmission configuration parameters and the LVDS timing configuration parameters to the control module (1) after the apparatus of the present invention is powered on.
In the above embodiment, the V-by-One hot plug detection module (8) is configured to receive a V-by-One auxiliary signal and a V-by-One data signal input by an external V-by-One image signal source, and detect a connection state of the V-by-One auxiliary signal and the V-by-One data signal and feed back the connection state to the control module (1) in real time, when the connection state of the V-by-One auxiliary signal and the V-by-One data signal is normal, the control module (1) may start other function modules to perform corresponding signal conversion operations, otherwise may stop the signal conversion operations of the other function modules, thereby preventing an external clutter signal from being introduced into the apparatus of the present invention to cause interference on output of an LVDS signal.
In the embodiment, after the V-by-One hot plug detection module (8) receives the V-by-One auxiliary signal and the V-by-One data signal, the V-by-One auxiliary signal is sent to the V-by-One auxiliary channel termination matching module, and the V-by-One data signal is sent to the V-by-One data channel termination matching module.
In the above embodiment, the V-by-One auxiliary channel termination matching module performs termination matching on the V-by-One auxiliary signal, so that the optimal V-by-One auxiliary signal is received and then sent to the physical layer transmission decoding module to perform physical decoding operation, data such as HDP hot plug information and LOCK information is captured, and then the data is sent to the information decoding module to be analyzed, so that the HDP hot plug information and the LOCK information are obtained and then sent to the control module (1). The V-by-One data channel termination matching module carries out termination matching and balancing operation on the V-by-One data signals, so that the optimal V-by-One data signals are respectively sent to the data channel number detection module, the transmission rate detection module, the data channel clock recovery module and the image transmission synchronous sequence detection module after being received, the data channel number detection module detects the number of the data channels of the sent signals, and the detection result is sent to the control module (1); meanwhile, the transmission rate detection module detects the data transmission rate of the sent signal and sends the detection result to the control module (1). Because different data transmission rates correspond to different V-by-One signal standards, the device can automatically identify V-by-One image signals of different V-by-One standards.
In the above embodiment, the image transmission synchronization sequence detection module detects the transmission sequence of the received V-by-One data signal, compares the transmission sequence with the transmission sequence issued by the control module (1), and when the transmission sequence of the V-by-One image data packet does not conform to the transmission sequence issued by the control module (1), the image reception synchronization module performs synchronization processing on the V-by-One data signal, and feeds back synchronization processing information to the data channel clock recovery module and the serial-to-parallel processing module through the control module (1).
In the above embodiment, after the data channel clock recovery module receives the V-by-One data signal sent by the V-by-One data channel termination matching module, the control module (1) sends the data transmission rate and the synchronous processing information fed back by the transmission rate detection module to the data channel clock recovery module, the data channel clock recovery module recovers the receiving clock of each data channel of the V-by-One according to the data transmission rate and the synchronous processing information, each data channel of the V-by-One recovers the transmission data in each data channel of the V-by-One according to the receiving clock (thereby overcoming the distortion of the data in the transmission process) and outputs the corrected V-by-One data signal to the serial-to-parallel processing module.
And the serial-to-parallel processing module converts the received corrected V-by-One data signal into parallel V-by-oneLINK data according to the synchronous processing information fed back by the control module (1) and sends the parallel V-by-oneLINK data to the image data decoding module. The image data unpacking module unpacks the received parallel V-by-OneLINK data to obtain packet header information and image data in the packet, and sends the packet header information and the image data to the image packet header analyzing module and the RGB image data packet decoding module respectively. The image packet header analysis module analyzes the data packet header to obtain decoding information of the data packet header and command words and sends the decoding information and the command words into the control module (1), the control module (1) controls the RGB image data packet decoding module to complete V-by-One data decoding operation according to the command words, the decoding information and the number of V-by-One data channels, RGB image data are obtained and then sent into the RGB image data caching module to be cached, meanwhile, the control module (1) sends LVDS time sequence parameters to the RGB image time sequence generation module, and the RGB image time sequence generation module generates corresponding RGB time sequence signals (VSync, HSync and DE) according to the LVDS time sequence parameters and sends the RGB image data into the RGB image generation module. Under the control of the RGB time sequence signal, the RGB image generation module takes out the image data cached by the RGB image data caching module, so that the image data is output into a standard RGB image signal and sent into the RGB signal caching module for caching.
In the above embodiment, the LVDS data link division module reads the RGB image signals of the RGB signal buffer module according to the LVDS link number issued by the control module (1) to perform link division processing, and synchronously divides the RGB timing signals to each data link. The LVDS image transmission encoding module encodes the multilink RGB signal according to an LVDS transmission encoding mode (such as VESA, JEIDA) issued by the control module (1) and a color gradation bit (6bit, 8bit, 10bit and 12bit) and outputs multilink LVDS encoding data.
In the above embodiment, the LVDS image transmission serialization module serializes the multilink LVDS encoded data according to the LVDS transmission parameters (such as the LVDS clock transmission bit mode, the LVDS transmission serialization factor, etc.) issued by the control module (1), and outputs a multilink LVDS image signal; the LVDS image signal output module adjusts the multilink LVDS image signals according to LVDS transmission parameters (such as LVDS driving strength, LVDS pre-emphasis, LVDS output impedance, LVDS output delay and the like) issued by the control module (1), and outputs the adjusted multilink LVDS image signals to the LVDS module to be tested.
Details not described in this specification are within the skill of the art that are well known to those skilled in the art. It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A device for converting a V-by-One image signal into an LVDS image signal is characterized by comprising a control module (1), a V-by-One data signal analysis module (3), a V-by-One LINK conversion module (4), an RGB signal conversion module (5), an LVDS transmission link segmentation module (6) and an LVDS image signal conversion module (7) which are arranged in a programmable logic device; wherein,
the V-by-One data signal analysis module (3) is used for receiving the V-by-One data signal and analyzing the V-by-One data signal to obtain the V-by-One data transmission rate and the V-by-One data channel number information;
the V-by-OneLINK conversion module (4) is used for recovering a receiving clock of a V-by-One data channel according to the V-by-One data transmission rate and outputting a corrected V-by-One data signal;
the RGB signal conversion module (5) is used for converting the corrected V-by-One data signal into an RGB signal according to the V-by-One data channel quantity information;
the LVDS transmission link division module (6) is used for dividing the RGB signals into multi-link RGB signals;
the LVDS image signal conversion module (7) is used for converting the multilink RGB signals into multilink LVDS image signals;
the control module (1) is used for realizing the transmission and the issuing of the control instructions of all the functional modules in the programmable logic device.
2. The apparatus for converting V-by-One image signal into LVDS image signal according to claim 1, wherein the V-by-One data signal parsing module (3) includes a V-by-One data channel termination matching module, a transmission rate detection module and a data channel number detection module; wherein,
the V-by-One data channel termination matching module is used for carrying out termination matching on the V-by-One data signals;
the transmission rate detection module is used for detecting the matched V-by-One data signal to obtain the V-by-One data transmission rate;
the data channel quantity detection module is used for detecting the matched V-by-One data signals to obtain the V-by-One data channel quantity information.
3. The apparatus for converting V-by-One image signals into LVDS image signals according to claim 2, wherein the V-by-OneLINK conversion module (4) includes a data channel clock recovery module and a serial to parallel processing module; wherein,
the data channel clock recovery module receives the matched V-by-One data signal, recovers a receiving clock of the V-by-One data channel according to the V-by-One data transmission rate, and outputs a corrected V-by-One data signal;
the serial-to-parallel processing module is used for converting the corrected V-by-One data signal into parallel V-by-oneLINK data; and the RGB signal conversion module (5) converts the parallel V-by-OneLINK data into RGB signals according to the V-by-One data channel quantity information.
4. The apparatus for converting a V-by-One image signal into an LVDS image signal according to claim 1, wherein the LVDS transmission link segmentation module (6) includes an RGB signal buffer module, an LVDS data link segmentation module and an LVDS image transmission encoding module; wherein,
the RGB signal buffer module is used for buffering the RGB signals;
the LVDS data link division module is used for dividing the RGB signals into multilink RGB signals;
the LVDS image transmission encoding module is used for encoding the multilink RGB signals and outputting multilink LVDS encoding data.
5. The apparatus for converting a V-by-One image signal into an LVDS image signal according to claim 4, wherein the LVDS image signal conversion module (7) includes an LVDS image transmission serialization module and an LVDS image signal output module; wherein,
the LVDS image transmission serialization module is used for performing serialization processing on the multilink LVDS coding data and outputting multilink LVDS image signals;
the LVDS image signal output module is used for adjusting the transmission quality of the multilink LVDS signal and outputting the adjusted multilink LVDS image signal.
6. The apparatus for converting V-by-One image signal into LVDS image signal according to claim 2, further comprising a transmission sequence synchronization module (9) disposed in the programmable logic device, wherein the transmission sequence synchronization module (9) is configured to detect a transmission sequence of the matched V-by-One data signal, perform synchronization processing on the matched V-by-One data signal, and feed back synchronization processing information to the V-by-One link conversion module (4) through the control module (1).
7. The apparatus for converting V-by-One image signal into LVDS image signal according to claim 1, further comprising a V-by-One hot plug detection module (8) disposed in the programmable logic device, wherein the V-by-One hot plug detection module (8) is configured to input the V-by-One data signal and feed back an input status of the V-by-One data signal to the control module (1) in real time.
8. A method for converting a V-by-One image signal into an LVDS image signal is characterized by comprising the following steps:
step 1: receiving a V-by-One data signal, and analyzing the V-by-One data signal to obtain a V-by-One data transmission rate and V-by-One data channel quantity information;
step 2: recovering a receiving clock of a V-by-One data channel according to the V-by-One data transmission rate, and outputting a corrected V-by-One data signal;
and step 3: converting the corrected V-by-One data signal into an RGB signal according to the V-by-One data channel quantity information;
and 4, step 4: dividing the RGB signals into multilink RGB signals according to LVDS configuration commands;
and 5: and converting the multilink RGB signals into multilink LVDS image signals.
9. The method for converting a V-by-One image signal into an LVDS image signal according to claim 8, wherein the step 3 further comprises:
(31) converting the corrected V-by-One data signal into parallel V-by-oneLINK data;
(32) and converting the parallel V-by-OneLINK data into RGB signals according to the V-by-One data channel quantity information.
10. The method of converting a V-by-One image signal into an LVDS image signal according to claim 8, wherein the step 5 further comprises the steps of:
(41) encoding the multilink RGB signal and outputting multilink LVDS encoded data;
(42) and performing serialization processing on the multilink LVDS coded data and outputting multilink LVDS image signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610151583.7A CN105704417B (en) | 2016-03-17 | 2016-03-17 | V-by-One picture signals are converted into the device and method of LVDS picture signals |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610151583.7A CN105704417B (en) | 2016-03-17 | 2016-03-17 | V-by-One picture signals are converted into the device and method of LVDS picture signals |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105704417A true CN105704417A (en) | 2016-06-22 |
| CN105704417B CN105704417B (en) | 2018-11-02 |
Family
ID=56221682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610151583.7A Active CN105704417B (en) | 2016-03-17 | 2016-03-17 | V-by-One picture signals are converted into the device and method of LVDS picture signals |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105704417B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108206017A (en) * | 2018-01-25 | 2018-06-26 | 广州晶序达电子科技有限公司 | Improve the method and system that liquid crystal display panel jumps screen |
| CN113688080A (en) * | 2021-10-26 | 2021-11-23 | 长芯盛（武汉）科技有限公司 | DP signal transmission device and method for improving transmission link compatibility |
| CN114040151A (en) * | 2021-09-28 | 2022-02-11 | 惠州华阳通用电子有限公司 | Decoding method and device for panoramic all-around system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103198807A (en) * | 2013-04-12 | 2013-07-10 | 深圳市华星光电技术有限公司 | Display signal processing system and circuit board and liquid crystal display device |
| CN104363405A (en) * | 2014-10-31 | 2015-02-18 | 深圳创维－Rgb电子有限公司 | Ultrahigh-definition signal conversion device and conversion method thereof |
| US9009379B1 (en) * | 2014-01-10 | 2015-04-14 | Lattice Semiconductor Corporation | Communicating with MIPI-compliant devices using non-MIPI interfaces |
| CN204652546U (en) * | 2015-06-05 | 2015-09-16 | 武汉精测电子技术股份有限公司 | For LVDS being converted to the system of V-BY-ONE vision signal |
-
2016
- 2016-03-17 CN CN201610151583.7A patent/CN105704417B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103198807A (en) * | 2013-04-12 | 2013-07-10 | 深圳市华星光电技术有限公司 | Display signal processing system and circuit board and liquid crystal display device |
| US9009379B1 (en) * | 2014-01-10 | 2015-04-14 | Lattice Semiconductor Corporation | Communicating with MIPI-compliant devices using non-MIPI interfaces |
| CN104363405A (en) * | 2014-10-31 | 2015-02-18 | 深圳创维－Rgb电子有限公司 | Ultrahigh-definition signal conversion device and conversion method thereof |
| CN204652546U (en) * | 2015-06-05 | 2015-09-16 | 武汉精测电子技术股份有限公司 | For LVDS being converted to the system of V-BY-ONE vision signal |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108206017A (en) * | 2018-01-25 | 2018-06-26 | 广州晶序达电子科技有限公司 | Improve the method and system that liquid crystal display panel jumps screen |
| CN108206017B (en) * | 2018-01-25 | 2020-08-11 | 广州晶序达电子科技有限公司 | Method and system for improving screen jumping of liquid crystal panel |
| CN114040151A (en) * | 2021-09-28 | 2022-02-11 | 惠州华阳通用电子有限公司 | Decoding method and device for panoramic all-around system |
| CN114040151B (en) * | 2021-09-28 | 2023-11-21 | 惠州华阳通用电子有限公司 | Panoramic looking-around system decoding method and device |
| CN113688080A (en) * | 2021-10-26 | 2021-11-23 | 长芯盛（武汉）科技有限公司 | DP signal transmission device and method for improving transmission link compatibility |
| CN113688080B (en) * | 2021-10-26 | 2022-01-21 | 长芯盛（武汉）科技有限公司 | DP signal transmission device and method for improving transmission link compatibility |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105704417B (en) | 2018-11-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105704418B (en) | MIPI picture signals are converted into the device and method of LVDS picture signals | |
| CN105812702B (en) | A kind of DP picture signal is converted into the device and method of LVDS picture signal | |
| CN105491318B (en) | A kind of DP vision signal single channel turns the device and method of multichannel | |
| CN105491373B (en) | A kind of LVDS vision signals single channel turns the device and method of multichannel | |
| CN103475842A (en) | Method for converting LVDS video signals into MIPI video signals | |
| TWI395476B (en) | Method and related device for determining timing sequence of video and audio data for high density multimedia interface | |
| CN105472288A (en) | Device and method for single-path to multiple-path conversion of V-BY-ONE video signals | |
| CN105812703B (en) | HDMI video signal is converted into the device and method of LVDS vision signal | |
| CN107205176B (en) | A signal conversion device and conversion method | |
| CN105023549A (en) | Resolution-adaptive MIPI (mobile industry processor interface) graph signal generation device and method | |
| CN105405375B (en) | A kind of MIPI vision signals single channel turns the device and method of multichannel | |
| CN103475840A (en) | Method for switching four-LINK LVDS video signals into MIPI video signals | |
| CN104469351B (en) | A kind of method of LVDS vision signals caused by detection video source | |
| CN104469354A (en) | Device for detecting quality of MIPI video signals | |
| CN104967844A (en) | Automatic LVDS (Low Voltage Differential Signaling) video signal testing method and device | |
| CN105704417B (en) | V-by-One picture signals are converted into the device and method of LVDS picture signals | |
| CN104469353B (en) | A kind of device detecting LVDS video signal quality | |
| CN105472287A (en) | Device and method for single-path to multiple-path conversion of single path of HDMI video signals | |
| CN104954723A (en) | Method and system for converting LVDS (low-voltage differential signaling) video signals into 1LANE DP (display port) video signals | |
| CN104575351A (en) | Signal conversion system, displayer and signal conversion method | |
| CN201898573U (en) | FPGA (field programmable gate array) component capable of realizing DVI (digital video interactive) coding and decoding | |
| CN103475843A (en) | Method for converting double-LINK LVDS video signals into MIPI video signals | |
| CN203504677U (en) | Device for converting LVDS video signal into MIPI video signal | |
| CN104967808A (en) | Method and system converting LVDS video signals to 2LANE DP video signals | |
| CN105049773A (en) | Method of transforming LVDS video signal into DP video signal and system of transforming LVDS video signal into DP video signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 430070 Hubei City, Hongshan Province, South Lake Road, No. 53, Hongshan Venture Center, building on the 4 floor, No. Applicant after: Wuhan fine test electronics group Limited by Share Ltd Address before: 430070 Hubei City, Hongshan Province, South Lake Road, No. 53, Hongshan Venture Center, building on the 4 floor, No. Applicant before: Wuhan Jingce Electronic Technology Co., Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |