CN105702672B - Semiconductor device with a plurality of semiconductor chips - Google Patents

Abstract

The present invention discloses a semiconductor device, including a metal oxide semiconductor and a bipolar junction structure formed in a substrate. The metal oxide semiconductor structure includes a first region, a second region, a third region and a fourth region. The first, second and fourth regions are of the first conductivity type, and are the drain region, the drain electrode and the source region of the metal oxide semiconductor structure. The doping degree of the second region is higher than that of the first region. The third region is of the second conductivity type, and includes a channel and a body region of the metal oxide semiconductor structure. The channel region is formed between the first and fourth regions. The bipolar junction structure includes a fifth region formed on the first region, the fifth region contacts the second region and is of the second conductivity type. The second, third and fifth regions are the base, collector and emitter regions of the bipolar junction structure, respectively.

Description

Semiconductor device

technical field

The present invention relates to a semiconductor device, and more particularly to an electrostatic discharge (ESD) protection device.

Background technique

Bipolar-Complementary Metal-Oxide-Semiconductor (CMOS)-Double-Diffused Metal-Oxide Semiconductor (DMOS) (BCD) and Triple Well processes have been widely used in high voltage applications such as ESD protection. In general, the ESD performance of a high-voltage ESD protection device depends on the overall width of the gate of the device, as well as the surface and lateral rules of the device. For smaller-sized high-voltage ESD protection devices, the surface-volume ratio (surface-bulk ratio) is larger than that of larger-sized high-voltage ESD protective devices, so the smaller-sized high-voltage ESD protective device Surface area has a greater impact than the surface area of larger sized high voltage ESD protection devices. Therefore, it is more challenging to achieve good ESD performance in relatively small-sized devices. In addition, on-chip ESD protection design becomes more challenging as the operating voltage of the device increases.

High voltage ESD protection devices usually have low on-state resistance (RDS-on). When electrostatic discharge occurs, the electrostatic discharge current tends to concentrate on the surface or near the drain of the high voltage protection device. This results in higher current densities and electric fields in surface junction regions and physical damage to these regions during ESD. Therefore, the surface area of a high voltage protection device has a greater influence on its surface than a device with a larger on-resistance, that is, the surface and lateral dimensions play a rather important role in a high voltage protection device.

Other properties of the high voltage protection device include, for example, a high breakdown voltage, which is always higher than the operating voltage of the high voltage protection device. Furthermore, the driving voltage (V _t1 ) of high voltage devices is usually much higher than the breakdown voltage. Therefore, during ESD, the device or the protected internal circuit (also referred to herein as "protected device/circuit") may be at risk of damage before the high voltage protection device is turned on to provide ESD protection.

High voltage protection devices usually have a low holding voltage, which may cause the high voltage protection device to be damaged by unwanted noise, power-on peak voltage, or surge voltage. trigger. Therefore, latch-up may occur during normal operation.

In addition, there may be a field plate effect in the high voltage protection device. That is to say, the electric field distribution in the high voltage protection device is quite sensitive to the wiring paths of different components or different parts of the connection device. Therefore, electrostatic discharge current tends to concentrate on the surface or near the drain of the high-voltage device.

Contents of the invention

According to the present invention, a semiconductor structure is provided, including a substrate, a metal oxide semiconductor structure and a bipolar junction structure, and the metal oxide semiconductor structure and the bipolar junction structure are formed in the substrate. The metal oxide semiconductor structure includes a first semiconductor region, a second semiconductor region, a third semiconductor region and a fourth semiconductor region. The first semiconductor region has a first conductivity type and a first doping level. The second semiconductor region is formed on the first semiconductor region and has a first conductivity type and a second doping degree, and the second doping degree is higher than the first doping degree. The third semiconductor region has a second conductivity type. The fourth semiconductor region is formed on the third semiconductor region and has the first conductivity type. The first semiconductor region, the second semiconductor region and the fourth semiconductor region are respectively the drain region, the drain electrode and the source region of the metal oxide semiconductor structure. The third semiconductor region includes a channel region and a body region of the metal oxide semiconductor structure. The channel region is formed between the first semiconductor region and the fourth semiconductor region. The bipolar junction structure includes a fifth semiconductor region formed on the first semiconductor region and in contact with the second semiconductor region. The fifth semiconductor region has a second conductivity type and is an emitter region of a bipolar junction structure. The second semiconductor region and the third semiconductor region are respectively the base region and the collector region of the bipolar junction structure.

According to the present invention, a semiconductor structure is provided, including a substrate, a metal oxide semiconductor structure and a bipolar junction structure, and the metal oxide semiconductor structure and the bipolar junction structure are formed in the substrate. The metal oxide semiconductor structure includes a drain region, a drain electrode, a channel region, a body region and a source region. The bipolar junction structure includes an emitter region, a base region and a collector region. The source region and the base region share a first common semiconductor region in the substrate, and the body region and the collector region share a second common semiconductor region in the substrate.

According to the present invention, a semiconductor structure is proposed, including a substrate, a first well, a first highly doped region, a second well, a second highly doped region and a third highly doped region . The first well is formed in the substrate. The first high-concentration doped region is formed in the first well. A second well is formed in the substrate adjacent to the first well. The second high-concentration doped region is formed in the second well. The third high-concentration doped region is formed in the first well. The first well has a first conductivity type and a first doping level. The first highly doped region has a first conductivity type and a second doping level, and the second doping level is higher than the first doping level. The second well has a second conductivity type and a third doping level. The second high-concentration doped region has a first conductivity type and a fourth doping level, and the fourth doping level is higher than the first doping level. The third high-concentration doped region has the second conductivity type and a fifth doping degree, and the fifth doping degree is higher than the third doping degree. The third high-concentration doped region contacts the first high-concentration doped region.

Some of the features and advantages of the present invention will be described later, and some will be obvious from the following description or can be learned from examples of the present invention. These features and advantages will be understood or obtained by means of the elements and combinations pointed out in the scope of the appended claims.

It should be understood that the foregoing general description and the following detailed description are examples or illustrations only, and are not intended to limit the present invention.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples, together with the accompanying drawings, are described in detail as follows:

Description of drawings

FIG. 1 shows an equivalent circuit of a high voltage electrostatic discharge protection device according to an embodiment of the present invention.

2A and 2B are partial plan and cross-sectional schematic diagrams of an electrostatic discharge protection device according to an embodiment of the present invention, respectively.

FIG. 3 is a schematic cross-sectional view of an ESD protection device according to another embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a conventional ESD protection device.

5A and 5B are current-voltage diagrams of a conventional ESD protection device and an ESD protection device according to an embodiment of the present invention.

6A and 6B are transmission line pulse diagrams of a conventional ESD protection device and an ESD protection device according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of electrical safety operation zones of a traditional ESD protection device and an ESD protection device according to an embodiment of the present invention.

【Symbol Description】

100, 200, 300: electrostatic protection device

102: Metal Oxide Semiconductor Structure

102-a: First Metal Oxide Semiconductor Structure

102-b: Second Metal Oxide Semiconductor Structure

102-2: Drain

102-4: Gate

102-6: Source

102-8: Ontology

104: Bipolar Junction Structure

104-a: First Bipolar Junction Structure

104-b: Second bipolar junction structure

104-2: Emitter

104-4: Base

104-6: collector

106, 108: terminal

110: Internal circuit

202: P-type substrate

204: High voltage N-type well

204-1: First high voltage N-type well section

204-2: Second high voltage N-type well section

206: P-type well

206-1: Middle part of P-type well

206-2: First P-type well side part

206-3: P-type well bottom part

206-4: Second P-type well side part

208-1: The first N-type well

208-2: Second N-type well

210-1: the first highly doped N-type region

210-2: The second high concentration doped N-type region

212: The third high-concentration doped N-type region

214: the fourth high-concentration doped N-type region

216: the first high-concentration doped P-type region

218: Continuous high concentration doped N-type semiconductor region

220-1: Second high concentration doped P-type region

220-2: The third high-concentration doped P-type region

222-1: First polysilicon layer

222-2: second polysilicon layer

224-1: first thin oxide layer

224-2: second thinnest oxide layer

226-1: First gate contact

226-2: Second gate contact

302-1: The first shallow N-type well

302-2: The second shallow N-type well

400: Traditional electrostatic discharge device

I _DS : represents the drain current

V _DS : represents the drain voltage

Detailed ways

Embodiments of the present invention include a high voltage electrostatic discharge (ESD) protection device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

FIG. 1 shows an equivalent circuit of a high-voltage (high-voltage, HV) ESD protection device 100 according to an embodiment of the present invention. The ESD protection device 100 includes a metal-oxide-semiconductor (MOS) structure 102 and a bipolar junction (BJ) structure 104 , the two structures are formed in one device. As described below, the metal oxide semiconductor structure 102 and the bipolar junction structure 104 are electrically coupled to each other without the use of metal wires. In the embodiment shown in FIG. 1, the metal oxide semiconductor structure 102 includes a high voltage N-channel metal oxide semiconductor structure (NMOS), and the bipolar junction structure 104 includes a PNP bipolar junction structure (here , "N" and "P" represent N-type conductivity and P-type conductivity respectively).

In the equivalent circuit shown in FIG. 1 , the metal oxide semiconductor structure 102 includes a drain 102 - 2 , a gate 102 - 4 , a source 102 - 6 and a body 102 - 8 . The bipolar junction structure 104 includes an emitter 104-2, a base 104-4, and a collector 104-6. Drain 102-2 of MOS structure 102 and emitter 104-2 of bipolar junction structure 104 are electrically coupled to each other and to terminal 106 which may be connected to a power supply (terminal 106 may also be referred to as "power supply terminals"). The source 102-6 of the MOS structure 102 and the collector 104-6 of the bipolar junction structure 104 are electrically coupled to each other and to a terminal 108 connectable to a circuit ground ( Terminal 108 may also be referred to as a "circuit ground terminal"). The base 104-4 of the bipolar junction structure 104 is electrically coupled to the terminal 106 through a resistor, which may be an internal resistance in the semiconductor substrate forming the metal oxide semiconductor structure 102 and the bipolar junction structure 104. . As shown in FIG. 1 , the gate 102 - 4 of the metal oxide semiconductor structure 102 is electrically coupled to an internal circuit 110 , and the internal circuit 110 is protected by an ESD protection device 100 .

In the equivalent circuit shown in FIG. 1 , the drain 102 - 2 of the metal oxide semiconductor structure 102 and the base 104 - 4 of the bipolar junction structure 104 are electrically coupled to each other. As described later in the embodiment of the present invention, the base 104-4 of the bipolar junction structure 104 can also be used as a drain electrode of the metal oxide semiconductor structure 102, for example, the base 104-4 of the bipolar junction structure 104 The drain electrode of the metal oxide semiconductor structure 102 physically shares a common region in the ESD protection device 100 . In addition, the body 102 - 8 of the metal oxide semiconductor structure 102 and the collector 104 - 6 of the bipolar junction structure 104 are electrically coupled to each other. As described later in the embodiment of the present invention, the body 102 - 8 of the metal oxide semiconductor structure 102 and the collector 104 - 6 of the bipolar junction structure 104 physically share another shared area in the ESD protection device 100 .

FIG. 2A is a partial plan view of an ESD protection device 200 according to an embodiment of the present invention. The ESD protection device 200 has an equivalent circuit corresponding to that shown in FIG. 1 . Therefore, the same reference numerals 102 and 104 are used to represent the metal oxide semiconductor structure and the bipolar junction structure of the ESD protection device 200 . FIG. 2B is a cross-sectional view of the ESD protection device 200 taken along the line AA' in FIG. 2A .

2A and 2B, the ESD protection device 200 includes a P-type substrate 202, a high-voltage N-type well (high-voltage N-well) 204 and a P-type well (P-well) 206, and the high-voltage N-type well 204 is formed on the P-type well. In the substrate 202 , a P-type well 206 is formed in a high voltage N-type well 204 .

The ESD protection device 200 also includes a first N-type well 208 - 1 and a second N-type well 208 - 2 electrically coupled to the high voltage N-type well 204 . The first N-type well 208-1 and the second N-type well 208-2 are roughly arranged relative to a middle part 206-1 of the P-type well 206 (hereinafter also referred to as "P-type well middle part 206-1"). symmetrical to each other. A first heavily doped N-type (N ⁺ ) region 210-1 and a second heavily doped N-type region 210-2 are respectively formed in the first N-type well 208-1 and the second N-type well 208-1. In or on the type well 208-2. The first heavily doped N-type region 210-1 and the second highly doped N-type region 210-2 are electrically coupled to the first N-type well 208-1 and the second N-type well 208-2 respectively, and opposite to each other. They are roughly arranged symmetrically in the middle part 206-1 of the P-type well.

The ESD protection device 200 further includes a third heavily doped N-type region 212, a fourth highly doped N-type region 214 and a first highly doped P-type (P ⁺ ) region 216 formed on the P-type Well 206. The third heavily doped N-type region 212 and the fourth highly doped N-type region 214 are approximately symmetrically arranged relative to the P-type well middle portion 206 - 1 . Consistent with the embodiment of the present invention and as shown in FIG. 2A , the third heavily doped N-type region 212 and the fourth highly doped N-type region 214 are part of a continuous highly doped N-type semiconductor region 218 , continuous The heavily doped N-type semiconductor region 218 is formed in the P-type well 206 . The first highly doped P-type region 216 is formed in the continuous highly doped N-type semiconductor region 218 . In the present invention, the first highly doped P-type region 216 can be formed in any form through the continuous highly doped N-type semiconductor region 218 , and physically and electrically contacts the P-type well 206 .

As shown in FIG. 2A and FIG. 2B , the ESD protection device 200 further includes a second highly doped P-type region 220-1 and a third highly doped P-type region 220-2, which are respectively formed on the first high The concentration doped N-type region 210-1 and the second high concentration doped N-type region 210-2 are located on the N-type wells 208-1 and 208-2 respectively. In some embodiments, as shown in FIG. 2B , the second highly doped P-type region 220-1 and the third highly doped P-type region 220-2 can be formed in any form through the first highly doped P-type region. The doped N-type region 210-1 and the second highly doped N-type region 210-2.

In the electrostatic discharge protection device 200, the P-type substrate 202 can be a P-type chip (such as a P-type silicon chip), a P-type layer epitaxially grown on the growth substrate, or silicon on a P-type insulator ( silicon-on-insulator) substrate. The impurity concentration in the P-type substrate 202 is, for example, about 1×10 ¹⁰ cm ⁻³ to 1×10 ¹⁵ cm ⁻³ . In some embodiments, the high-voltage N-type well 204 can be formed by injecting N-type impurities, such as antimony, arsenic, or phosphorous, into the P-type substrate 202 by, for example, ion implantation. form. In some embodiments, the high voltage N-type well 204 can be formed by epitaxially growing an N-type semiconductor layer on the P-type substrate. The high voltage N-type well 204 may also include a plurality of N-type buried layer stacks. In some embodiments, the impurity concentration in the high voltage N-type well 204 is, for example, about 1×10 ¹⁰ cm ⁻³ to 1×10 ¹⁶ cm ⁻³ .

The P-type well 206 can be formed by injecting P-type impurities, such as boron, aluminum or gallium, into the high-voltage N-type well 204 by, for example, ion implantation. The P-type well 206 may also include multiple P-type buried layer stacks. In some embodiments, the impurity concentration in the P-type well 206 is, for example, about 1×10 ¹² cm ⁻³ to 1×10 ²⁰ cm ⁻³ .

The first N-type well 208 - 1 and the second N-type well 208 - 2 can be formed by introducing other N-type impurities into the high-voltage N-type well 204 . Therefore, the impurity concentrations in the first N-type well 208 - 1 and the second N-type well 208 - 2 are higher than the impurity concentrations in the high voltage N-type well 204 . In some embodiments, the impurity concentrations in the first N-type well 208-1 and the second N-type well 208-2 are about 1×10 ¹⁰ cm ⁻³ to 1×10 ¹⁶ cm ⁻³ . The first highly-doped N-type region 210-1 and the second highly-doped N-type region 210-2 can enter the first N-type well 208-1 and the second N-type well 208 respectively by other N-type impurities. Formed in -2. In some embodiments, the impurity concentrations in the first heavily doped N-type region 210-1 and the second highly doped N-type region 210-2 are about 1×10 ¹⁵ cm ⁻³ to 1×10 ²⁰ cm ^-3 .

The third highly doped N-type region 212 and the fourth highly doped N-type region 214 (or the continuous highly doped N-type region 218 ) can be formed by entering N-type impurities into the P-type well 206 . In some embodiments, the impurity concentrations in the third highly doped N-type region 212 and the fourth highly doped N-type region 214 are about 1×10 ¹⁵ cm ⁻³ to 1×10 ²⁰ cm ⁻³ . In some embodiments, the first heavily doped N-type region 210-1, the second highly doped N-type region 210-2, the third highly doped N-type region 212 and the fourth highly doped N-type region The N-type region 214 is formed in the same doping step, for example, in the same ion implantation step.

The first highly doped P-type region 216 can be formed by introducing P-type impurities into the continuous highly doped N-type region 218 . In some embodiments, the impurity concentration in the first heavily doped P-type region 216 is about 1×10 ¹⁵ cm ⁻³ to 1×10 ²⁰ cm ⁻³ . Similarly, the second highly-doped P-type region 220-1 and the third highly-doped P-type region 220-2 can be obtained by respectively entering the P-type impurities into the continuous first highly-doped N-type region 210-1 and The second high concentration doping is formed in the N-type region 210-2. In some embodiments, the impurity concentrations in the second heavily doped P-type region 220-1 and the third highly doped P-type region 220-2 are about 1×10 ¹⁵ cm ⁻³ to 1×10 ²⁰ cm ^-3 . In some embodiments, the first heavily doped P-type region 216, the second highly doped P-type region 220-1, and the third highly doped P-type region 220-2 are formed on the same doped step, for example formed in the same ion implantation step.

The ESD protection device 200 also includes a first polysilicon layer 222-1 and a second polysilicon layer 222-2, a first thin oxide layer 224-1 and a second thin oxide layer 224-2. The first polysilicon layer 222-1 and the second polysilicon layer 222-2 are formed on the P-type well 206, and the first thin oxide layer 224-1 is formed on the first polysilicon layer 222-1 and the P-type well. Between the wells 206 , a second thin oxide layer 224 - 2 is formed between the second polysilicon layer 222 - 2 and the P-type well 206 .

In an embodiment of the present invention, as shown in FIG. 2B , the metal oxide semiconductor structure 102 includes a first sub metal oxide semiconductor structure 102-a and a second sub metal oxide semiconductor structure 102-b, with respect to P The type well middle portions 206-1 are generally arranged symmetrically to each other. Similarly, the bipolar junction structure 104 includes a first sub-bipolar junction structure 104-a and a second sub-bipolar junction structure 104-b, which are substantially arranged with respect to the P-type well middle portion 206-1. symmetry. In the embodiment of the present invention, the above-mentioned different regions are defined as the first sub-MOS structure 102-a and the second sub-MOS structure 102-b and the first sub-bipolar junction structure 104-a and the second sub-structure 104-a. Different functional components of the two sub-bipolar junction structures 104-b will be described in detail later.

The first sub-MOS structure 102-a includes a first N-type well 208-1, a first highly doped N-type region 210-1, and is interposed between the first N-type well 208-1 and the P-type well 206. Part of the high-voltage N-type well 204 (hereinafter also referred to as "the first high-voltage N-type well part 204-1"), located under the first thin oxide layer 224-1 and between the first high-voltage N-type well part 204- Part of the P-type well 206 between 1 and the third highly-doped N-type region 212 (hereinafter also referred to as "the first P-type well side part 206-2"), connected to the first P-type well side part 206-2 Another part of the P-type well 206 (hereinafter referred to as “P-type well bottom portion 206 - 3 ”), the first highly doped P-type region 210 and the third highly doped N-type region 212 . In the embodiment of the present invention, the first N-type well 208-1, the first highly doped N-type region 210-1, the first high-voltage N-type well part 204-1, and the first P-type well side part 206-2 , the bottom part of the P-type well 206-3, the first highly-doped P-type region 216 and the third highly-doped N-type region 212 are respectively used as the drain region of the first sub-metal oxide semiconductor structure 102-a, Drain electrode, drift region, channel region, body region, body electrode and source region. As can be understood by those skilled in the art, the drift region refers to the region between the drain region and the channel region of the transistor, and/or the region between the source region and the channel region of the transistor in a transistor device. A region is more lightly doped than the drain or source regions, and the drift region helps increase the breakdown voltage of the transistor.

Similarly, the second sub-MOS structure 102-b includes a second N-type well 208-2, a second highly doped N-type region 210-2, and a P-type region between the second N-type well 208-2 and the P-type Another part of the high-voltage N-type well 204 between the wells 206 (hereinafter also referred to as "the second high-voltage N-type well part 204-2") is located under the second thin oxide layer 224-2 and between the second high-voltage N-type well. Another part of the P-type well 206 between the well part 204-2 and the fourth highly-doped N-type region 214 (hereinafter also referred to as "the second P-type well side part 206-4"), the bottom part of the P-type well 206 -3. The first heavily doped P-type region 216 and the fourth highly doped N-type region 214 . In the embodiment of the present invention, the second N-type well 208-2, the second highly doped N-type region 210-2, the second high-voltage N-type well part 204-2, and the second P-type well side part 206-4 , the bottom part of the P-type well 206-3, the first highly doped P-type region 216 and the fourth highly doped N-type region 214 are respectively used as the drain region of the second metal oxide semiconductor structure 102-b, Drain electrode, drift region, channel region, body region, body electrode and source region.

In the ESD protection device 200, a first gate contact (gate contact) 226-1 is formed on the first polysilicon layer 222-1 and electrically coupled to the first polysilicon layer 222-1, so the first A gate contact 226-1 is electrically coupled to the gate electrode of the first sub-MOS structure 102-a. The second gate contact 226-2 is formed on the second polysilicon layer 222-2 and is electrically coupled to the second polysilicon layer 222-2, so the second gate contact 226-2 is electrically coupled to the second polysilicon layer 222-2. The gate electrode of the second sub-MOS structure 102-b. The first gate contact 226-1 and the second gate contact 226-2 can be electrically coupled to each other through, for example, metal wires, and electrically coupled to the internal circuit 110 protected by the ESD protection device 200 (not shown in FIG. Figure 2A and Figure 2B).

The first sub-bipolar junction structure 104-a includes a second highly doped P-type region 220-1, a first highly doped N-type region 210-1, a P-type well 206 and a first highly doped P-type doped region 220-1. The impurity region 216 serves as the emitter region, the base region, the collector region and the collector electrode of the first sub-bipolar junction structure 104-a, respectively. Similarly, the second sub-bipolar junction structure 104-b includes a third heavily doped P-type region 220-2, a second highly doped N-type region 210-2, a P-type well 206 and the first highly doped The P-type doped region 216 serves as the emitter region, the base region, the collector region and the collector electrode of the second sub-bipolar junction structure 104-b, respectively.

FIG. 3 illustrates an ESD protection device 300 according to another embodiment of the present invention. The plan view of the ESD protection device 300 is the same as the plan view of the ESD protection device 200 shown in FIG. 2A , so it will not be repeated. FIG. 3 is a cross-sectional view of the ESD protection device 300 taken along the AA' section line in the plan view of FIG. 2A .

The ESD protection device 300 is similar to the ESD protection device 200, except that the ESD protection device 300 further includes a first shallow N-type well 302-1 and a second shallow N-type well 302-2. The first shallow N-type well 302-1 and the second shallow N-type well 302-2 can be formed by introducing other N-type impurities into the first N-type well 208-1 and the second N-type well 208-2, respectively. Therefore, the impurity concentrations in the first shallow N-type well 302-1 and the second shallow N-type well 302-2 are respectively higher than the impurity concentrations in the first N-type well 208-1 and the second N-type well 208-2. In this embodiment, the first highly-doped N-type region 210-1 and the second highly-doped N-type region 210-2 can pass other N-type impurities into the first shallow N-type well 302- 1 and the second shallow N-type well 302-2, therefore, the impurity concentrations in the first shallow N-type well 302-1 and the second shallow N-type well 302-2 are respectively lower than those in the first highly doped N-type well. The impurity concentration in the region 210-1 and the second highly doped N-type region 210-2. In some embodiments, the impurity concentrations in the first shallow N-type well 302-1 and the second shallow N-type well 302-2 are about 1×10 ¹⁵ cm ⁻³ to 1×10 ²⁰ cm ⁻³ . In the embodiment of the present invention, an additional first shallow N-type well 302-1 and a second shallow N-type well 302-2 are provided, and the first and second sub-bipolar junction structures 104-a and 104-B can be punched more easily than the first and second sub-bipolar junction structures 104-A and 104-B described in FIG. 2B.

As mentioned above, compared with conventional devices (such as the traditional ESD protection device 400 shown in FIG. 4 ), the device according to the embodiment of the present invention (hereinafter also referred to as a "novel ESD protection device"), for example, is The ESD protection device 200 shown in FIG. 2A and FIG. 2B or the ESD protection device 300 shown in FIG. 3 has a built-in bipolar junction structure in addition to a high voltage metal oxide semiconductor structure. In contrast, as shown in FIG. 4 , the conventional ESD protection device 400 does not have a built-in bipolar junction structure. Therefore, in the novel ESD protection device according to the embodiment of the present invention, since the metal oxide semiconductor structure and the bipolar junction structure share part of the same substrate area, the total substrate area required by the novel ESD protection device is almost the same as The total substrate area required by a conventional ESD protection device 400 with only one HVMOS structure. During operation of the novel ESD protection device, the metal oxide semiconductor structure and the bipolar junction structure are turned on at the same time, so that an electrostatic discharge current passes through the metal oxide semiconductor structure and the bipolar junction structure. During electrostatic discharge, electrostatic discharge current can also pass through deeper paths in the bipolar junction structure. Therefore, the novel ESD protection device has lower turn-on resistance and better safe operating area (SOA). For example, compared with the conventional ESD protection device 400, the on-resistance of the novel ESD protection device can be reduced by about 14% to 18%, and the safe operating area of the novel ESD protection device can be improved by about 23% to 32%. .

The comparison of electrical characteristics between the traditional ESD protection device 400 and the novel ESD protection devices 200 and 300 is shown in FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B and FIG. 7 .

Specifically, FIG. 5A and FIG. 5B show I _DS -V _DS diagrams actually measured by the traditional ESD protection device 400 and the novel ESD protection devices 200, 300 (wherein I DS represents the drain current and V _DS represents the drain voltage ). FIG. 5A shows the linear regions of the I _DS -V _DS diagram, and FIG. 5B shows the linear regions and saturation regions of the I _DS -V _DS diagram. As shown in FIG. 5A , in the linear region, under the same V _DS , the I _DS of the ESD protection devices 200 and 300 are greater than the I _DS of the conventional ESD protection device 400 . In addition, when V _DS increases, the I _DS of the ESD protection device 200 , 300 increases faster than the I _DS of the conventional ESD protection device 400 . This means that the on-resistance R _DS-on of the ESD protection device 200 , 300 is smaller than the on-resistance R DS _-on of the conventional ESD protection device 400 . Furthermore, as shown in FIG. 5B , when the device enters the saturation region, the I _DS of the ESD protection devices 200 and 300 are greater than the I _DS of the conventional ESD protection device 400 . That is to say, the saturation current I _DS-sat of the ESD protection device 200 , 300 is greater than the I _DS-sat of the conventional ESD protection device 400 . In summary, as shown in FIG. 5A and FIG. 5B , when electrostatic discharge occurs, the ESD protection devices 200 and 300 can handle a larger current than the conventional ESD protection device 400 .

A transmission line pulse (TLP) test is performed to evaluate the ESD protection performance of the ESD protection devices 200 , 300 and the traditional ESD protection device 400 . FIG. 6A shows the transmission line pulse diagram of the conventional ESD protection device 400 and the transmission line pulse diagrams of the ESD protection devices 200 and 300 . FIG. 6B is an enlarged view of a transmission line pulse diagram showing details where snapback occurs, such as where the device is triggered to turn on (circled area in FIG. 6A ). In FIG. 6A and FIG. 6B , the horizontal axis represents the drain voltage V _DS and the vertical axis represents the drain current I _DS . As shown in FIG. 6A and FIG. 6B , when foldback occurs, the drain current I _DS of the ESD protection devices 200 and 300 is higher than the drain current I _DS of the conventional ESD protection device 400 . That is to say, the trigger current of each of the ESD protection devices 200 and 300 is higher than that of the conventional ESD protection device 400 . Specifically, the trigger current of the ESD protection device 200 is about three times higher than that of the traditional ESD protection device 400, and the trigger current of the ESD protection device 300 is about three times higher than the trigger current of the traditional ESD protection device 400. five times. Compared with the traditional ESD protection device 400 , the ESD protection devices 200 and 300 are less prone to latch-up due to the higher trigger current.

FIG. 7 shows measurement results of the electrical safe-operating area (ESOA) of the conventional ESD protection device 400 and the ESD protection devices 200 and 300 . As shown in FIG. 7 , compared with the traditional ESD protection device 400 , the ESD protection devices 200 and 300 have a larger electrical safe operation area. Specifically, the electrical safe operating area of the ESD protection device 200 is approximately 1.2 times that of the traditional ESD protection device 400, and the electrical safe operating area of the ESD protection device 300 is approximately 1.2 times that of the traditional ESD protection device 400 1.2 times the electrical safe operating area.

Table 1 below summarizes the improvements of the ESD protection devices 200 and 300 compared with the traditional ESD protection device 400 . The percentages in the table represent the change in percentage, and “times” represents how many times the specific property of the ESD protection device 200 , 300 is that of the conventional ESD protection device 400 . For example, as shown in Table 1, the trigger current of the ESD protection device 200 is about three times that of the conventional ESD protection device 400 .

Electrostatic discharge protection device 200 Electrostatic discharge protection device 300 On-resistance reduction ~14.66% ~17.59% Drive current improvement ~3 times ~5 times Improvement of electrical safety operating area ~1.3 times ~1.2 times Electrostatic Discharge Improvement ~2.9 times ~2.6 times

Comparison of Traditional ESD Protection Devices and Novel ESD Protection Devices

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (20)

1. a kind of semiconductor device, including：

One substrate；

One metal-oxide-semiconductor structure is formed in the substrate, which includes：

One the first semiconductor region, it is the gold to have a first conductive type and one first doping level, the first semiconductor region Belong to a drain region of oxide-semiconductor structure；

One second semiconductor regions, are formed on the first semiconductor region, second semiconductor regions, and there is this first to lead Electric type and one second doping level, second doping level are higher than first doping level, which is the gold Belong to a drain electrode of oxide-semiconductor structure, and is electrically coupled to the drain region of the metal-oxide-semiconductor structure；

One the third semiconductor region has a second conductive type, which includes the metal-oxide semiconductor (MOS) One passage area of structure and a body regions；And

One the fourth semiconductor region is formed on the third semiconductor region and has the first conductive type, and the 4th half leads Body region is the source region of the metal-oxide-semiconductor structure；

Wherein the passage area is formed between the first semiconductor region and the fourth semiconductor region；And

Bipolar junction structure is formed in the substrate, which includes：

One the 5th semiconductor regions are formed on the first semiconductor region and are contacted with second semiconductor regions, this Five semiconductor regions have the second conductive type, and are an emitter region in the bipolar junctions region；

Wherein second semiconductor is a base region of the bipolar junctions structure, and

The third semiconductor region is a collector region of the bipolar junctions structure.

2. semiconductor device according to claim 1, further includes：

One drift region of the metal-oxide-semiconductor structure, be formed in the substrate and between the first semiconductor region with Between the third semiconductor region, the drift region have the doping level of the first conductive type and the drift region less than this One doping level.

3. semiconductor device according to claim 1, the wherein doping level of the 5th semiconductor regions are higher than the third The doping level of semiconductor regions.

4. semiconductor device according to claim 1, further includes：

One electrode zone is formed on the third semiconductor region,

Wherein the electrode zone has the second conductive type, and the doping level of the electrode zone is higher than the third semiconductor region Doping level, and

The electrode zone is a bulk electrode of the metal-oxide-semiconductor structure and the collector electricity of the bipolar junctions structure Pole.

5. semiconductor device according to claim 4, the wherein electrode zone contact the third semiconductor region.

6. semiconductor device according to claim 4, the wherein electrode zone pass through an electricity with the fourth semiconductor region Wiring electrical couplings each other.

7. semiconductor device according to claim 1, wherein the 5th semiconductor regions connect with the first semiconductor region It touches, and is surrounded by second semiconductor regions on the direction on the surface for being parallel to the semiconductor device.

8. semiconductor device according to claim 1, wherein

The first conductive type is a N-type conductivity type, and

The second conductive type is a P-type conduction type.

9. semiconductor device according to claim 8, the wherein substrate are a p-type substrate, and the semiconductor device more wraps It includes：

One N-type trap is formed in the p-type substrate, and the doping level of the N-type trap is less than first doping level,

Wherein the metal-oxide-semiconductor structure is formed in the bipolar junctions structure in the N-type trap.

10. semiconductor device according to claim 9, the wherein N-type trap include the metal-oxide-semiconductor structure One drift region, the drift region are formed between the first semiconductor region and the third semiconductor region.

11. semiconductor device according to claim 9, the wherein doping level of the N-type trap are 1 × 10¹⁰cm^-3To 1 × 10¹⁶cm^-3。

It, should be partly 12. semiconductor device according to claim 8, the wherein the first semiconductor region include one first N-type trap Conductor device further includes：

One second N-type trap is formed in first N-type trap, the doping level of second N-type trap higher than first doping level and Less than second doping level,

Wherein second semiconductor regions are formed in the 5th semiconductor regions in second N-type trap.

13. semiconductor device according to claim 1, further includes：

One gate dielectric film, is formed on the passage area of the metal-oxide-semiconductor structure；And

One gate electrode is formed on the gate dielectric film.

14. semiconductor device according to claim 1, wherein

The metal-oxide-semiconductor structure is one first metal-oxide-semiconductor structure, and

The bipolar junctions structure is one first bipolar junctions structure,

The semiconductor device further includes：

One second metal-oxide-semiconductor structure, is formed in the substrate, which includes：

One the 6th semiconductor regions are arranged as and first semiconductor relative to a middle section of the third semiconductor region Region is symmetrical, and the 6th semiconductor regions have the first conductive type and a third doping level, and the 6th semiconductor regions For a drain region of second metal-oxide-semiconductor structure；

One the 7th semiconductor regions, are formed on the 6th semiconductor regions, and being somebody's turn to do relative to the third semiconductor region Middle section, is arranged as symmetrical with second semiconductor regions, and the 7th semiconductor regions have the first conductive type and one the Four doping levels, and the drain electrode that the 7th semiconductor regions are second metal-oxide-semiconductor structure；And

One the 8th semiconductor regions, are formed on the third semiconductor region, and being somebody's turn to do relative to the third semiconductor region Middle section, be arranged as it is symmetrical with the third semiconductor region, the 8th semiconductor regions have the first conductive type be this The source region of two metal-oxide-semiconductor structures,

Wherein the third semiconductor region further includes a passage area and an ontology for second metal-oxide-semiconductor structure Region, the middle part of the passage area of second metal-oxide-semiconductor structure relative to the third semiconductor region Point, it is arranged as symmetrical with the passage area of first metal-oxide-semiconductor structure；And

One second bipolar junctions structure, is formed in the substrate, which includes：

One the 9th semiconductor regions are formed on the 6th semiconductor regions and are contacted with the 7th semiconductor regions, this The middle section of nine semiconductor regions relative to the third semiconductor region, be arranged as it is symmetrical with the 5th semiconductor regions, 9th semiconductor is poly- the second conductive type, and is an emitter region of the second bipolar junctions structure；

Wherein the 7th semiconductor regions are a base region of the second bipolar junctions structure, and

The third semiconductor region is a collector region of the second bipolar junctions structure.

15. semiconductor device according to claim 14, wherein

First doping level is equal to the third doping level, and

Second doping level is equal to the 4th doping level.

16. semiconductor device according to claim 14, the wherein the fourth semiconductor region and the 8th semiconductor regions For the part in a continuous semiconductor region, which has the first conductive type and is formed in the third semiconductor region On domain.

17. semiconductor device according to claim 16, further includes：

One electrode zone is formed on the third semiconductor region, wherein

The electrode zone has the doping level of the second conductive type and the electrode zone mixing higher than the third semiconductor region Miscellaneous degree,

The electrode zone is surrounded on being parallel to the direction on a surface of the semiconductor device by the continuous semiconductor region, And

The electrode zone is a bulk electrode and the second bipolar junctions structure for second metal-oxide-semiconductor structure One collector electrode.

18. semiconductor device according to claim 17, the wherein electrode zone contact the third semiconductor region.

19. a kind of semiconductor device, including：

One substrate；

One metal-oxide-semiconductor structure is formed in the substrate, which includes a drain region Domain, the drain electrode for being electrically coupled to the drain region, a body regions and source region；The drain region is one first Semiconductor regions, the first semiconductor region have a first conductive type and one first doping level；The drain electrode is one the Two semiconductor regions, second semiconductor regions are formed on the first semiconductor region, have the first conductive type and one Second doping level, second doping level are higher than first doping level；The body regions are a third semiconductor region A part, the third semiconductor region include a passage area and the body regions for the metal-oxide-semiconductor structure, tool There is a second conductive type；The source region is a fourth semiconductor region, which is formed in the third and partly leads On body region and there is the first conductive type；The passage area is formed in the first semiconductor region and the 4th semiconductor region Between domain；And

Bipolar junction structure is formed in the substrate, which includes an emitter region, a base region and one Collector region；The emitter region is one the 5th semiconductor regions, and the 5th semiconductor regions are formed in the first semiconductor region On and contact with second semiconductor regions, there is the second conductive type；The base region is second semiconductor regions；It should Collector region is the third semiconductor region, wherein

The drain electrode shares one first common semiconductor region with the base region in the substrate, and

The body regions share one second common semiconductor region with the collector region in the substrate.

20. a kind of semiconductor device, including：

One substrate；

One first trap, is formed in the substrate, which has a first conductive type and one first doping level；

One first high-concentration dopant region is formed in first trap, which has first conduction Type and one second doping level, second doping level are higher than first doping level；

One second trap, is formed in the substrate, which has a second conductive type and a third doping level；

One second high-concentration dopant region is formed in second trap, which has first conduction Type and one the 4th doping level, the 4th doping level are higher than first doping level；And

One third high-concentration dopant region, is formed in first trap, which has second conduction Type and one the 5th doping level, the 5th doping level are higher than the third doping level, third high-concentration dopant region contact The first high-concentration dopant region；

Wherein, first trap, the first high-concentration dopant region, second trap and the second high-concentration dopant region constitute a gold medal Belong to oxide-semiconductor structure, the third high-concentration dopant region, the first high-concentration dopant region and second trap constitute one Bipolar junctions structure.