CN105741869B - The test method and test equipment of resistance-change memory device - Google Patents

Abstract

The embodiment of the present invention provides a kind of test method and test equipment of resistance-change memory device.The test method includes programming step：Have in the first memory cell group and the second memory cell group at least one set of in the case of the high-impedance state or original state, operation is programmed to one group in the first memory cell group and the second memory cell group to change the resistance state of the variable-resistance memory unit in described group, wherein, do not undergo the programming operation during the programming operation another group remains original state or high-impedance state；And detecting step：Read operation is performed at least one variable-resistance memory unit that experienced the programming operation in above-mentioned programming step with obtain indicating at least one variable-resistance memory unit whether qualified information, wherein, during the read operation is performed, do not undergo the programming operation another group remains original state or high-impedance state.

Description

Test method and test equipment for resistive memory device

technical field

Embodiments of the present invention relate to a testing method and testing equipment for a resistive variable memory device.

Background technique

A resistive memory device with a resistive memory cell array is considered to be one of the most promising next-generation high-density memory technologies. The cross-point matrix resistive memory cell array includes a set of parallel word lines and a set of parallel bit lines perpendicular thereto. The resistive memory cell is located at the intersection of the word line and the bit line. FIG. 1 schematically shows the phenomenon of crosstalk in a resistive memory cell array. The four resistive memory cells R1 to R4 are arranged in an array of 2 rows and 2 columns, wherein R2 is in a high resistance state, and R1, R3 and R4 are in a low resistance state. If you want to read the current flowing through R2, but because there is a leakage current path flowing through R1→R3→R4, the final read current is not the current that actually passes through R2, resulting in a misreading operation. This phenomenon may be called a crosstalk phenomenon.

Contents of the invention

An embodiment of the present invention provides a testing method for a resistive memory device, the resistive memory device includes a plurality of resistive memory cells arranged in an array, and the array includes at least one odd-numbered row and at least one even-numbered row; and at least one odd-numbered column and at least one even-numbered column alternately arranged in a second direction different from the first direction, the plurality of resistive memory cells can be divided into first A memory cell group and a second memory cell group, wherein the sum of the row number and the column number of each resistive memory cell in the first memory cell group is an even number, and each resistive variable memory cell in the second memory cell group The sum of the row number and the column number of the variable memory cell is an odd number, and each resistive variable memory cell is designed to have an initial state, a high resistance state and a low resistance state, and the test method includes the following steps:

A programming step: when at least one of the first memory cell group and the second memory cell group is in a high-resistance state or an initial state, program the first memory cell group and the second memory cell one of the groups performs a programming operation to change the resistance state of the resistive memory cells in the group, wherein the other group that has not undergone the programming operation during the programming operation remains in an initial state or a high resistance state; as well as

Detection step: performing a read operation on at least one resistive memory cell that has undergone the programming operation in the above programming step to obtain information indicating whether the at least one resistive memory cell is qualified, wherein, after performing the read During operation, the other group that has not undergone the programming operation remains in an initial state or a high-impedance state,

Wherein, the programming operation is a forming operation, a reset operation or a setting operation, and the forming operation is designed to switch the resistive memory cell from an initial state to a low resistance state; The variable memory unit is switched from a low resistance state to a high resistance state; the setting operation is designed to switch the resistance variable memory unit from a high resistance state to a low resistance state, wherein the resistance variable memory unit in the low resistance state The resistance value of the cell is smaller than the resistance value of the resistive memory cell in the high resistance state or the initial state.

In an example, when both the first storage unit group and the second storage unit group are in an initial state, or when one of the first storage unit group and the second storage unit group is in an initial state In the initial state and wherein the resistive memory cells in another group are in the high-resistance state or in the initial state, performing a formation operation on the group in the initial state to switch the resistive memory cells in the group to the a low-resistance state, wherein another group that has not undergone the forming operation during the forming operation remains in the initial state or the high-resistance state; and a read operation is performed on the memory cell group that has undergone the forming operation In order to obtain information indicating whether the formation of the resistive memory cells in the group is qualified, wherein, during the execution of the read operation, another group that has not undergone the formation operation remains in the initial state or the high resistance state.

In one example, when one of the first memory cell group and the second memory cell group is in the high-resistance state or the initial state and the other group is in a low-resistance state, the pair is in A group of the low-resistance state performs a reset operation to switch the resistive memory cells in the group to the high-resistance state, wherein the other group that has not undergone the reset operation during the reset operation Maintaining the high-resistance state or the initial state; and performing a read operation on the memory cell group that has undergone the reset operation to obtain information indicating whether the reset of the resistive memory cells in the group is qualified, wherein, in During the execution of the read operation, the other group that has not undergone the reset operation remains in an initial state or a high-impedance state.

In one example, when both the first memory cell group and the second memory cell group are in the high-impedance state, one of the first memory cell group and the second memory cell performing a set operation by the group to switch the resistive memory cells in the group to the low resistance state, wherein the resistive memory cells not undergoing the set operation during the set operation remain in the high resistance state; and Performing a read operation on the resistive memory cells that have undergone the setting operation to obtain information indicating whether the resistive memory cells in the group are qualified for setting, wherein, during the execution of the read operation, those that have not undergone the setting operation The other group remains in the initial state or high-impedance state.

In an example, the testing method of the resistive memory device further includes: when the first memory cell group and the second memory cell group are not both in the high resistance state or the initial state, testing the multiple At least one of the resistive memory cells executes a reset operation or a repair operation so that each resistive memory cell in the first memory cell group and the second memory cell group is in the high resistance state or the initial state.

In one example, the testing method of the resistive memory device further includes: performing the programming step again after the detecting step is performed.

In one example, before the programming step, the method for testing a resistive memory device further includes: a state judging step: judging whether at least one of the first memory cell group and the second memory cell group has In high impedance state or initial state.

In one example, the state judging step includes: determining that at least one of the first storage unit group and the second storage unit group is in an inactive state after preparation, and at least one of the second storage unit groups is in an initial state.

In one example, the state judging step includes: performing a read operation on at least one of the first storage unit group and the second storage unit group, so as to obtain indications of the first storage unit group and the second storage unit group. Information about whether at least one of the memory cell groups is in a high-resistance state or an initial state.

Another embodiment of the present invention provides a testing device for a resistive memory device. The resistive memory device includes a plurality of resistive memory cells arranged in an array, and the array includes at least one odd-numbered row and at least one even-numbered row; and at least one odd-numbered column and at least one even-numbered column alternately arranged in a second direction different from the first direction, the plurality of resistive memory cells can be divided into first A memory cell group and a second memory cell group, wherein the sum of the row number and the column number of each resistive memory cell in the first memory cell group is an even number, and each resistive variable memory cell in the second memory cell group The sum of the row number and the column number of the variable memory cell is an odd number, and each resistive variable memory cell is designed to include an initial state, a high resistance state and a low resistance state,

The test equipment includes:

a program detection section configured to output a programming signal to the first memory cell group and the second memory cell group when at least one of the first memory cell group and the second memory cell group is in a high resistance state or an initial state A group of the second memory cell group performs a program operation and outputs a read signal to at least one resistive memory cell that has undergone the program operation to perform a read operation to obtain an indication of the at least one resistive memory cell Whether it is qualified or not, wherein, during the programming operation and during the reading operation, the other group that has not undergone the programming operation remains in a high-impedance state or an initial state,

Wherein, the programming signal is a forming signal for a forming operation, a reset signal for a reset operation, or a setting signal for a setting operation, and the forming operation is designed to switch the resistive memory cell from an initial state to a low-resistance state; the reset operation is designed to switch the resistive memory unit from a low-resistance state to a high-resistance state; the set operation is designed to switch the resistive memory unit from a high-resistance state to a low-resistance state state, wherein the resistance value of the resistive memory cell in the low resistance state is smaller than the resistance value of the resistive memory cell in the high resistance state or the initial state.

In one example, the program detection part is configured to be used when both the first memory cell group and the second memory cell group are in an initial state or when the first memory cell group and the second memory cell group are in an initial state. When one of the cell groups is in the initial state and the resistive memory cells in the other group are in the high-resistance state or the initial state, a forming signal is output to the group in the initial state to perform a forming operation to convert The resistive memory cells in the group are switched to the low-resistance state, and a read signal is output to the memory cell group that has undergone the forming operation to perform a read operation to obtain an indication of whether the resistive memory cells in the group are formed Qualified information, wherein, during the forming operation and during the readout operation, another group that has not undergone the forming operation remains in the initial state or the high-resistance state.

In one example, the program detection part is used for when one of the first memory cell group and the second memory cell group is in the high-resistance state or the initial state and the other group is in a low-resistance state In this case, output a reset signal to a group in the low resistance state to perform a reset operation to switch the resistive memory cells in the group to the high resistance state, and output a read signal to the group that has experienced the described performing a read operation to obtain information indicating whether the reset of the resistive memory cells in the group is qualified, wherein during the reset operation and during the read operation, the reset operation has not been performed The other set of operations remains in the high-impedance state or the initial state.

In one example, the program detection part is configured to output a set signal to the first memory cell group and the second memory cell group when both the first memory cell group and the second memory cell group are in the high-impedance state. performing a set operation on one group of the two memory cells to switch the resistive memory cells in the group to the low-resistance state, and outputting a read signal to the memory cell group that has undergone the set operation to perform a read operation In order to obtain the information indicating whether the resistive memory cells in the group are qualified, wherein during the setting operation and the reading operation, another group that has not undergone the setting operation remains in the high resistance state.

In one example, the test equipment for the resistive memory device further includes: a state adjustment part, configured to, when the first memory cell group and the second memory cell group are not both in the high resistance state or the initial state, Outputting a reset signal to at least one of the plurality of resistive memory cells to perform a reset operation, so that each resistive memory cell in the first memory cell group and the second memory cell group is in the high-impedance state or initial state.

In one example, the test equipment for the resistive memory device further includes:

A state detection part, configured to output a readout signal to at least one of the first memory cell group and the second memory cell group to obtain information indicating the resistance state of the resistive memory cell, according to the information indicating the resistance state of the resistive memory cell The information of the resistance state of the memory cell is used to judge whether at least one of the first memory cell group and the second memory cell group is in a high resistance state or an initial state, and output a state detection signal indicating the result of the above judgment to The programming detection section,

Wherein, the program detection part outputs a programming signal to the first memory cell in response to a state detection signal that at least one of the first memory cell group and the second memory cell group is in a high resistance state or an initial state. One of the cell group and the second memory cell group is subjected to a program operation, wherein the other group that has not undergone the program operation during the execution of the program operation remains in an initial state or a high-resistance state.

In one example, the test equipment for the resistive memory device further includes:

A state detection part, configured to output a readout signal to at least one of the first memory cell group and the second memory cell group to obtain information indicating the resistance state of the resistive memory cell, according to the information indicating the resistance state of the resistive memory cell judge whether at least one of the first memory cell group and the second memory cell group is in a high-impedance state or an initial state, and output a state detection signal indicating a result of the judgment to the program detection section and the state adjustment section,

Wherein, the state adjustment part is configured to output a reset signal to the plurality of resistors in response to a state detection signal that the first memory cell group and the second memory cell group are not both in a high-impedance state or an initial state. changing at least one of the memory cells to perform a reset operation, so that each resistive memory cell in the first memory cell group and the second memory cell group is in the high resistance state or an initial state,

The program detection section is configured to output a program signal to the first memory cell group in response to a state detection signal that both the first memory cell group and the second memory cell group are in a high resistance state or an initial state. and one group of the second memory cell group to perform a program operation, wherein the other group not undergoing the program operation during the program operation remains in an initial state or a high-resistance state.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings that need to be used in the embodiments or related technical descriptions. Obviously, the drawings in the following description only relate to some implementations of the present invention example, not limitation of the present invention.

FIG. 1 is a schematic diagram of a crosstalk phenomenon in a resistive memory cell array of the related art;

FIG. 2 is a schematic plan view of a resistive memory device provided by an embodiment of the present invention;

FIG. 3 is a flow chart of a testing method for a resistive memory device provided in an embodiment of the present invention;

FIG. 4 is a schematic diagram of the resistance state distribution of each resistive memory cell after performing a forming operation on the first memory cell group in the resistive memory device shown in FIG. 2 .

FIG. 5 is a schematic diagram of the resistance state of each resistive memory cell after a reset operation is performed on the first memory cell group in the resistive memory device having the resistance state distribution shown in FIG. 4 .

FIG. 6 is a schematic diagram of the distribution of resistance states of each resistive memory cell after repairing the reset failed resistive memory cell in the resistive memory device shown in FIG. 5 .

FIG. 7 is a schematic diagram of the resistance state distribution of each resistive memory cell after the forming operation is performed on the second memory cell group in the resistive memory device having the resistance state distribution shown in FIG. 6 .

FIG. 8 is a schematic diagram of the resistance state distribution of each resistive memory cell after a reset operation is performed on the second memory cell group in the resistive memory device having the resistance state distribution shown in FIG. 7 .

FIG. 9 is a schematic diagram of the resistance state distribution of each resistive memory cell after performing a set operation on the second memory cell group in the resistive memory device having the resistance state distribution shown in FIG. 8 .

FIG. 10 is a schematic diagram of the resistance state distribution of each resistive memory cell after a reset operation is performed on the second memory cell group in the resistive memory device having the resistance state distribution shown in FIG. 9 .

FIG. 11 is a schematic diagram of the resistance state distribution of each resistive memory cell after performing a set operation on the first memory cell group in the resistive memory device having the resistance state distribution shown in FIG. 10 .

FIG. 12 is a schematic diagram of the resistance state distribution of each resistive memory cell after a reset operation is performed on the first memory cell group in the resistive memory device having the resistance state distribution shown in FIG. 11 .

FIG. 13 is a block diagram of testing equipment for a resistive memory device according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Referring to the non-limiting exemplary embodiments shown in the accompanying drawings and detailed in the following description, the examples of the present invention will be more fully described. Embodiments and their various features and advantageous details. It should be noted that the features shown in the figures are not necessarily drawn to scale. Descriptions of well-known materials, components, and process techniques are omitted so as not to obscure the example embodiments of the invention. The examples are merely intended to facilitate understanding of the practice of the example embodiments of the invention and to further enable those skilled in the art to practice the example embodiments. Thus, the examples should not be construed as limiting the scope of the example embodiments of the invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by those skilled in the art to which the present invention belongs. The use of "first", "second" and similar words in , do not imply any order, quantity or importance, but are only used to distinguish different components. "Up", "Down", "Left", "Right" and so on are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

Embodiments of the present invention provide a testing method and testing equipment for a resistive memory device, which can effectively avoid misreading operations caused by crosstalk during the test phase, and can accurately identify various unqualified resistive switches in the resistive memory device. storage unit.

An embodiment of the present invention provides a testing method for the resistive memory device 10 .

As shown in FIG. 2 , the resistive memory device 10 includes, for example, five word lines WL1 - WL5 extending in the horizontal direction, and five bit lines BL1 - BL5 extending in the vertical direction. Any bit line is insulated from and intersects with all word lines, and any word line is insulated from and intersects with all bit lines, thereby forming 25 crossing regions. A resistive memory cell Rnm is formed in each intersection area, where n represents the row number of the resistive memory cell, and m represents the column number of the resistive memory cell. The 25 resistive memory cells R11-R55 are arranged in an array of 5 rows and 5 columns. Here, the number of rows and the number of columns of the array formed by the resistive memory cells are not limited, as long as the number of rows and the number of columns of the formed array are integers greater than or equal to 2.

In FIG. 2 , each resistive memory cell Rnm is shown by a solid circle or a dotted line. The resistive memory cells in the same row are electrically connected to the same word line, and the resistive memory cells in the same column are electrically connected to the same bit line. The array of resistive memory cells with 5 rows and 5 columns shown in Figure 2 includes 3 odd-numbered rows and 2 even-numbered rows alternately arranged in the vertical direction, and 3 odd-numbered columns arranged alternately in the horizontal direction and 2 even columns. In the vertical direction, the 1st row to the 5th row are arranged in sequence; in the horizontal direction, the 1st column to the 5th column are arranged in sequence. According to the position in the array, the plurality of resistive memory cells can be divided into two groups, ie, a first memory cell group and a second memory cell group. The sum of the row number and the column number of each resistive memory cell in the first memory cell group is an even number, and the resistive memory cells belonging to the first memory cell group are shown in dotted circles in Fig. 2; the second memory cell group The sum of the row number and the column number of each resistive memory cell is an odd number, and the resistive memory cells belonging to the second memory cell group are shown in circles with solid lines in FIG. 2 . For example, for the resistive memory cell R23, since the sum of its row number 2 and column number 3 is equal to 5 (an odd number), it belongs to the second memory cell group; for the resistive memory cell R24, since its row number 2 and The sum of column numbers 4 is equal to 6 (an even number), so it belongs to the first memory cell group. By analogy, each resistive memory cell can be divided into the first memory cell group or the second memory cell group.

In this embodiment, each resistive memory cell includes, for example, only one resistive memory device, that is, 1R type. A resistive variable memory device includes, for example, an upper electrode, a lower electrode, and a resistive layer material capable of reversible resistance transition between the upper and lower electrodes. Here, the word line and the bit line may be used, for example, as an upper electrode and a lower electrode of the resistive memory device, respectively. In another example, the resistive memory cell may include, for example, a diode and a resistive memory device connected in series, that is, 1D1R type; in yet another example, the resistive memory cell may include, for example, a transistor and a Resistive memory device, namely, 1T1R type;

For example, a resistive memory device is usually in an initial high-resistance state I after fabrication is completed. Generally, an electrical activation operation needs to be performed first to form (FORMING) the resistive memory device from an initial high-resistance state I to a low-resistance state L. Then, for example, under the action of an external bias voltage, the resistance of the resistive memory device can be reversibly switched between a high-resistance state H and a low-resistance state L, thereby realizing data storage. Corresponding to the resistance state of the resistive memory device, each resistive memory cell is designed to have an initial state, a high resistance state and a low resistance state. That is, the resistive memory unit being in the initial state I means that the resistive memory device it includes is in the initial state I; the resistive memory cell being in the low-resistance state L means that the resistive memory device it includes is in the low-resistance state L; The variable memory cell being in the high resistance state H means that the resistive memory device included in it is in the high resistance state H. The resistance value of the resistive memory cell in the low resistance state is smaller than the resistance value of the resistive memory cell in the high resistance state or the initial state. Here, the resistance of the resistive memory cell refers to the resistance of the resistive memory device included therein. In one example, the resistance of the resistive memory cell in the high resistance state or the initial state is at least 1000 times that of the resistive memory cell in the low resistance state. For example, the resistance value of the resistive memory cell in the high resistance state or the initial state is 10 ^{to 10} times the resistance value of the resistive memory cell in the low resistance state. The resistance of the resistive memory unit in the initial state is greater than the resistance of the resistive memory unit in the high resistance state. Under the action of an external bias voltage, the resistance of the resistive memory cell can be reversibly switched between the high-resistance state H and the low-resistance state L, thereby realizing writing "0" and writing "1", and then realizing data storage . Here, writing "0" refers to resetting (RESET) the resistive memory cell from the low-resistance state L to a high-resistance state H; writing "1" refers to setting (SET) the resistive memory cell from the high-resistance state H to Low resistance state L.

As shown in FIG. 3, the testing method of the resistive memory device provided by the embodiment of the present invention includes the following steps, for example:

A programming step: when at least one of the first memory cell group and the second memory cell group is in a high-resistance state or an initial state, program the first memory cell group and the second memory cell one of the groups performs a programming operation to change the resistance state of the resistive memory cells in the group, wherein the other group that has not undergone the programming operation during the execution of the programming operation remains in an initial state or a high resistance state ;as well as

Detection step: perform a read operation on the resistive memory cells that have undergone the programming operation in the above programming step to obtain information indicating whether the resistive memory cells are qualified, wherein, during the execution of the read operation, no The other set of the programming operations remain in the initial state or high-impedance state.

Here, the program operation refers to any one of a form operation, a reset operation, and a set operation. The forming operation is designed to switch the resistive memory cell from an initial state to a low resistance state; the reset operation is designed to switch the resistive memory cell from a low resistance state to a high resistance state; the setting operation It is designed to switch the resistive memory unit from a high resistance state to a low resistance state. The first memory cell group is in (or remains in) a high-resistance state or an initial state means that each resistive memory cell in the first memory cell group is in (or remains in) a high-resistance state or an initial state; similarly The fact that the second memory cell group is in (or remains in) a high-resistance state or an initial state means that each resistive memory cell in the second memory cell group is in (or remains in) a high-resistance state or an initial state. Performing a programming operation on one of the first memory cell group and the second memory cell group refers to performing a programming operation on each resistive memory cell in the group.

Hereinafter, with reference to FIG. 4 , a test method provided by an embodiment of the present invention for testing whether there are unqualified resistive memory cells in the resistive memory device shown in FIG. 2 will be described.

For example, the 25 resistive memory cells of the resistive memory device shown in FIG. 2 are all in an inactive initial state I and a high-resistance state after preparation. In order to test whether there are unqualified resistive memory cells in the first memory cell group, steps P1 and C1 may be included.

In step P1, a formation operation is performed on the first memory cell group to change the resistive memory cells in the first memory cell group (shown by dotted circles in FIG. 4 ) from the initial high resistance state I to low resistance state L . For example, the forming operation is performed by applying a forming voltage to each of the first memory cell groups in the first memory cell group.

During this forming operation, each resistive memory cell in the second memory cell group maintains an initial high resistance state I. Therefore, after the formation operation is completed, each resistive memory cell in the second memory cell group is still in the initial high resistance state I, while each resistive memory cell in the first memory cell group should be in the normal state. Low resistance state L. Here, the normal situation refers to the situation that there is no unqualified resistive memory cell in the memory cell group that is subjected to the programming operation (here, the forming operation).

If there is an unqualified resistive memory cell in the first memory cell group, for example, the resistive memory cell R24 in row 2 and column 4 is an unqualified resistive memory cell, its resistance state remains at the initial state The high-impedance state I (as shown by the dotted circle filled with slash hatching in FIG. 4 ).

Next, checking step C1 is carried out.

In step C1, a read operation is performed on each resistive memory cell in the first memory cell group to obtain information indicating whether there is an unqualified resistive memory cell in the first memory cell group. During the read operation, the second memory cell group remains in an initial high-impedance state I. For example, the read operation is performed by providing a read voltage to each resistive memory cell in the first memory cell group.

Here, when a read operation is performed on any resistive memory cell in the first memory cell group, the resistive memory cells at the four adjacent positions of the selected resistive memory cell are in an initial high-resistance state I, therefore effectively avoiding the generation of leakage current around the selected resistive memory cell, thereby being able to accurately read out the information indicating the resistance state of each resistive memory cell in the first memory cell group, and the information can simultaneously be Indicating whether the resistive memory cell to be read is an unqualified resistive memory cell. For example, the information is a current value. When the read current value obtained by performing the read operation on the resistive memory cell R24 is less than a predetermined current value, it can be determined that the resistive memory cell R24 is an unqualified resistive memory cell. When the readout current value obtained by performing the read operation on the resistive memory cells in the first memory cell group is greater than or equal to the predetermined current value, it can be determined that the resistive memory cells are qualified resistive memory cells.

Hereinafter, with reference to FIG. 5 , a test method provided by an embodiment of the present invention for testing whether there are reset unqualified resistive memory cells in the first memory cell group of the resistive memory device having the resistance state distribution shown in FIG. 4 is described.

The test method may for example comprise steps P2 and C2.

In step P2, a reset operation is performed on the first memory cell group to change the resistive memory cells in the first memory cell group from a low-resistance state L to a high-resistance state H (see dotted circles in Fig. 4 and Fig. 5 ). For example, the reset operation is performed by providing a reset voltage to each of the first memory cell groups in the first memory cell group.

During the reset operation, each resistive memory cell in the second memory cell group maintains an initial high resistance state I. Therefore, after the reset operation is completed, each resistive memory cell in the second memory cell group is still in the initial high resistance state I, while each resistive memory cell in the first memory cell group is The unqualified resistive memory cells R24 should all be in the high resistance state H under normal conditions.

If, in the first memory cell group, there are reset unqualified resistive memory cells, for example, the resistive memory cell R11 in the first row and the first column is a reset unqualified resistive memory cell, then its resistance state remains It is a low-resistance state L (shown as a dotted circle filled with grid hatching in FIG. 5 ).

Next, checking step C2 is carried out.

In step C2, a read operation is performed on each resistive memory cell in the first memory cell group to obtain information indicating whether there is a reset-unqualified resistive memory cell in the first memory cell group. During the read operation, the second memory cell group remains in an initial high-impedance state I. For example, the read operation is performed by providing a read voltage to each resistive memory cell in the first memory cell group.

Here, when a read operation is performed on any resistive memory cell in the first memory cell group, the resistive memory cells at the four adjacent positions of the selected resistive memory cell are in an initial high-resistance state I, therefore effectively avoiding the generation of leakage current around the selected resistive memory cell, thereby being able to accurately read out the information indicating the resistance state of each resistive memory cell in the first memory cell group, and the information can simultaneously be Indicating whether the resistive memory cell to be read is a resistive memory cell whose reset is unqualified. For example, the information is a current value. When the readout current value obtained by performing the read operation on the resistive memory cell R11 is greater than a predetermined current value, it can be determined that the resistive memory cell R11 is a reset-unqualified resistive memory cell. When the read current value obtained by performing the read operation on the resistive memory cells in the first memory cell group is less than or equal to the predetermined current value, it can be determined that the resistive memory cells are resetting qualified resistive memory cells. It should be noted that although there are unqualified resistive memory cells R24 in the resistive memory device shown in FIG. The role of leakage current in operation, therefore does not affect the test results. In case there is a resistive memory cell R11 that fails to be reset, it can be repaired so that it has a high-resistance state H. Referring to FIG. The resistance state distribution of each resistive memory cell of the resistive memory device after repair is shown in FIG. 6 .

Hereinafter, referring to FIG. 7 , a test method for testing whether there are unqualified resistive memory cells in the second memory cell group of the resistive memory device having the resistance state distribution shown in FIG. 6 will be described according to an embodiment of the present invention.

The test method may for example comprise steps P3 and C3.

In step P3, a formation operation is performed on the second memory cell group to change the resistive memory cells in the second memory cell group from the initial high-resistance state I to the low-resistance state L (see the solid line circles in FIGS. 6 and 7 ). For example, the forming operation is performed by providing a forming voltage to each resistive memory cell in the first memory cell group.

During this forming operation, each resistive memory cell in the first memory cell group remains in the high-resistance state H or the initial high-resistance state since the reset-failure resistive memory cell R11 has been repaired to have a high-resistance state I. After the forming operation is completed, each resistive memory cell in the first memory cell group is still in the high-resistance state H or the initial high-resistance state I, while each resistive memory cell in the second memory cell group is in the normal state Should be in the low resistance state L.

Next, checking step C3 is carried out.

In step C3, a read operation is performed on each resistive memory cell in the second memory cell group to obtain information indicating whether there is an unqualified resistive memory cell in the second memory cell group. During the read operation, the first memory cell group remains in the high resistance state H or the initial high resistance state I. For example, the read operation is performed by providing a read voltage to each of the first memory cell groups in the first memory cell group.

Here, when a read operation is performed on any resistive memory cell in the second memory cell group, the resistive memory cells at the four adjacent positions of the selected resistive memory cell are all in the high resistance state H or The initial high-impedance state I, therefore effectively avoiding the leakage current around the selected resistive memory cell, thereby accurately reading the information indicating the resistance state of each resistive memory cell in the second memory cell group, At the same time, the information can indicate whether the resistive memory cell to be read is an unqualified resistive memory cell. For example, the information is a current value. When the read current value obtained by performing a read operation on a certain resistive memory cell is less than a predetermined current value, it can be determined that the resistive memory cell is an unqualified resistive memory cell. When the read current value obtained by performing a read operation on a certain resistive memory cell is greater than or equal to the predetermined current value, it can be determined that the resistive memory cell is a qualified resistive memory cell. As mentioned above, if there is an unqualified resistive memory cell, it will not affect the subsequent test because it still maintains the initial high resistance state.

Hereinafter, with reference to FIG. 8 , a test method provided by an embodiment of the present invention for testing whether there are reset unqualified resistive memory cells in the second memory cell group of the resistive memory device with the resistance state distribution shown in FIG. 7 will be described.

The test method may for example comprise steps P4 and C4.

In step P4, a reset operation is performed on the second memory cell group to change the resistive memory cells in the second memory cell group from a low-resistance state L to a high-resistance state H (see the solid line circles in FIGS. 7 and 8 ). For example, the reset operation is performed by providing a reset voltage to each of the resistive memory cell groups in the second memory cell group.

During the reset operation, each resistive memory cell in the first memory cell group remains in the high resistance state H or the initial high resistance state I. After the reset operation is completed, each resistive memory cell in the first memory cell group is still in the high resistance state H or the initial high resistance state I, while each resistive memory cell in the second memory cell group is in the normal state Both should be in the high-impedance state H.

Next, checking step C4 is carried out.

In step C4, a read operation is performed on each resistive memory cell in the second memory cell group to obtain information indicating whether there is a resistive memory cell that fails to be reset in the second memory cell group. During the read operation, the first memory cell group remains in the high resistance state H or the initial high resistance state I. For example, the read operation is performed by providing a read voltage to each resistive memory cell in the second memory cell group.

Here, when a read operation is performed on any resistive memory cell in the second memory cell group, the resistive memory cells at the four adjacent positions of the selected resistive memory cell are all in the high resistance state H or The initial high-impedance state I, therefore effectively avoiding the leakage current around the selected resistive memory cell, thereby accurately reading the information indicating the resistance state of each resistive memory cell in the second memory cell group, At the same time, the information can indicate whether the resistive memory cell subjected to the read operation is a reset-unqualified resistive memory cell. For example, the information is a current value. When the read current value obtained by performing a read operation on a certain resistive memory cell is greater than a predetermined current value, it can be determined that the resistive memory cell is a reset unqualified resistive memory cell. When the read current value obtained by performing a read operation on a certain resistive memory cell is less than or equal to the predetermined current value, it can be determined that the resistive memory cell is a reset qualified resistive memory cell. As mentioned above, if there is a reset-unqualified resistive memory cell, it can be repaired to be in a high-resistance state.

Hereinafter, referring to FIG. 9 , a test method provided by an embodiment of the present invention for testing whether there are unqualified resistive memory cells in the second memory cell group of the resistive memory device with the resistance state distribution shown in FIG. 8 will be described.

The test method may for example comprise steps P5 and C5.

In step P5, a set operation is performed on the second memory cell group to change the resistive memory cells in the second memory cell group from the high-resistance state H to the low-resistance state L (see the solid line circles in FIGS. 8 and 9 ) . For example, the reset operation is performed by providing a setting voltage to each of the resistive memory cell groups in the second memory cell group.

During the set operation, each resistive memory cell in the first memory cell group remains in the high-resistance state H or the initial high-resistance state I. After the setting operation is completed, each resistive memory cell in the first memory cell group is still in the high resistance state H or the initial high resistance state I, while each resistive memory cell in the second memory cell group is in the normal state Should be in the low resistance state L.

Next, checking step C5 is carried out.

In step C5, a read operation is performed on each resistive memory cell in the second memory cell group to obtain information indicating whether there is a resistive memory cell with an unqualified configuration in the second memory cell group. During the read operation, each resistive memory cell in the first memory cell group remains in the high-resistance state H or the initial high-resistance state I. For example, the read operation is performed by providing a read voltage to each resistive memory cell in the second memory cell group.

Here, when a read operation is performed on any resistive memory cell in the second memory cell group, the resistive memory cells at the four adjacent positions of the selected resistive memory cell are all in the high resistance state H or The initial high-impedance state I, therefore effectively avoiding the leakage current around the selected resistive memory cell, thereby accurately reading the information indicating the resistance state of each resistive memory cell in the second memory cell group, At the same time, the information can indicate whether the resistive memory cell on which the read operation is performed is an unqualified resistive memory cell. For example, the information is a current value. When the read current value obtained by performing a read operation on a certain resistive memory cell is less than a predetermined current value, it can be determined that the resistive memory cell is an unqualified resistive memory cell. When the read current value obtained by performing a read operation on a certain resistive memory cell is greater than or equal to the predetermined current value, it can be determined that the resistive memory cell is a resistive memory cell that is qualified for setting. If there is an unqualified resistive memory cell, since it still maintains a high-resistance state, it does not affect subsequent tests.

Hereinafter, with reference to FIG. 10 , a test method provided by an embodiment of the present invention for testing whether there are reset unqualified resistive memory cells in the second memory cell group of the resistive memory device with the resistance state distribution shown in FIG. 9 will be described.

The test method may, for example, include steps P6 and C6.

In step P6, a reset operation is performed on the second memory cell group to change each resistive memory cell in the second memory cell group from a low-resistance state L to a high-resistance state H (see the examples in FIGS. 9 and 10 . line circle). For example, the reset operation is performed by providing a reset voltage to each of the resistive memory cell groups in the second memory cell group.

During the reset operation, each resistive memory cell in the first memory cell group remains in the high resistance state H or the initial high resistance state I. After the reset operation is completed, each resistive memory cell in the first memory cell group is still in the high resistance state H or the initial high resistance state I, while each resistive memory cell in the second memory cell group is in the normal state Both should be in the high-impedance state H.

Next, checking step C6 is performed.

In step C6, a read operation is performed on each resistive memory cell in the second memory cell group to obtain information indicating whether there is a resistive memory cell that fails to be reset in the second memory cell group. During the read operation, each resistive memory cell in the first memory cell group remains in the high-resistance state H or the initial high-resistance state I. For example, the read operation is performed by providing a read voltage to each resistive memory cell in the second memory cell group.

Here, when a read operation is performed on any resistive memory cell in the second memory cell group, the resistive memory cells at the four adjacent positions of the selected resistive memory cell are all in the high resistance state H or The initial high-impedance state I, therefore effectively avoiding the leakage current around the selected resistive memory cell, thereby accurately reading the information indicating the resistance state of each resistive memory cell in the second memory cell group, At the same time, the information can indicate whether the resistive memory cell subjected to the read operation is a reset-unqualified resistive memory cell. For example, the information is a current value. When the read current value obtained by performing a read operation on a certain resistive memory cell is greater than a predetermined current value, it can be determined that the resistive memory cell is a reset unqualified resistive memory cell. When the read current value obtained by performing a read operation on a certain resistive memory cell is less than or equal to the predetermined current value, it can be determined that the resistive memory cell is a reset qualified resistive memory cell. If there is a resistive memory cell unqualified for resetting, it can be repaired to be in a high-resistance state.

In one example, the above steps P5, C5, P6, and C6 may be repeated multiple times in sequence to test the resistance switching stability of each resistive memory cell in the second memory cell group subjected to the set/reset operation.

Hereinafter, with reference to FIG. 11 , a test method provided by an embodiment of the present invention for testing whether there are unqualified resistive memory cells in the first memory cell group of the resistive memory device having the resistance state distribution shown in FIG. 10 will be described.

The test method may, for example, include steps P7 and C7.

In step P7, a set operation is performed on the first memory cell group to change the resistive memory cells in the first memory cell group from a high-resistance state H to a low-resistance state L (see dotted circles in FIGS. 10 and 11 ). For example, the setting operation is performed by providing a setting voltage to each of the resistive memory cell groups in the first memory cell group.

During the set operation, each resistive memory cell in the second memory cell group remains in a high-resistance state H. After the setting operation is completed, each resistive memory cell in the second memory cell group is still in the high resistance state H, while in the first memory cell group, except for the unqualified resistive memory cell R24, each resistive memory cell The memory cells should all be in the low-resistance state L under normal conditions.

Next, checking step C7 is performed.

In step C7, a read operation is performed on each resistive memory cell in the first memory cell group to obtain information indicating whether there is a resistive memory cell with an unqualified configuration in the first memory cell group. During the read operation, each resistive memory cell in the second memory cell group remains in a high-resistance state H. For example, the read operation is performed by providing a read voltage to each resistive memory cell in the first memory cell group.

Here, when a read operation is performed on any resistive memory cell in the first memory cell group, the resistive memory cells at the four adjacent positions of the selected resistive memory cell are all in the high resistance state H, Therefore, the generation of leakage current around the selected resistive memory cell is effectively avoided, so that the information indicating the resistance state of each resistive memory cell in the first memory cell group can be accurately read out, and the information can also indicate the resistance state of the selected resistive memory cell. Whether the resistive memory cell performing the read operation is an unqualified resistive memory cell. For example, the information is a current value. When the read current value obtained by performing a read operation on a certain resistive memory cell is less than a predetermined current value, it can be determined that the resistive memory cell is an unqualified resistive memory cell. When the read current value obtained by performing a read operation on a certain resistive memory cell is greater than or equal to the predetermined current value, it can be determined that the resistive memory cell is a resistive memory cell that is qualified for setting. If there is an unqualified resistive memory cell, since it still maintains a high-resistance state, it does not affect subsequent tests.

Hereinafter, with reference to FIG. 12 , a test method provided by an embodiment of the present invention for testing whether there are reset unqualified resistive memory cells in the first memory cell group of the resistive memory device with the resistance state distribution shown in FIG. 11 will be described.

The test method may, for example, include steps P8 and C8.

In step P8, a reset operation is performed on the first memory cell group to change the resistive memory cells in the first memory cell group from a low-resistance state L to a high-resistance state H (see dotted circles in FIGS. 11 and 12 ) . For example, the setting operation is performed by providing a reset voltage to each of the resistive memory cell groups in the first memory cell group.

During the reset operation, each resistive memory cell in the second memory cell group remains in a high resistance state H. After the reset operation is completed, each resistive memory cell in the second memory cell group is still in the high resistance state H, while in the first memory cell group, except for the unqualified resistive memory cell R24, each resistive memory cell The variable memory cells should be in the high resistance state H under normal conditions.

Next, checking step C8 is performed.

In step C8, a read operation is performed on each resistive memory cell in the first memory cell group to obtain information indicating whether there is a resistive memory cell unqualified for reset in the first memory cell group. During the read operation, each resistive memory cell in the second memory cell group remains in a high-resistance state H. For example, the read operation is performed by providing a read voltage to each resistive memory cell in the first memory cell group.

Here, when a read operation is performed on any resistive memory cell in the first memory cell group, the resistive memory cells at the four adjacent positions of the selected resistive memory cell are all in the high resistance state H, Therefore, the generation of leakage current around the selected resistive memory cell is effectively avoided, so that the information indicating the resistance state of each resistive memory cell in the first memory cell group can be accurately read out, and the information can also indicate the resistance state of the selected resistive memory cell. Whether the resistive memory cell performing the read operation is a resistive memory cell unqualified for reset. For example, the information is a current value. When the read current value obtained by performing a read operation on a certain resistive memory cell is greater than a predetermined current value, it can be determined that the resistive memory cell is a reset unqualified resistive memory cell. When the read current value obtained by performing a read operation on a certain resistive memory cell is less than or equal to the predetermined current value, it can be determined that the resistive memory cell is a reset qualified resistive memory cell. If there is a resistive memory cell unqualified for resetting, it can be repaired to be in a high-resistance state.

In one example, the above steps P7, C7, P8, and C8 may be repeated multiple times in sequence to test the resistance switching stability of each resistive memory cell in the first memory cell group subjected to the set/reset operation.

In one example, the testing method may include the above steps P1, C1, P2, C2, P3, C3, P4, C4, P5, C5, P6, C6, P7, C7, P8, C8 in sequence. In this case, various types of unqualified resistive memory cells in the first and second memory cell groups (for example, forming unqualified resistive memory cells, resetting unqualified resistive memory cells, and setting unqualified resistive memory cells storage unit) can be effectively tested.

In one example, the forming operation may not be performed due to the characteristics of the resistive memory cell. In this case, the test method may include, for example, the above-mentioned steps P5, C5, P6, C6, P7, C7, P8, and C8 in sequence. In this way, various types of unqualified resistive memory cells (for example, resetting unqualified resistive memory cells and setting unqualified resistive memory cells) in the first and second memory cell groups can be effectively tested.

In one example, before the programming step, the testing method further includes a state judging step: judging whether at least one of the first memory cell group and the second memory cell group is in a high resistance state or initial state.

For example, in the above-mentioned embodiment, before step P1, it may be determined that the Both the first storage unit group and the second storage unit group are in an initial state. Similarly, in the above embodiment, before step P2, it may be determined that the second memory cell group is in the initial state based on the fact that the second memory cell group of the resistive memory device is in an inactive state after preparation . Before step P3, it may be determined that the second memory cell group is in an initial state based on the fact that the second memory cell group of the resistive memory device is in an inactive state after preparation.

For example, in the above embodiment, before step P4, it may be determined whether the first memory cell group is in a high-impedance state based on the read operation performed on the first memory cell group in step C2. Similarly, before step P5, the first and second memory cell groups may be determined based on the read operation performed on the first memory cell group in step C2 and the read operation performed on the second memory cell group in step C4. Whether the second storage cell group is in a high resistance state. Similarly, before step P6, it may be determined whether the first memory cell group is in a high resistance state based on the read operation performed on the first memory cell group in step C2. Similarly, before step P7, the first and second memory cell groups may be determined based on the read operation performed on the first memory cell group in step C2 and the read operation performed on the second memory cell group in step C6. Whether the second storage cell group is in a high resistance state. Similarly, before step P8, it may be determined whether the second memory cell group is in a high resistance state based on the read operation performed on the second memory cell group in step C6.

In an example, the test method further includes: when none of the first memory cell group and the second memory cell group is in a high-resistance state or an initial state, testing the plurality of resistance switches At least one of the memory cells performs a reset operation or a repair operation such that each resistive memory cell in at least one of the first memory cell group and the second memory cell group is in the high resistance state.

For example, when the resistance state of each resistive memory cell in the resistive memory device to be tested is unknown, each resistive memory cell in the first memory cell group and the second memory cell group can be Applying a reset voltage, in this case, the resistive memory cells in the low-resistance state undergo a reset operation and switch to a high-resistance state, so that the first memory cell group and the second memory cell group Each resistive memory cell is in a high resistance state or an initial state.

For example, the resistance state of each resistive memory cell in the first memory cell group and the second memory cell group is known but does not meet the requirements in the first memory cell group and the second memory cell group. When at least one group is in the high-resistance state or the initial state, perform a reset operation on at least one of the resistive memory cells in the low-resistance state so that the first memory cell group and the second memory cell Each resistive memory cell in at least one of the cell groups is in the high resistance state or the initial state.

For example, in the above-mentioned embodiment, referring to FIGS. 5 and 6, in step C2, it is found that the resistive memory cell R11 in the first memory cell group is a resistive memory cell R11 that is unqualified for reset, and it is changed to high impedance state. In this way, it can be ensured that each resistive memory cell in the first memory cell group is in the high resistance state H when step P3 is executed.

In the above test method provided by the embodiment of the present invention, when a read operation is performed on any resistive memory cell, the resistive memory cells at the four adjacent positions of the selected resistive memory cell are all in a high-impedance state Or an initial high-resistance state, thus effectively avoiding the leakage current around the selected resistive memory cell, thereby accurately judging whether the resistive memory cell is an unqualified resistive memory cell. In the case that the resistive memory cell is of the 1D1R type, the requirements on the performance of the selector can be reduced or eliminated.

Another embodiment of the present invention provides a testing device 20 for the resistive memory device 10 .

Referring to FIG. 13 , the testing device 20 includes, for example: a programming detection part 21 communicatively connected to the plurality of resistive memory cells R11-R55, for selecting the first memory cell group and the second memory cell group When at least one group is in a high-impedance state or an initial state, a program signal Sp is output to one of the first memory cell group and the second memory cell group to perform a program operation and a read signal Sr is output to experience performing a read operation on at least one resistive memory cell subjected to the programming operation to form information indicating whether at least one resistive memory cell is qualified, wherein, during the programming operation and during the read operation, no The memory cell group undergoing the program operation remains in a high resistance state or an initial state.

Here, the program signal is any one of a form signal, a reset signal, and a set signal. The form signal, reset signal and set signal are used for the form operation, reset operation and set operation, respectively. Here, the group of memory cells that have not undergone the programming operation refers to a group in which each resistive memory cell has not received a programming signal and has not undergone the programming operation. The programming signal Sp is, for example, a formation voltage signal Vf, a reset voltage signal Vreset or a set voltage signal Vset. When the program detection part 21 provides a forming voltage signal Vf to a group of the first memory cell group and the second memory cell group, the group can be switched from the initial state to a low-resistance state; in the program detection part 21. When a reset voltage signal Vreset is provided to one of the first memory cell group and the second memory cell group, the group can be switched from a low-resistance state to a high-resistance state; Setting the voltage signal Vset to one of the first memory cell group and the second memory cell group enables the group to switch from a high resistance state to a low resistance state; here, it can be understood that the programming signal Sp and the readout signal Sr may also be current signals.

In one example, the program detection part 21 is used for when both the first memory cell group and the second memory cell group are in an initial state or when the first memory cell group and the second When one of the memory cell groups is in the initial state and the resistive memory cells in the other group are in the high-resistance state or the initial state, a forming signal is output to the group in the initial state to perform a forming operation to switching the resistive memory cells in the group to the low-resistance state, and outputting a read signal to the memory cell group that has undergone the forming operation to perform a read operation to obtain an indication of whether the resistive memory cells in the group are Passed information is formed, wherein, during the forming operation and during the readout operation, another group that has not undergone the forming operation remains in the initial state or the high-resistance state.

In one example, the programming detection part 21 is used to set one of the first memory cell group and the second memory cell group in the high resistance state or the initial state and the other group in the low resistance state In the case of , output a reset signal to a group in the low resistance state to perform a reset operation to switch the resistive memory cells in the group to the high resistance state, and output a read signal to experience the set A read operation is performed on the memory cell group for the reset operation to obtain information indicating whether the reset of the resistive memory cells in the group is qualified, wherein, during the reset operation and during the read operation, the reset operation has not been experienced The resistive memory cell in the reset operation remains in the high resistance state or the initial state.

In one example, the program detection part 21 is configured to output a set signal to the first memory cell group and the second memory cell group when both the first memory cell group and the second memory cell group are in the high-impedance state. A group of second memory cells performs a set operation to switch the resistive memory cells in the group to the low-resistance state, and outputs a readout signal to the group of memory cells subjected to the set operation to perform readout. operating to obtain information indicating whether the resistive memory cells in the group are set qualified, wherein during the set operation and during the read operation, the resistive memory cells that have not undergone the set operation remain in the high resistance state.

As shown in FIG. 13 , the testing equipment 20 of the resistive variable memory device 10 may further include: a state adjustment part 22, configured to determine whether the first memory cell group and the second memory cell group are not both in a high-resistance state or In the case of an initial state, a reset signal is output to at least one of the plurality of resistive memory cells to perform a reset operation, so that each of the two groups of the first memory cell group and the second memory cell group A resistive memory unit is in the high resistance state or the initial state.

As shown in FIG. 13 , the test equipment 20 of the resistive variable memory device 10 may further include: a connection state detection part 23 . The state detection part 23 is used to output a readout signal to at least one of the first memory cell group and the second memory cell group to obtain information indicating the resistance state of the resistive memory cell, according to the indicated Resistively change the information of the resistance state of the memory unit to determine whether at least one of the first memory cell group and the second memory cell group is in a high resistance state or an initial state, and output a state detection indicating the result of the above judgment The signal is sent to the program detection part 21 and the state adjustment part 22.

The program detection section 21 outputs a programming signal to the first memory cell in response to a state detection signal that at least one of the first memory cell group and the second memory cell group is in a high resistance state or an initial state. group and one of the second group of memory cells for a programming operation.

The state adjustment part 22 outputs a reset signal to the plurality of resistive switches in response to a state detection signal that none of the first memory cell group and the second memory cell group is in a high resistance state or an initial state. at least one of the memory cells to perform a reset operation.

For example, in the case that the resistive memory device to be tested is not in a manufactured and inactivated state, but is in an unknown resistance state distribution, the state detection part 23 of the testing device 20 can first output the read signal to The first memory cell group and the second memory cell group are two groups to obtain a plurality of current values indicating the resistance state of each resistive memory cell; for example, the state detection part 23 of the testing device 20 judges In the first memory cell group and the second memory cell group, only the resistive memory cell R22 in the first memory cell group is in a low-resistance state, R43 in the second memory cell group is in an initial high-resistance state, and all other resistance-switching memory cells are in a low-resistance state. The variable memory cells are all in a high resistance state; then, the state detection part 23 of the testing device 20 outputs a state detection signal indicating the above judgment result to the programming detection part 21 and the state adjustment part 22. The state adjustment part 22 outputs a reset signal to the resistive memory unit R22 in the first memory cell group in response to the above state detection signal to perform a reset operation so that the resistive memory unit R22 switches from a low resistance state to a high resistance state . Alternatively, the state adjusting part 22 outputs a reset signal to each resistive memory cell in the first and second memory cell groups in response to the above state detection signal to perform a reset operation so that the resistive memory cell R22 has a low resistance state switches to a high-impedance state. At this time, the state detection part 23 outputs a readout signal to the first memory cell group and the second memory cell group through the state detection part 23 of the testing device 20 again to obtain the resistance value indicating each resistive memory cell. For example, the state detection part 23 of the testing device 20 judges and obtains each resistive memory cell in the first memory cell group and the second memory cell group according to the multiple current values It is in the high-impedance state or the initial state, and outputs a state detection signal indicating the above judgment result to the programming detection part 21 and the state adjustment part 22 . Based on the state detection signal, the programming detection part 21 can, for example, start to execute the steps P5, C5, P6, C6, P7, C7, P8, and C8 described in the above embodiments in sequence. In this way, various types of unqualified resistive memory cells (for example, resetting unqualified resistive memory cells and setting unqualified resistive memory cells) in the first and second memory cell groups can be effectively tested.

It can be understood that, although the testing device 20 shown in FIG. The programming detection section 21 is included. In the case that the test equipment 20 only includes the programming detection part 21, the resistance state of each memory cell group can be manually judged or judged by another testing device, and then the programming step and the testing step are started manually. and state adjustment steps. In another example, the testing device 20 may only include the programming detection part 21 and the state detection part 23 . In this case, the resistance state of each memory cell group can be judged by the state detection section 23, for example. In the case that none of the first and second memory cell groups is in a high-resistance state or an initial state, at least one of the plurality of resistive memory cells can be reset or repaired manually. The operation is such that at least one of the first and second memory cell groups is in a high resistance state or an initial state.

Here, the programming detection part 21 , the state adjustment part 22 and the state detection part 23 may include, for example, various control circuits, drive circuits, selection circuits, etc., respectively, to realize the above-mentioned functions.

In the test equipment provided by the embodiment of the present invention, when performing a read operation on any resistive memory unit during the test of the resistive memory unit, the four adjacent positions of the selected resistive memory unit The resistive memory cells are all in a high-resistance state or an initial high-resistance state, thus effectively avoiding leakage current around the selected resistive memory cell, thereby accurately judging whether the resistive memory cell is an unqualified resistive memory cell storage unit. In the case that the resistive memory cell is of the 1D1R type, the requirements on the performance of the selector can be reduced or eliminated.

Although the present invention has been described in detail with general descriptions and specific implementations above, it is obvious to those skilled in the art that some modifications or improvements can be made on the basis of the embodiments of the present invention. Therefore, the modifications or improvements made on the basis of not departing from the spirit of the present invention all belong to the protection scope of the present invention.

Claims (16)

1. a kind of test method of resistance-change memory device, the resistance-change memory device includes multiple resistance-change memories into array arrangement Unit, the array include submitting at least one odd-numbered line for arrangement and at least one even number line in a first direction；And It is described more different from least one odd column being arranged alternately in the second direction of the first direction and at least one even column A variable-resistance memory unit can be divided into the first memory cell group and the second memory cell group, wherein, in first memory cell group Each variable-resistance memory unit line number and the sum of row number be even number, each resistance-change memory list in second memory cell group The sum of line number and row number of member are odd number, and each variable-resistance memory unit is designed as with original state, high-impedance state and low-resistance shape State, the test method comprise the following steps：

Programming step：There is at least one set to be in high-impedance state in first memory cell group and second memory cell group Or in the case of original state, behaviour is programmed to one group in first memory cell group and second memory cell group Make to change the resistance state of the variable-resistance memory unit in described group, wherein, do not undergo the programming behaviour during the programming operation Another group made remains original state or high-impedance state；And

Detecting step：Reading is performed at least one variable-resistance memory unit that experienced the programming operation in above-mentioned programming step Operation to obtain indicating the whether qualified information of at least one variable-resistance memory unit, wherein, described read behaviour performing During work, do not undergo the programming operation another group remains original state or high-impedance state, wherein, the original state is Another high-impedance state,

Wherein, for the programming operation to form operation, reset operation or setting operation, the formation operational design is by the resistance Become storage unit and low resistive state is switched to by original state；The reset operation is designed as the variable-resistance memory unit by low-resistance State is switched to high-impedance state；The setting operational design is that the variable-resistance memory unit is switched to low-resistance shape by high-impedance state State, wherein, it is less than in the resistance value of the variable-resistance memory unit of the low resistive state in the high-impedance state or the initial shape The resistance value of the variable-resistance memory unit of state.

2. the test method of resistance-change memory device according to claim 1, wherein,

In the case where first memory cell group and second memory cell group are in original state, or described First memory cell group and the second memory cell group one of which are in the resistance in the original state and wherein another group Become storage unit and be in the high-impedance state, one group in original state is performed to be formed operate with by the resistive in described group Storage unit switches to the low resistive state, wherein not undergoing another group of guarantor for forming operation during the formation operation Hold as the original state or the high-impedance state；And

Read operation is performed to the memory cell group that experienced the formation operation to obtain indicating variable-resistance memory unit in the group Whether the information of qualification is formed, wherein, during the read operation is performed, another group of holding for forming operation is not undergone For original state or high-impedance state.

3. the test method of resistance-change memory device according to claim 1, wherein,

The high-impedance state or described first is in first memory cell group and the second memory cell group one of which In the case that beginning state and wherein another group are in low resistive state, to one group of carry out reset operation in the low resistive state with Variable-resistance memory unit in described group is switched into the high-impedance state, wherein not undergone during the reset operation described heavy Put operation another group remains the high-impedance state or the original state；And

Read operation is performed to the memory cell group that experienced the reset operation to obtain indicating variable-resistance memory unit in the group Whether the information of qualification is reset, wherein, during the read operation is performed, another group of holding of the reset operation is not undergone For original state or high-impedance state.

4. the test method of resistance-change memory device according to claim 1, wherein,

In the case where first memory cell group and second memory cell group are in the high-impedance state, to described One group in first memory cell group and second storage unit is configured operation with by the resistance-change memory list in described group Member switches to the low resistive state, is protected wherein not undergoing the variable-resistance memory unit for setting operation during the setting operation Hold as the high-impedance state；And

Read operation is performed to the variable-resistance memory unit that experienced the setting operation to obtain indicating resistance-change memory list in the group Whether member sets the information of qualification, wherein, during the read operation is performed, another group of guarantor that operation is set is not undergone Hold as high-impedance state.

5. the test method of resistance-change memory device according to claim 1, further includes：In first memory cell group and In the case that second memory cell group is not in high-impedance state or original state, to the multiple variable-resistance memory unit In at least one execution reset operation or repair operation so that first memory cell group and second memory cell group Each variable-resistance memory unit in two groups is in the high-impedance state or original state.

6. the test method of resistance-change memory device according to any one of claim 1 to 5, further includes：Perform described The programming step is performed again after detecting step.

7. the test method of resistance-change memory device according to any one of claim 1 to 5, before the programming step Further include：

Condition adjudgement step：Judge whether there is at least one set of place in first memory cell group and second memory cell group In high-impedance state or original state.

8. the test method of resistance-change memory device according to claim 7, wherein, the condition adjudgement step includes：Base At least one group un-activation shape after the completion of preparing in first memory cell group and second memory cell group State and determine at least one set be in original state.

9. the test method of resistance-change memory device according to claim 7, wherein, the condition adjudgement step includes：It is right At least one set of execution read operation in first memory cell group and second memory cell group, to obtain indicating described first Whether at least one set of information in high-impedance state or original state is had in memory cell group and second memory cell group.

10. a kind of test equipment of resistance-change memory device, the resistance-change memory device includes depositing into multiple resistives of array arrangement Storage unit, the array include submitting at least one odd-numbered line for arrangement and at least one even number line in a first direction；And At least one odd column and at least one even column being arranged alternately on the second direction different from the first direction, it is described Multiple variable-resistance memory units can be divided into the first memory cell group and the second memory cell group, wherein, first memory cell group In each variable-resistance memory unit line number and the sum of row number be even number, each resistance-change memory in second memory cell group The sum of line number and row number of unit are odd number, and each variable-resistance memory unit is designed as including original state, high-impedance state and low-resistance State,

The test equipment includes：

Program detection part, for thering is at least one set to be in first memory cell group and second memory cell group In the case of high-impedance state or original state, output programming signal to first memory cell group and second storage unit One group in group is deposited with being programmed operation and output read output signal at least one resistive that experienced the programming operation Storage unit and perform read operation with obtain indicating at least one variable-resistance memory unit whether qualified information, wherein, During the programming operation and during the read operation, do not undergo the programming operation another group remains high resistant shape State or original state, wherein, the original state is another high-impedance state,

Wherein, the programming signal is to form signal, the reset signal for reset operation or for setting for formation operation The setting signal of operation is put, the formation operational design is that the variable-resistance memory unit is switched to low-resistance shape by original state State；The reset operation is designed as the variable-resistance memory unit being switched to high-impedance state by low resistive state；It is described that operation is set It is designed as the variable-resistance memory unit being switched to low resistive state by high-impedance state, wherein, in the resistance of the low resistive state Become the resistance value of storage unit less than the resistance value in the high-impedance state or the variable-resistance memory unit of the original state.

11. the test equipment of resistance-change memory device according to claim 10, wherein,

The program detection part is used to be in initial shape in first memory cell group and second memory cell group The initial shape is in the case of state or in first memory cell group and the second memory cell group one of which In the case that variable-resistance memory unit in state and wherein another group is in the high-impedance state, output forms signal and arrives in initially One group of state and perform to form operation so that the variable-resistance memory unit in described group is switched to the low resistive state, and output Read output signal performs read operation to obtain indicating that resistive is deposited in the group to experienced the memory cell group for forming operation Whether storage unit forms the information of qualification, wherein, formed described during operation and during the read operation, do not undergo institute State and to form another group of operation and remain the original state or the high-impedance state.

12. the test equipment of resistance-change memory device according to claim 10, wherein,

The program detection part is used to be in described in first memory cell group and the second memory cell group one of which In the case that high-impedance state or the original state and wherein another group are in low resistive state, described in output reset signal is arrived and is in One group of low resistive state and carry out reset operation so that the variable-resistance memory unit in the group is switched to the high-impedance state, it is and defeated Go out read output signal and perform read operation to the memory cell group that experienced the reset operation to obtain indicating resistive in the group Whether storage unit resets the information of qualification, wherein, during the reset operation and during the read operation, do not undergo described Another group of reset operation remains the high-impedance state or the original state.

13. the test equipment of resistance-change memory device according to claim 10, wherein,

The program detection part is used to be in the high resistant shape in first memory cell group and second memory cell group In the case of state, export setting signal and be configured behaviour to one group in first memory cell group and second storage unit Make so that the variable-resistance memory unit in the group switched to the low resistive state, and output read output signal is to experienced the setting The memory cell group of operation and perform read operation to obtain indicating whether variable-resistance memory unit in the group sets the information of qualification, Wherein during the setting operates and during the read operation, another group that operation is set is not undergone and remains the height Resistance state.

14. the test equipment of resistance-change memory device according to claim 10, further includes：

State adjustment member, for first memory cell group and second memory cell group be not in high-impedance state or In the case of original state, at least one reset with execution exported in reset signal to the multiple variable-resistance memory unit is grasped Make so that each variable-resistance memory unit in two groups of first memory cell group and second memory cell group is in described High-impedance state or original state.

15. the test equipment of resistance-change memory device according to claim 10, further includes：

State detection portion, for exporting in read output signal to first memory cell group and second memory cell group at least One group to obtain indicating the information of the resistance state of the variable-resistance memory unit, according to the institute for the resistance state for indicating the variable-resistance memory unit State information judge whether to have in first memory cell group and second memory cell group it is at least one set of in high-impedance state or Original state, and the state detection signal of the result of the above-mentioned judgement of output indication is to the program detection part,

Wherein, the program detection partial response has at least in first memory cell group and second memory cell group One group of state detection signal in high-impedance state or original state and export programming signal to first memory cell group and One group in second memory cell group is operated with being programmed, wherein, institute is not undergone during the programming operation is performed State programming operation another group remains original state or high-impedance state.

16. the test equipment of resistance-change memory device according to claim 14, further includes：

State detection portion, for exporting in read output signal to first memory cell group and second memory cell group at least One group to obtain indicating the information of the resistance state of the variable-resistance memory unit, according to the institute for the resistance state for indicating the variable-resistance memory unit State information judge whether to have in first memory cell group and second memory cell group it is at least one set of in high-impedance state or Original state, and the state detection signal of the result judged described in output indication is to the program detection part and the state Adjustment member,

Wherein, the state adjustment member for not being in response to first memory cell group and second memory cell group It is in the state detection signal of high-impedance state or original state and exports reset signal into the multiple variable-resistance memory unit It is at least one to perform reset operation so that it is every in two groups of first memory cell group and second memory cell group A variable-resistance memory unit is in the high-impedance state or original state,

The program detection part is used to locate in response to two groups of first memory cell group and second memory cell group Programming signal is exported to first memory cell group and described in the state detection signal of high-impedance state or original state One group in two memory cell groups is operated with being programmed, wherein, do not undergo the programming operation during the programming operation Another group remain original state or high-impedance state.