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CN105762084B - Packaging method and packaging device of flip chip - Google Patents

Packaging method and packaging device of flip chip Download PDF

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Publication number
CN105762084B
CN105762084B CN201610282085.6A CN201610282085A CN105762084B CN 105762084 B CN105762084 B CN 105762084B CN 201610282085 A CN201610282085 A CN 201610282085A CN 105762084 B CN105762084 B CN 105762084B
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China
Prior art keywords
packaging
semiconductor chip
substrate
carrier
package
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CN201610282085.6A
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CN105762084A (en
Inventor
石磊
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Nantong Fujitsu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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Publication of CN105762084A publication Critical patent/CN105762084A/en
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

The invention discloses a packaging method and a packaging device of a flip chip, wherein the method comprises the steps of providing a carrier and a packaging substrate, wherein the carrier comprises a bearing area, a fixing part is arranged on the carrier, and the packaging substrate is used for packaging a semiconductor chip; and fixing the carrier on a machine table of packaging equipment by using the fixing part, and fixing the packaging substrate in the bearing area so as to package the semiconductor chip. By the mode, the substrate space can be saved, the waste of substrate materials is reduced, and the cost is reduced.

Description

Packaging method and packaging device of flip chip
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method and an apparatus for packaging a flip chip.
Background
The interconnection technology is one of the key technologies in microelectronic packaging, and has a significant impact on the quality, efficiency and cost of microelectronic packaging products, and mainly includes two packaging technologies, namely wire bonding and Flip chip (Flip chip). The flip chip package has the characteristics of high density, high performance, light weight, short size, low packaging cost and easy realization of chip stacking and three-dimensional packaging processes, and has been found as the main development of packaging technology.
Referring to fig. 1 and 2, the flip chip packaging technique is mainly to deposit tin lead balls 13 on the active surface of the semiconductor chip 11, and then turn the active surface of the semiconductor chip 11 upside down and heat it to bond the molten tin lead balls 13 with the traces or leads on the substrate unit 12 or other carrier, circuit board, or the like. After the semiconductor chip 11 and the substrate unit 12 are bonded to each other, the semiconductor chip 11 is subjected to plastic molding, so that a package layer 14 is formed on the surface of the semiconductor chip 11, and the package layer 14 covers the entire surface of the semiconductor chip 11 to protect the semiconductor chip 11 and the substrate unit 12.
As shown in fig. 2, in the conventional packaging technology, a "multi-chip package" is mostly performed, that is, a mother substrate 20 is divided into a plurality of substrate units 12, and then a plurality of semiconductor chips 11 are flip-chip mounted on the plurality of substrate units 12 one by one, and each substrate unit 12 is packaged with one semiconductor chip 11. After the semiconductor chip 11 is flip-chip mounted on the substrate unit 12, the semiconductor chip 11 is subjected to plastic molding, and then the mother substrate 20 is cut to separate a plurality of substrate units, thereby obtaining a plurality of independent package structures. Since the mother substrate 20 has a large area and is easily deformed and warped due to stress during packaging, a certain space is usually reserved between the substrate units 12 or a partial region between the substrate units 12 is hollowed out to reduce the stress.
In the packaging process, the mother substrate 20 is directly placed on a machine of a packaging device, in order to fix the mother substrate 20 to the machine of the device, for example, in the plastic packaging process, the mother substrate 20 needs to be fixed to the machine of the plastic packaging device, a positioning hole 201 is usually formed in the mother substrate 20, and then a positioning pin on the machine passes through the positioning hole 201 on the mother substrate 20, so as to fix the mother substrate 20 on the machine. However, in the above method, the mother substrate 20 needs to reserve a certain space for disposing the positioning holes 201, and the substrate region where the positioning holes 201 are disposed will be discarded after the dicing, so that the mother substrate cannot be used for completely packaging the semiconductor chips, which results in waste of substrate materials and is not favorable for reducing the production cost.
Disclosure of Invention
The invention mainly solves the technical problem of providing a packaging method and a packaging device of a flip chip, which can improve the utilization rate of a substrate and is beneficial to reducing the cost.
In order to solve the technical problems, the invention adopts a technical scheme that: provided is a flip chip packaging method, including: providing a carrier and a packaging substrate, wherein the carrier comprises a bearing area, a fixing part is arranged on the carrier, and the packaging substrate is used for packaging a semiconductor chip; and fixing the carrier on a machine table of packaging equipment by using the fixing part, and fixing the packaging substrate in the bearing area so as to package the semiconductor chip.
The carrier is of a groove structure, the groove structure comprises four frames connected end to end and a groove bottom connected with the four frames, the bearing area is located at the bottom of the groove, and the fixing portion is a positioning hole formed in the frames.
The bottom of the groove is an adhesive film adhered to the frame.
The carrier is a flat plate-shaped bearing plate, and the fixing part is a positioning hole arranged on the bearing plate.
The number of the packaging substrates is multiple, the packaging substrates are mutually independent, each packaging substrate is used for packaging at least one semiconductor chip, and the bearing area is provided with a positioning mark used for positioning each packaging substrate; the step of fixing the package substrate in the carrying region includes: and fixing a plurality of packaging substrates on the bearing area according to the positioning marks.
Wherein, the step of providing the substrate bearing frame and the packaging substrate comprises the following steps: a plurality of the semiconductor chips are also provided, the surfaces of the semiconductor chips comprise a first surface and a second surface, the first surface is provided with a first connecting terminal, the packaging substrate comprises a third surface and a fourth surface, and a second connecting terminal is formed on the third surface; after the step of fixing the package substrate in the carrying region, the method includes: arranging the first surface of the semiconductor chip and the corresponding third surface of the packaging substrate oppositely, and welding the first connecting terminal and the second connecting terminal together; and forming an encapsulation layer on the surface of the semiconductor chip, and exposing at least part of the second surface.
Wherein, after the step of forming the packaging layer on the surface of the semiconductor chip, the method comprises the following steps: and forming a heat dissipation layer on the exposed second surface.
Wherein the step of forming an encapsulation layer on the surface of the semiconductor chip comprises: disposing a barrier layer on a portion of the second surface of the semiconductor chip; filling a first packaging material in a space between the barrier layer and the bearing area; curing the first packaging material to form the packaging layer on the surface of the semiconductor chip; removing the barrier layer to expose the portion of the second surface.
Wherein the barrier layer is an elastic adhesive film; the step of providing a barrier layer on a portion of the second surface of the semiconductor chip comprises: and arranging the barrier layer on an upper film of the plastic package mold, and laminating the upper film on the second surface through the barrier layer.
Wherein after the step of removing the barrier layer, comprising: and cutting the packaging layer positioned between the packaging substrates to separate the packaging substrates, and forming the packaging layer on the rest surfaces except the fourth surface in the packaging substrates.
Wherein, after the step of oppositely arranging the first surface of the semiconductor chip and the corresponding third surface of the package substrate and soldering the first connection terminal and the second connection terminal together, the method comprises: and forming an underfill layer between the first surface of the semiconductor chip and the corresponding third surface of the package substrate.
In order to solve the technical problem, the invention adopts another technical scheme that: the packaging device comprises a carrier, wherein the carrier comprises a bearing area, the bearing area is used for fixing a packaging substrate, and the packaging substrate is used for packaging a semiconductor chip; the carrier is provided with a fixing part so as to be fixed on a machine table of packaging equipment by using the fixing part, and a semiconductor chip fixed on the packaging substrate in the bearing area is packaged.
The carrier is of a groove structure, the groove structure comprises four frames connected end to end and a groove bottom connected with the four frames, the bearing area is located at the bottom of the groove, and the fixing portion is a positioning hole formed in the frames.
The bottom of the groove is an adhesive film adhered to the frame.
The invention has the beneficial effects that: different from the situation of the prior art, in the packaging method of the invention, the carrier provided with the fixing part is provided, the carrier is fixed on the machine table of the packaging equipment by using the fixing part, and the packaging substrate for packaging the semiconductor chip is arranged in the bearing area of the carrier, so that the packaging substrate is fixed on the machine table, and the semiconductor chip can be packaged.
Further, in the packaging of the semiconductor chip, by exposing a part of the second surface of the semiconductor chip, compared with the existing method of wrapping the plastic packaging layer on the surface of the whole semiconductor chip, the semiconductor chip can be cooled through the exposed second surface, which is beneficial to improving the cooling effect of the semiconductor chip.
Drawings
FIG. 1 is a schematic diagram of a semiconductor chip according to the prior art;
FIG. 2 is a top view of a prior art mother substrate for packaging semiconductor chips;
FIG. 3 is a flow chart of one embodiment of a flip chip packaging method of the present invention;
FIG. 4 is a schematic structural diagram of an embodiment of the packaging device of the present invention;
FIG. 5 is a schematic cross-sectional view of the packaged device of FIG. 4 taken along the direction AB;
FIG. 6 is a schematic flow chart showing a structure corresponding to each step of a flip chip packaging method according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a semiconductor chip according to an embodiment of the flip chip packaging method of the present invention;
FIG. 8 is a schematic diagram of a heat sink layer formed on the exposed second surface according to an embodiment of the flip chip packaging method of the present invention;
FIG. 9 is a schematic flow chart of forming a packaging layer on the surface of a semiconductor chip according to an embodiment of the flip chip packaging method of the present invention, showing a corresponding structural schematic of each step;
fig. 10 is a schematic diagram of forming a bottom encapsulation layer between a semiconductor chip and a package substrate according to an embodiment of the flip chip packaging method of the invention.
Detailed Description
In the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The invention can be implemented in a number of ways different from those described herein and similar generalizations can be made by those skilled in the art without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
Aiming at the defects mentioned in the background technology, the invention provides a packaging method of a flip chip. The present invention will be described in further detail with reference to the accompanying drawings and embodiments.
Referring to fig. 3, an embodiment of the flip chip packaging method of the present invention includes the following steps:
step S301: the carrier comprises a bearing area, a fixing part is arranged on the carrier, and the packaging substrate is used for packaging the semiconductor chip.
Referring to fig. 4 and 5, in an embodiment of the present invention, the carrier 40 is a substrate carrying frame, which has a groove structure. Wherein the carrier 40 comprises four side frames 41 connected end to end and a groove bottom 42 connected with the four side frames 41, the carrying area is located at the groove bottom 42. The carrier 40 is provided with a fixing portion, where the fixing portion is a positioning hole 411 disposed on the frame 41, for example, the positioning hole 411 may be disposed on two opposite frames 41, or disposed on two adjacent frames 41, and specifically may be disposed according to a machine of the packaging apparatus. The frame 41 may be made of metal, plastic, ceramic, or other materials.
In the present embodiment, the bottom 42 of the groove is a glue film adhered to the frame. The adhesive film may be a photosensitive adhesive film having a relatively high viscosity, so that the package substrate is fixed by adhesion.
The package substrate may be a mother substrate including a plurality of substrate units, or may be an individual substrate unit separated from the mother substrate. In this embodiment, the package substrate refers to a substrate unit, one substrate unit is, for example, a circuit board, and is used for packaging semiconductor chips, and other circuit components, such as passive components, may also be packaged on the substrate unit, where the semiconductor chips packaged on each package substrate may be single or multiple, and may be specifically determined by an actual circuit structure. Each package substrate corresponds to one or more package units, and in this embodiment, each package substrate preferably corresponds to one package unit.
Step S302: the carrier is fixed on a machine table of the packaging equipment by using the fixing part, and the packaging substrate is fixed in the bearing area so as to package the semiconductor chip.
When a semiconductor chip is packaged on a package substrate, it usually needs to go through a plurality of process steps, such as cleaning, flip-chip mounting, plastic packaging, cutting, etc., and the packaging equipment includes equipment required at each process station, such as flip-chip mounting equipment, plastic packaging equipment, etc. By using the carrier of the embodiment of the invention, when the packaging substrate needs to be fixed, the packaging substrate can be fixed on a machine table of packaging equipment by using the carrier so as to carry out corresponding operation.
For example, during the flip-chip process, the package substrate needs to be fixed on a machine of the flip-chip apparatus. At this time, the carrier 40 may be fixed on the stage of the flip-chip apparatus through the positioning hole 411, and then the package substrate may be fixed on the carrying area of the carrier 40, so that the package substrate is fixed on the stage of the flip-chip apparatus, and then the semiconductor chip may be flip-chip mounted on the package substrate by using the flip-chip apparatus. Alternatively, the package substrate may be fixed on the carrying area of the carrier 40, and then the carrier 40 may be fixed on the stage of the flip-chip device.
After the semiconductor chip is flip-chip mounted on the package substrate, the semiconductor chip is subjected to a plastic package process. Specifically, the carrier 40 is taken out from the machine table of the flip-chip device, and the carrier 40 carrying the package substrate is fixed on the machine table of the plastic package device through the positioning hole 411, so that the semiconductor chip on the package substrate is plastic-packaged by the plastic package device. After the molding is completed, the groove bottom 42 of the carrier 40, i.e., the adhesive film, is peeled off to expose the bottom of the package substrate for subsequent operations. Since the bottom 42 of the groove is made of photoresist, the bottom 42 of the groove can be illuminated to reduce the viscosity of the bottom 42 of the groove, and then the bottom 42 of the groove can be peeled off the frame 41.
In the embodiment, the carrier 40 is used to fix the package substrate on the platform of the packaging device so as to package the semiconductor chip on the package substrate, compared with the prior art, the package substrate can be fixed on the platform without arranging a positioning hole on the mother substrate, therefore, the mother substrate does not need to reserve a space to form the positioning hole, the substrate space can be saved, more package substrates can be obtained for the mother substrate with the same size, thereby more semiconductor chips can be packaged, and the production cost can be reduced.
In addition, in the present embodiment, since one package substrate is a single substrate unit separated from the mother substrate, the package is performed in units of substrate units having an area smaller than that of the mother substrate during the packaging process, and the stress applied to the package substrate can be reduced to some extent, so that the degree of deformation and warpage of the package substrate can be reduced. Moreover, for the mother substrate, a certain space does not need to be reserved between the substrate units or a part of area between the substrate units does not need to be hollowed out like the existing mother substrate, the space of the mother substrate can be further saved, the mother substrate can be effectively utilized to package more semiconductor chips, the production cost can be further reduced, and the process of the mother substrate can be simplified.
In addition, in the present embodiment, the bottom 42 of the groove of the carrier 40 is an adhesive film, so that after the plastic package is completed, the adhesive film can be better peeled off by using the soft characteristic of the adhesive film, and the damage to the bottom of the package substrate caused by the peeling process can be reduced.
In another embodiment, the carrier 40 may further include a bottom plate, which may be a metal plate, a plastic plate, or the like. The adhesive film is attached to the bottom plate, the bottom plate with the adhesive film attached thereto is connected to the four frames 41 to form a groove bottom 42 of the carrier 40, the adhesive film faces the opening direction of the groove, and the package substrate is fixed to the adhesive film. Through setting up a bottom plate, can improve the intensity of carrier 40 bottoms, avoid among the packaging process glued membrane fracture. Of course, the carrier 40 may also be a groove structure with four rims and a groove bottom integrally formed.
In other embodiments of the present invention, the carrier may also be a flat plate-shaped carrier plate, the carrying area of the carrier plate is an area on the carrier plate, for example, the middle area of the carrier plate is a carrying area, and the fixing portion is a positioning hole disposed on the carrier plate, and the position of the positioning hole can be determined according to the structure of the machine. At this time, in the packaging process, when the packaging substrate is fixed on the carrier plate, a layer of adhesive film may be attached to the carrier region, the packaging substrate is fixed on the adhesive film, and then the carrier plate is fixed on the machine through the positioning hole for operation. The flat-plate-shaped bearing plate is used as a carrier of the packaging substrate, so that the packaging substrate can be fixed on a machine table, and meanwhile, the manufacturing process of the carrier can be reduced.
To better describe the packaging method of the present invention, one package substrate in which a semiconductor chip is packaged is defined as one package body. In order to improve the production efficiency, a plurality of package substrates are usually packaged with the required semiconductor chips at the same time, so as to produce a plurality of packages at the same time. By using the carrier 40 of the present invention, it is possible to package a plurality of package substrates with required semiconductor chips at the same time, wherein the carrying area of the carrier 40 can be divided into a plurality of small blocks, and each small block carries at least one package substrate.
More specifically, referring to fig. 6 in conjunction with fig. 4 and 5, fig. 6 is a flowchart of an embodiment of a flip chip packaging method according to the present invention, in which the structure corresponding to each step is illustrated, and elements with the same reference number in the diagram have the same function. Where only two package substrates are shown in fig. 6, it will be understood by those skilled in the art that when carrier 40 is large enough, its carrier area may carry more package substrates for producing multiple packages simultaneously. The method comprises the following steps:
in step S601, a plurality of semiconductor chips 62 are provided in addition to the carrier 40 and the plurality of package substrates 61. The plurality of package substrates 61 are independent of each other, and as an example, only two semiconductor chips 62 are shown in the figure, and each semiconductor chip 62 is correspondingly packaged on one package substrate 61, however, as mentioned above, more semiconductor chips and other components can be packaged on the package substrate 61, and can be determined according to the actual circuit.
Wherein the surface of the semiconductor chip 62 includes a first surface 621 and a second surface 622. The first surface 621 is an active surface of the semiconductor chip 62, i.e., a surface having a circuit structure, and is a front surface of the semiconductor chip 62, and the second surface 622 is a back surface of the semiconductor chip 62. First connection terminals 623 are formed on the first surface 621, wherein four first connection terminals 623 are shown, and the first connection terminals 623 are electrically connected to circuit structures (not shown) in the semiconductor chip 62.
The package substrate 61 includes opposite third and fourth surfaces 611 and 612. The third surface 611 has second connection terminals 613 formed thereon, and the fourth surface 612 has third connection terminals 614 formed thereon. The second connection terminals 613 and the third connection terminals 614 are electrically connected to each other, and the connection relationship between the second connection terminals 613, between the third connection terminals 614, and between the second connection terminals 613 and the third connection terminals 614 may be determined according to actual circuit requirements, and the illustration is merely an example.
In step S602, a plurality of package substrates 61 are fixed on the carrier region, specifically, on the groove bottom 42 of the carrier 40. The groove bottom 42 is provided with a positioning mark for positioning each package substrate 61, and the positioning mark may be a positioning line or a positioning symbol, for example. A plurality of package substrates 61 are fixed on the groove bottom 42 according to the positioning marks.
In step S603, the first surface 621 of the semiconductor chip 62 and the corresponding third surface 611 of the package substrate 61 are oppositely disposed and the first connection terminal 623 on the first surface 621 and the second connection terminal 613 on the third surface 611 are soldered together, so that the semiconductor chip 62 is flip-chip mounted on the package substrate 61. Each semiconductor chip 62 is flip-chip mounted on a package substrate 61.
Wherein, the first connection terminal 623 can be interconnected with the second connection terminal 613 of the package substrate 61 after being dipped with the soldering flux; a Non-Conductive Paste (NCP) may be applied to the surface of the package substrate 61, and the first connection terminal 623 of the semiconductor chip 62 and the second connection terminal 613 of the package substrate 61 may be interconnected by Thermal Compression Bonding (TCB).
In one possible embodiment, referring to fig. 7, the first connection terminal 623 is a solder bump, and may be a structure of a metal bump (stud bond) + solder formed by a bonding process. Here, the first connection terminal 623 may be formed by forming a bonding metal bump 6231 on the pad in advance and forming a solder layer 6232 on the metal bump 6231. When the first surface 621 of the semiconductor chip 62 and the third surface 611 of the package substrate 61 are oppositely disposed, the solder layer 6232 of the first connection terminal 623 and the second connection terminal 613 on the third surface 611 are contacted, so that the solder layer 6232 on the metal bump 6231 is melted by the reflow process, and the metal bump 6231 and the second connection terminal 613 are soldered together, thereby achieving interconnection of the semiconductor chip 62 and the package substrate 61. In another embodiment, a metal bump may be formed on the second connection terminal 613, and then interconnected with the first connection terminal 623 of the semiconductor chip 62 by the metal bump on the second connection terminal 613. By forming the first or second connection terminals with metal bumps to interconnect the package substrate 61 and the semiconductor chip 62, the height of the gap between the semiconductor chip 62 and the package substrate 61 can be increased, thereby facilitating the filling of the molding compound in the molding process.
Of course, in other embodiments, the first connection terminal 623 may be a ball-shaped solder ball (solder ball) formed by solder, a columnar solder bump (pillar bump), or the like.
Continuing to refer to fig. 6, in step S604, a molding layer 63 is formed on the surface of the semiconductor chip 62, and the second surface 622 is exposed. After the semiconductor chip 62 is fixed to the package substrate 61, the semiconductor chip 62 is molded so that a molding layer 63 is formed on the surface of the semiconductor chip 62. Specifically, the groove 42 is filled with a molding compound, and then the molding compound is cured by heating or other means, thereby forming the molding layer 63. In the present embodiment, the molding layer 63 is formed using an epoxy resin material as a sealing layer of the semiconductor chip 62, that is, the molding material is an epoxy resin material. The molding layer 63 wraps most of the surface of the semiconductor chip 62, and the molding layer 63 is not formed on the second surface 622 so that the second surface 622 is exposed.
The exposed second surface 622 is the back surface of the semiconductor chip 62 opposite to the first surface 621, and the side surface of the semiconductor chip 62 and the first surface 621 are wrapped by the molding layer 63. Further, the gap between the first surface 621 of the semiconductor chip 62 and the third surface 611 of the package substrate 61 is also filled with the molding layer 63.
Step S605 is further included, in which the bottom 42 of the groove is removed, and solder bumps 615 are formed on the third connection terminals 614 on the fourth surface 612 of the package substrate 61, so as to form a package similar to a Ball Grid Array (BGA) package, and then the package is interconnected with the next layer. The solder bump 615 may be a solder ball or a combination of a metal bump and solder. In other embodiments, if the third connection terminal 614 of the package substrate 61 is directly interconnected as a signal terminal with a next layer assembly to form a package similar to a Land Grid Array (LGA) profile, the solder bump 615 does not need to be formed on the third connection terminal 614.
In step S606, the molding compound 63 located between the package substrates 61 is cut to separate the package substrates 61, and the molding compound 63 is formed on the remaining surfaces of each package substrate 61 except the fourth surface 612. As shown in the figure, in the cutting process, the molding layer 63 is cut to separate a plurality of package structures, and a portion of the molding layer 63 remains on both sides of each package substrate 61. The package structure refers to a structure including a package substrate 61 and a semiconductor chip 62 fixed on the package substrate 61.
Because the plastic package layer 63 is cut, compared with the traditional method of cutting the mother substrate, the method of the present embodiment can retain a part of the plastic package layer 63 on both sides of the package substrate 61 during the cutting process, which is beneficial to protecting the internal circuit of the package substrate 61.
In the conventional packaging method, the molding compound layer usually wraps up the whole semiconductor chip, which results in that the semiconductor chip can only radiate heat outwards through the packaging substrate, and in this embodiment, the second surface 622 opposite to the first surface 621 is exposed, so that the heat of the semiconductor chip 62 can be radiated out through the second connecting terminal 613 of the packaging substrate 61 via the packaging substrate 61, and can be radiated through the exposed second surface 621, thereby greatly improving the heat radiation capability of the semiconductor chip 62, making the heat radiation effect of the semiconductor chip 62 more, and being beneficial to improving the stability of the circuit.
In another embodiment of the present invention, in order to further improve the heat dissipation capability of the semiconductor chip 62, referring to fig. 8, after the step of forming the molding layer 63 on the surface of the semiconductor chip 62, it may further include the following steps: a heat spreading layer 64 is formed on the exposed second surface 622. The heat dissipation layer 64 may be made of aluminum material with better heat dissipation performance. Wherein the heat dissipation layer 64 may be formed on the exposed second surface 622 of each semiconductor chip 62 after the molding layer 63 is cut.
Referring to fig. 9, in an embodiment of the packaging method of the present invention, the plastic encapsulation process may expose a portion of the second surface 622 by disposing a barrier layer. Specifically, the step of forming the molding layer 63 on the surface of the semiconductor chip 62, i.e., step S604 shown in fig. 6, further includes the following sub-steps:
in the substep S6041, before the upper film 92 of the plastic package mold is closed and pressed, a barrier layer is disposed on the upper film 92, and the barrier layer is an elastic adhesive film 91.
In the substep S6042, the upper film 92 with the adhesive film 91 is pressed on the second surface 622 of the semiconductor chip 62, that is, the upper mold 92 of the plastic mold is pressed with the semiconductor chip 62 through the adhesive film 91. Thereby disposing the adhesive film 91 on the second surface 622 of the semiconductor chip 62.
In sub-step S6043, a space between the adhesive film 91 and the carrying region is filled with a plastic sealing material, and then the plastic sealing material is cured to form the plastic sealing layer 63. The bearing area is the groove bottom 42, that is, a space between the adhesive film 91 and the groove bottom 42 is filled with a plastic sealing material. The molding compound may be an epoxy resin material. Wherein the molding compound is caused to fill the gap between the semiconductor chip 62 and the third surface 611 of the package substrate 61.
In step S6044, the upper film 92 and the adhesive film 91 are removed to expose the second surface 622 attached to the adhesive film 91.
After the adhesive film 91 is removed, step S605 shown in fig. 6 is performed.
In this embodiment, by disposing a layer of adhesive film 91 on the second surface 622 of the semiconductor chip 62, the plastic material can be prevented from overflowing onto the second surface 622 during the plastic package process, so that the plastic package layer 63 can be prevented from being formed on the second surface 622. In addition, the adhesive film 91 of the present embodiment is an elastic adhesive film, so that the upper film 92 of the mold can be pressed on the adhesive film 91, so that the adhesive film 91 can be tightly attached to the second surface 622 of the semiconductor chip 62, the plastic material is further prevented from overflowing onto the second surface 622, and the adhesive film 91 can absorb the stress of the upper film 92 to prevent the upper film 92 from crushing the semiconductor chip 62.
Further, by the adhesive film 91, a solder height tolerance caused by the semiconductor chip 62 during reflow soldering can be adjusted. Specifically, after the semiconductor chip 62 and the package substrate 61 which are oppositely arranged are subjected to reflow soldering to perform soldering therebetween, there may be a height difference between the plurality of semiconductor chips 62, resulting in that the exposed second surfaces 622 of the plurality of semiconductor chips 62 are not on the same plane. In the subsequent plastic package process, by arranging the adhesive film 91 with elasticity, when the pressing plate 92 is pressed on the adhesive film 91, the adhesive film 91 can be tightly attached to the plurality of semiconductor chips 62 with inconsistent heights by utilizing the elasticity of the adhesive film 91, so that a larger gap is prevented from being formed between the adhesive film 91 and the lower semiconductor chip 62, and therefore the packaging material can be prevented from overflowing to the exposed second surface 622.
In an embodiment of the present invention, a TCB/NCP process is used in the flip chip process, and the gap between the package substrate 61 and the semiconductor chip 62 is filled with NCP before plastic encapsulation. Specifically, as shown in fig. 10, before the step of forming the molding layer 63 on the surface of the semiconductor chip 62, i.e., before step S604, after the semiconductor chip 62 and the package substrate 61 are soldered together, NCP underfill is performed to a gap between the first surface 621 of the semiconductor chip 62 and the third surface 611 of the package substrate 61 to form the underfill layer 34.
In other embodiments, the underfill may be performed by dispensing. Of course, when the distance between the semiconductor chip 62 and the package substrate 61 is large, the flow of the molding material into the space between the semiconductor chip 62 and the package substrate 61 is facilitated, and therefore, the chip can be directly molded without underfill.
When the distance between the semiconductor chip 62 and the package substrate 61 is small, the gap between the semiconductor chip 62 and the package substrate 61 is first filled with the underfill, so that the probability of the internal cavity caused by the difficulty in filling the gap between the first surface 621 of the semiconductor chip 62 and the third surface 611 of the package substrate 61 with the material of the molding layer 33 can be reduced.
In the above embodiment, by providing the adhesive film 91 to prevent the first packaging material from covering the second surface 622 opposite to the first surface 621, so as to expose the second surface 622 opposite to the first surface 621, in other embodiments of the present invention, the second surface 622 may also be exposed in other manners. For example, without providing the adhesive film 91, the semiconductor chip 62 is filled with a first encapsulating material to form an encapsulating layer that wraps the entire surface of the semiconductor chip 62, and then the encapsulating layer on a second surface opposite to the first surface is removed by a process such as cutting, grinding, or chemical etching to expose a part of the second surface. Alternatively, the amount of the first packaging material can be controlled such that the first packaging material after filling is located under the second surface opposite to the first surface, thereby preventing the first packaging material from flooding the second surface opposite to the first surface and exposing the second surface opposite to the first surface.
In addition, as shown in fig. 6, the exposed second surface 622 is the entire second surface opposite to the first surface 621, in other embodiments, the exposed second surface may also be a portion of the second surface opposite to the first surface 621, and the shape of the exposed second surface may be a trapezoid, a circle, an irregular shape, or the like.
The present invention also provides an embodiment of a packaging device comprising a carrier, wherein the structure and method of use of the carrier is the same as the structure and method of use of the carrier of any of the preceding embodiments.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (5)

1. A method of packaging a flip chip, comprising:
providing a carrier, a plurality of mutually independent packaging substrates and a plurality of semiconductor chips, wherein the carrier comprises a bearing area, the bearing area is provided with a positioning mark for positioning each packaging substrate, a fixing part is arranged on the carrier, the packaging substrates are independent substrate units separated from a mother substrate, each packaging substrate is used for packaging at least one semiconductor chip, the surface of each semiconductor chip comprises a first surface and a second surface, a first connecting terminal is formed on the first surface, the packaging substrate comprises a third surface and a fourth surface, and a second connecting terminal is formed on the third surface;
fixing the carrier on a machine table of packaging equipment by using the fixing part, and fixing the packaging substrates in the bearing area through adhesive films according to the positioning marks;
arranging the first surface of the semiconductor chip and the corresponding third surface of the packaging substrate oppositely, and welding the first connecting terminal and the second connecting terminal together;
disposing a barrier layer on a portion of the second surface of the semiconductor chip;
filling a plastic packaging material in a space between the barrier layer and the bearing area;
solidifying the plastic packaging material to form a packaging layer on the surface of the semiconductor chip;
removing the barrier layer to expose a portion of the second surface;
forming a heat dissipation layer on the exposed second surface;
wherein the barrier layer is an elastic adhesive film, and the step of providing a barrier layer on a part of the second surface of the semiconductor chip comprises: and arranging the barrier layer on an upper film of the plastic package mold, and laminating the upper film on the second surface through the barrier layer.
2. The packaging method according to claim 1, wherein the carrier has a groove structure, the groove structure includes four side frames connected end to end and a groove bottom connected to the four side frames, the bearing area is located at the groove bottom, and the fixing portions are positioning holes disposed on the side frames.
3. The package method as claimed in claim 1, wherein the carrier is a plate-shaped carrier, and the fixing portions are positioning holes disposed on the carrier.
4. The method of claim 1, wherein after the step of removing the barrier layer, comprising:
and cutting the packaging layer positioned between the packaging substrates to separate the packaging substrates, and forming the packaging layer on the rest surfaces except the fourth surface in the packaging substrates.
5. The packaging method according to claim 1, wherein the step of disposing the first surface of the semiconductor chip and the corresponding third surface of the package substrate opposite to each other and soldering the first connection terminal and the second connection terminal together comprises:
and forming an underfill layer between the first surface of the semiconductor chip and the corresponding third surface of the package substrate.
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