CN105762187B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device, comprising: a plurality of fins extending along a first direction on a substrate; a plurality of gate stacks and a plurality of contact lines extending along a second direction on the substrate and spanning the plurality of fins; insulating layer, filled between a plurality of gate stacks and a plurality of contact lines; source and drain regions, in a plurality of fins, distributed on both sides of the plurality of gate stacks; wherein, between two adjacent gate stacks there are One or more contact lines, the contact lines form source-drain contacts on the source-drain regions. According to the semiconductor device and its manufacturing method of the present invention, a double patterning process is used to form spaced sacrificial gate lines and sacrificial source-drain contact lines across the fin structure, and the two are sequentially removed by selective etching to fill the final gate The electrode and the final source-drain contact improve the reliability of the source-drain contact.

Description

Semiconductor device and method of manufacturing the same

technical field

The present invention relates to a semiconductor device and its manufacturing method, in particular to a self-aligned source-drain contact FinFET and its manufacturing method.

Background technique

Three-dimensional multi-gate devices such as fin field effect transistors (FinFETs) and tri-gate (tri-gate) devices are among the most promising new device technologies as device dimensions scale down to 22nm technology and below, and these structural enhancements The gate control ability is improved, and the leakage and short channel effects are suppressed.

For conventional processes, CMOS devices including FinFETs, tri-gate devices are gate patterned and contacts are formed by the following steps to achieve isolated functional devices:

1. The gate is patterned using a line--and--cut dual lithography patterning technique and subsequent etching of the gate stack;

2. Use uniform feature size and pitch to print parallel lines for gate patterning in one direction;

3. Arrange gate line ends (tips) only at predetermined grid nodes;

4. Form conductive contact holes for device gate electrodes and source/drain electrodes by photolithography and etching after forming the inter-device insulating dielectric layer.

The above approach has some advantages:

1. Simplified lithography for special lighting modes;

2. Eliminates many of the proximity effects that complicate lithography, etching and OPC.

FinFET and tri-gate devices are three-dimensional (3D) devices unlike planar CMOS devices. Typically, semiconductor fins are formed on bulk or SOI substrates by selective dry or wet etching, and then gate stacks are formed across the fins. Three-dimensional tri-gate transistors form conductive channels on all three sides of the vertical fin structure, thereby providing a "fully depleted" mode of operation. Tri-gate transistors can also have multiple fins connected to increase the overall drive capability for higher performance.

However, as FinFET devices enter the 22nm technology node and shrink further, it is difficult for 3D FinFETs, especially for SOI FinFETs, to form self-aligned source-drain contacts on nanometer-sized fin source-drain regions, the contact and gate The distance between them is difficult to precisely control, which may easily cause device interconnection errors, resulting in device failure and reduced reliability.

SUMMARY OF THE INVENTION

From the above, the purpose of the present invention is to overcome the above technical difficulties and improve the reliability of the FinFET source-drain contact.

To this end, the present invention provides a semiconductor device, comprising: a plurality of fins extending along a first direction on a substrate; a plurality of gate stacks and a plurality of contact lines extending along a second direction on the substrate and Across a plurality of fins; an insulating layer, filled between a plurality of gate stacks and a plurality of contact lines; source and drain regions, in the plurality of fins, distributed on both sides of the plurality of gate stacks; wherein, adjacent two There are one or more contact lines between the gate stacks, and the contact lines form source-drain contacts on the source-drain regions.

Wherein, the substrate is a thick substrate or an SOI substrate.

Wherein, each of the plurality of gate stacks includes a gate insulating layer of a high-k material and a gate conductive layer of a metal material.

Wherein, the source and drain regions include metal silicide.

Wherein, the plurality of gate stacks and the plurality of contact lines have the same pitch and size.

Wherein, the starting positions and/or lengths of the plurality of gate stacks and the plurality of contact lines along the second direction are the same.

Wherein, each two sides of the plurality of gate stacks is one of the source region or the drain region, and the two sides of the plurality of contact lines are the same source region or drain region.

The present invention also provides a method for manufacturing a semiconductor device, comprising: forming a plurality of fins extending in a first direction on a substrate; forming a plurality of sacrificial gate stacks and a plurality of sacrificial gate stacks extending in a second direction on the substrate a sacrificial contact stack spanning the plurality of fins; source and drain regions are formed in the plurality of fins and on both sides of the plurality of sacrificial gate stacks; an insulating layer is formed between the plurality of sacrificial gate stacks and the plurality of sacrificial contact stacks; Selective etching removes a plurality of sacrificial gate stacks, leaving a first opening in the insulating layer, and filling a plurality of gate stacks in the first opening; selective etching removes a plurality of sacrificial contact stacks, leaving a plurality of sacrificial contact stacks in the insulating layer Lower the second opening, and fill a plurality of contact lines in the second opening.

Wherein, the step of forming a plurality of sacrificial gate stacks and a plurality of sacrificial contact stacks further includes: forming a sacrificial stack on the substrate, including a liner layer, a sacrificial layer and a cap layer, spanning and covering the plurality of fins; forming a plurality of gate masks extending along the second direction; etching the sacrificial stack until the sacrificial layer is exposed, leaving a plurality of cap layer lines extending along the second direction; forming one or more cap layer lines between the plurality of cap layer lines a plurality of contact masks; etching the sacrificial stack until the plurality of fins are exposed, leaving a plurality of sacrificial gate stacks consisting of a liner layer, a sacrificial layer and a capping layer conformal to the plurality of gate masks, and A plurality of sacrificial contact stacks consisting of a liner layer and a sacrificial layer conformal to the contact mask.

The liner layer includes silicon oxide, the sacrificial layer includes amorphous silicon, polycrystalline silicon, amorphous germanium, amorphous carbon, diamond-like amorphous carbon (DLC) and combinations thereof, and the cap layer includes silicon nitride, silicon oxynitride and their combinations. combination.

Wherein, the plurality of sacrificial gate stacks and the plurality of sacrificial contact stacks have the same spacing and size, and have the same starting positions and/or lengths along the second direction.

Wherein, lightly doped source and drain regions and/or heavily doped source and drain regions are formed by ion implantation.

Wherein, the insulating layer is formed by a conformal deposition process.

Wherein, the step of leaving the first opening in the insulating layer further includes: sequentially selectively etching the cap layer, the sacrificial layer and the liner layer of the plurality of sacrificial gate stacks until the plurality of fins are exposed, and the plurality of sacrificial contact stacks are subjected to The insulating layer protects from being etched.

Wherein, each of the plurality of gate stacks includes a gate insulating layer of a high-k material and a gate conductive layer of a metal material.

Wherein, the step of leaving the second opening in the insulating layer further includes: CMP planarizing the insulating layer until the sacrificial layers of the plurality of sacrificial contact stacks are exposed, and sequentially selectively etching the sacrificial layers and the liner layer of the plurality of sacrificial contact stacks until Expose multiple fins.

Wherein, filling the plurality of contact lines in the second opening further includes: forming a metal silicide on the source and drain regions; forming a blocking layer on the metal silicide; and forming a source-drain contact on the blocking layer.

The etching process for removing the cap layer, the sacrificial layer and the liner layer by etching is selective dry etching or wet etching.

According to the semiconductor device and its manufacturing method of the present invention, a double patterning process is used to form spaced sacrificial gate lines and sacrificial source-drain contact lines across the fin structure, and the two are sequentially removed by selective etching to fill the final gate The electrode and the final source-drain contact improve the reliability of the source-drain contact.

Description of drawings

The technical solutions of the present invention are described in detail below with reference to the accompanying drawings, wherein:

1 to 13 are schematic diagrams illustrating steps of a method for manufacturing a semiconductor device according to the present invention.

Detailed ways

The features and technical effects of the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the schematic embodiments, and a FinFET with improved source-drain contact reliability and a manufacturing method thereof are disclosed. It should be noted that similar reference numerals denote similar structures, and the terms "first", "second", "upper", "lower", etc. used in this application may be used to modify various device structures or fabrication processes . These modifications do not imply a spatial, sequential, or hierarchical relationship of the modified device structures or fabrication processes unless otherwise specified.

It is worth noting that in the following Figures 1 to 13, the left part of each figure is a top view of the device, and the right part is shown along the AA' section line in the top view (the vertical fins extend and distribute The cross-section line in the first direction, that is, along the second direction, through the gate stack structure) or the BB' cross-section line (parallel to the first direction of the fin, and through a fin) obtained Cutaway view.

As shown in FIG. 1 , a semiconductor layer 2 is provided on a substrate 1 . The substrate 1 is preferably an insulating substrate, such as an insulating and electrically isolated substrate such as plastic, resin, ceramic, glass, etc., and preferably has good thermal conductivity, such as an electrical device with a heat sink or a concave-convex heat dissipation fin structure on the back. Insulating and thermally conductive substrates. The semiconductor layer 2 is formed on the insulating substrate 1 by processes such as PECVD, HDPCVD, MBE, ALD, evaporation, sputtering, etc., or is peeled off from the surface of other temporary support substrates (not shown) by wafer lift-off technology and attached to the insulating substrate. bottom 1. The material of the semiconductor layer 2 is, for example, crystalline silicon (Si), single crystal germanium (Ge), strained silicon (Strained Si), silicon germanium (SiGe), SOI, GeOI, or compound semiconductor materials such as gallium nitride (GaN), Gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as graphene, SiC, carbon nanotubes, and the like. For compatibility with the CMOS process, the semiconductor layer 2 is preferably bulk Si/Ge or SOI/GeOI. In a preferred embodiment of the present invention, both the insulating substrate 1 and the semiconductor layer 2 are and/or form part of an SOI or GeOI substrate, that is, the insulating substrate 1 is a thick Si/Ge substrate (not shown). ) surface thinner (eg 10-100nm) oxide layer (buried oxide layer BOX), semiconductor layer 2 is a thinner top semiconductor layer (top Si layer or top Ge layer, with a thickness of eg 5 on top of the oxide layer) ~40nm). As shown in FIG. 1 , at the beginning of the entire process, the semiconductor layer 2 completely covers the top surface of the insulating substrate 1 . In another embodiment of the present invention, the substrate 1 is a thick Si substrate, such as a Si wafer, and the semiconductor layer 2 is a Si layer on the surface of the Si substrate.

As shown in FIG. 2 , the semiconductor layer 2 is patterned to leave a plurality of mutually parallel fin structures 2F on the substrate 1 . Preferably, a hard mask layer (not shown) is formed on the semiconductor layer 2 by conventional processes such as LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, etc., and its material can be selected from silicon oxide, silicon nitride , silicon oxynitride, amorphous carbon, diamond-like amorphous carbon (DLC), etc. and combinations thereof. A photoresist of polymer material is formed on the hard mask layer by processes such as spin coating, spray coating, screen printing, etc., and then exposed and developed using a preset template to obtain a plurality of parallel photoresist lines. Using the photoresist line as a mask, dry etching is performed on the hard mask layer to form a plurality of parallel insulating material lines (extending and distributed along the first direction) on the semiconductor layer 2 . For example, the length/width of the hard mask line itself (in the direction AA' in the figure, that is, along the extension direction of the final device gate stack or called the second direction) is set according to the driving capability of the device. The spacing and pitch between them are 50 to 100 nm. Although periodic lines are shown in the diagrams of the present invention, in fact, the width and pitch of the lines can be reasonably set according to the needs of the layout design, that is, the line layout can be discrete and discrete. Then, using the pattern of the hard mask layer as a mask, the semiconductor layer 2 is anisotropically etched and stopped on the substrate 1, and a plurality of trenches distributed in parallel along the first direction and between the trenches are formed in the semiconductor layer 2 The fins 2F formed by the remaining semiconductor layer 2 material. The aspect ratio of the trenches, or the aspect ratio of the fins 2F, is preferably greater than 5:1. In an embodiment of the present invention, the etching process may be wet etching. For the semiconductor layer 2 made of Si (single crystal Si or SOI) material, the wet etching etchant is tetramethylammonium hydroxide (TMAH) Or KOH solution, for other materials (SiGe, Ge, GaN, etc.), a combination of strong acid (eg, sulfuric acid, nitric acid) and strong oxidant (eg, hydrogen peroxide, ozone-containing deionized water) can be used. In another embodiment of the present invention, the etching process is, for example, plasma dry etching or reactive ion etching, and the reactive gas may be a fluorocarbon-based etching gas or other halogen-based etching gas (such as chlorine gas, hydrogen chloride, bromine vapor) , hydrogen bromide, etc.). In a preferred embodiment of the present invention, the plurality of fins 2F have the same pitch and fin dimensions (eg, three-dimensional dimensions such as width, height, length, etc.). In the case where the substrate 1 is a buried oxide layer BOX in an SOI substrate, the fins 2F formed by a plurality of semiconductor layers 2 are isolated and insulated from each other by the buried oxide layer 1 at the bottom; the substrate 1 is a single crystal silicon substrate In this case, a silicon oxide or silicon nitride dielectric layer may be additionally deposited between the fins 2F and etched back to partially expose the fins 2F, leaving a shallow trench isolation structure STI (not shown) on the substrate 1 ).

As shown in FIG. 3, a sacrificial stack 3A is formed on the entire substrate 1, covering the surface of the substrate 1, the top surface and sidewalls of the fins 2F, and spanning all and/or a portion of the plurality of fin structures 2F, In addition, a plurality of gate masks 3B extending along the second direction (preferably perpendicular to the first direction) are formed on the sacrificial stack 3A. A liner layer 3A1, a sacrificial layer 3A2, and a cap layer 3A3 are sequentially formed on the substrate 1 through processes such as LPCVD, PECVD, HDPCVD, MBE, ALD, evaporation, and sputtering to form a sacrificial stack 3A. The liner layer 3A1, such as silicon oxide, is used to protect the substrate 1 in the subsequent etching process to reduce interface defects. The liner layer preferably covers not only the surface of the substrate 1, the top surface of the fin 2F, but also the fin 2F. side wall. The sacrificial layer 3A2, such as amorphous silicon, polycrystalline silicon, amorphous germanium, amorphous carbon, diamond-like amorphous carbon (DLC), etc., is used to define the pattern of the sacrificial lines and improve the etching selectivity ratio with adjacent materials. The sacrificial layer is completely The trenches between the fins 2F are filled. The cap layer 3A3 is, for example, a hard material such as silicon nitride and silicon oxynitride, which is used to protect the sacrificial layer 3A2 from erosion during subsequent etching or planarization, so as to achieve the desired selective etching effect, preferably planarization cover layer. Then, a plurality of gate masks 3B extending and distributed along the second direction are formed on the top of the sacrificial stack 3A, especially the cap layer 3A3, for example, a photoresist material formed by processes such as spin coating, spray coating, screen printing, embossing, etc. The soft mask is then exposed and developed by DUV or EUV to pattern into a plurality of gate mask lines 3B; Silicon, etc., to improve the etch selectivity) and photolithography (such as DUV, EUV lithography)/etch the hard mask formed. The plurality of gate masks 3B have the same line spacing and size, for example, the width and spacing along the first direction are the same, and the length and starting position along the second direction are the same.

As shown in FIG. 4 , using the plurality of gate masks 3B as masks, the exposed sacrificial stack 3A is etched, and the cap layer 3A3 not covered by the gate masks 3B is removed. An anisotropic dry etching process is preferably used, such as adjusting the carbon-fluorine ratio and flow rate of the carbon-fluorine-based etching gas, controlling the vertical etching rate and the etching selection ratio with adjacent materials (the etching rate difference of different materials) ), improve the etching of the capping layer 3A3 made of silicon nitride and silicon oxynitride, remove part of the capping layer 3A3 not covered by the mask 3B, and expose the sacrificial layer 3A2 below for the subsequent double patterning process . Subsequently, the dry method (oxygen plasma etching) or wet method (etching by a mixed solution of strong oxidant and strong acid or strong alkali, adding organic solvent) process lifts off the mask 3B, leaving the mask 3B under the original position of the gate mask 3B. Mold 3B conformal capping line 3A3 serves as the top capping layer for subsequent sacrificial gate stacks.

As shown in FIG. 5, a double patterning process is performed to form one or more contact masks 3C in parallel (ie, extending in the second direction) between the capping lines 3A3. Similar to the process and material of the gate mask 3B, the contact mask 3C may be a photoresist or a hard mask. In a preferred embodiment of the present invention, the contact mask 3C and the gate mask 3B/the remaining cap layer lines 3A3 have the same spacing and size, for example, the width and spacing along the first direction are equal, and the length and starting length along the second direction are equal. position is equal. The lengths of the contact mask 3C and the cap layer lines 3A3 along the second direction may be the same or very close, for example, generally between 20 and 50 nm, preferably between 30 and 40 nm. It is worth noting that the right side of FIGS. 1 to 4 are sectional views along line AA in the second direction, while the right side of FIGS. 5 to 13 are sectional views along the first direction BB and passing through the fin 2F.

As shown in FIG. 6 , using the cap layer line 3A3 and the contact mask 3C as masks, the sacrificial layer 3A2 and the liner layer 3A1 below are etched in sequence until the fins 2F are exposed, and a sacrificial gate stack (including the cap layer line) is formed. 3A3 and the sacrificial layer 3A2, liner layer 3A1, which are conformal thereunder, and the sacrificial contact stack (including the sacrificial layer 3A2, liner layer 3A1, which are conformal under the contact mask 3C). The etching is preferably anisotropic dry etching, such as plasma dry etching or reactive ion etching (RIE) to adjust the carbon-fluorine ratio and flow rate, or mixed wet etching for sacrificial layer materials, such as TMAH for polysilicon , amorphous silicon, or oxygen plasma dry etching for the sacrificial layer of amorphous carbon and DLC materials, etc. Since the material of the contact mask 3C is different from that of the cap layer 3A3, the sacrificial layer 3A2, and the liner layer 3A1, such as a soft photoresist pattern, the contact mask 3C is not etched during the etching process, but is etched during the etching process. After the etching is completed, it is stripped by a dry or wet process, thereby leaving the sacrificial contact stack not including the contact mask 3C.

As shown in FIG. 7, using the plurality of sacrificial gate stacks and the plurality of sacrificial contact stacks as masks, ion implantation is performed, and in the fin structure 2F exposed in FIG. 6, the sacrificial gate stacks (3A3/3A2/3A1) The source and drain regions of the device are formed on both sides. Preferably, lightly doped ion implantation is performed first to form a lightly doped source-drain extension region (ESD, not shown) with a small junction depth in the fin, and then heavily doped ion implantation is performed to form a heavily doped ion implantation in the fin. Doping and heavily doped source and drain regions 2S and 2D with large junction depth. Further, annealing may be performed after performing the ion implantation to activate the implanted impurities. The type of implanted ions is opposite to that contained in the semiconductor layer 2 and the fin structure 2F. For example, the substrate 1 and the semiconductor layer 2 are n--, and the source and drain regions are p, p+, and vice versa. In the embodiment of the present invention, one of the source and drain regions on both sides of the sacrificial gate stack is used as a source region and the other is used as a drain region, and the source and drain regions on both sides of the sacrificial contact stack are both source regions or both drain regions (At this time, due to the activation annealing, the vertically implanted impurity ions will diffuse in the fins and enter under the sacrificial contact stack and are preferably connected, as shown on the right side of Figure 7).

As shown in FIG. 8, an insulating layer 4 is formed on the entire device, covering the surface of the substrate 1, the top surface and sidewalls of the sacrificial gate stack (3A3/3A2/3A1), and the top of the sacrificial contact stack (3A2/3A1). face, side wall, completely fill the gap between the two. In an embodiment of the present invention, a deposition process with high step coverage such as PECVD, HDPCVD, MBE, and ALD is used to deposit insulating dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride or low-k dielectric materials, and the deposition is controlled The process parameters are such that the insulating layer 4 is a conformally deposited layer, ie the insulating layer 4 completely fills the gap between the sacrificial gate stack and the sacrificial contact stack without leaving holes. Low-k materials include, but are not limited to, organic low-k materials (such as organic polymers containing aromatic groups or multiple rings), inorganic low-k materials (such as amorphous carbon nitride films, polycrystalline boron nitride films, fluorosilicate glass, BSG, PSG) , BPSG), porous low-k materials such as disiloxane (SSQ) based porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymer). After the insulating layer 4 is deposited, a planarization process such as CMP or etchback is used to planarize the insulating layer 4 until the sacrificial gate stack (eg, the cap layer 3A3 on top thereof) is exposed. At this time, the sacrificial contact stack is not exposed but is covered by the insulating layer 4 full coverage. The deposition steps of the insulating layer 4 are similar to the process of device spacer formation and device interlayer dielectric layer (ILD), but unlike these conventional devices, the FinFET of the present invention does not require additional device spacers. In addition to the self-aligned formation of the gate stack lines and source-drain contact lines, the gate side and source-drain contacts are electrically isolated, which saves process steps and improves device manufacturing accuracy.

As shown in FIG. 9 , the plurality of sacrificial gate stacks are etched away, leaving first openings or trenches 4T1 in insulating layer 4 until fins 2F are exposed. First, the cap layers 3A3 on top of the exposed sacrificial gate stacks 3A are removed by selective etching, for example, by adjusting the ratio and flow rate of etching gases in dry plasma etching or RIE, so that the materials of each layer can be selected for etching. High performance (the etching rate is at least 5 times higher than the etching rate of other adjacent materials), or wet etching is used for each layer material, such as hot phosphoric acid for silicon nitride, strong oxidants (hydrogen peroxide, ozone-containing deoxidizers) The mixed solution of ionized water) and strong acid (hydrofluoric acid, hydrochloric acid) is used for silicon oxynitride, etc., KOH and TMAH are used for polysilicon, amorphous silicon, etc., and oxygen plasma dry etching is used for the sacrificial layer of amorphous carbon and DLC. The liner layer of silicon oxide is etched by HF and BOE. In the etching step shown in FIG. 9 , since the tops of the plurality of sacrificial contact stacks are not exposed but are covered and protected by the insulating layer 4 , the sacrificial layer 3A2 and the liner layer 3A1 of the sacrificial contact lines are not eroded.

As shown in FIG. 10, the final gate stack 5G is formed in the first opening or trench 4T1. The gate stack 5G, including the gate insulating layer 5G1 and the gate conductive layer 5G2, is conformally deposited by PECVD, HDPCVD, MBE, ALD, magnetron sputtering and other processes. The gate insulating layer 5G1 is preferably silicon oxide, nitrogen-doped silicon oxide, silicon nitride, or other high-k materials. The high-k materials include, but are not limited to, _HfO2 , _HfSiOx , HfSiON, _HfAlOx , _HfTaOx , HfLaO Hafnium-based materials of _x , HfAlSiO _x , HfLaSiO _x (wherein, the content of oxygen atoms x can be adjusted reasonably according to the proportion of multi-metal components and chemical valence of each material, for example, it can be 1-6 and is not limited to an integer), or include Rare earth-based high-K dielectric materials selected from ZrO ₂ , La ₂ O ₃ , LaAlO ₃ , TiO ₂ , Y ₂ O ₃ , or a composite layer including Al ₂ O ₃ , or the above materials. The gate conductive layer 5G2 may be polysilicon, polysilicon germanium, or metal, wherein the metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Simple metals such as Ir, Eu, Nd, Er, La, or alloys of these metals and nitrides of these metals, the gate conductive layer 5G2 can also be doped with C, F, N, O, B, P, As, etc. elements to adjust the work function. A nitride barrier layer (not shown) is preferably formed between the gate conductive layer 5G2 and the gate insulating layer 5G1 by conventional methods such as PVD, CVD, ALD, etc., and the barrier layer material is M _x N _y , M _x Si _y N _z , _MxAlyNz , _MaAlxSiyNz , _where M _{is Ta} , _Ti , _Hf , Zr, Mo, W or other elements. More preferably, the gate conductive layer 5G2 and the barrier layer not only use a composite layer structure stacked on top of each other, but also a hybrid implanted doped layer structure, that is, the materials constituting the gate conductive layer 5G2 and the barrier layer are simultaneously deposited on the gate electrode. On the polar insulating layer 5G1, the gate conductive layer includes the material of the above-mentioned barrier layer. As shown in FIG. 10 , the gate insulating layer 5G1 surrounds the bottom and sidewalls of the gate conductive layer 5G2. Preferably, the gate stack 5G is planarized until the top of the insulating layer 4 is exposed by a process such as CMP, etch back, or the like.

As shown in FIG. 11, the device is planarized until the sacrificial layer 3A2 of the sacrificial contact stack is exposed.

As shown in FIG. 12 , a plurality of sacrificial contact stacks, ie, the sacrificial layer 3A2 and the liner layer 3A1 , are selectively etched away until the source and drain regions 2S/2D in the fin 2F are exposed. The same as or similar to the steps shown in FIG. 9 , the sacrificial layer 3B2 and the liner layer 3B1 are sequentially removed by dry etching or wet etching, leaving a second opening 4T2 used as a source-drain contact opening. In a preferred embodiment of the present invention, the sacrificial layer 3A2 of polysilicon and amorphous silicon is removed by wet etching with KOH and TMAH, and the liner layer 3A1 of silicon oxide is removed by etching with HF and BOE.

As shown in FIG. 13 , similar to that shown in FIG. 10 , the second opening 4T2 is filled with metal to form the contact line 6C. Preferably, a thin metal layer is deposited on the surface of the source and drain regions and annealed to form a metal silicide 6C1 to reduce the source-drain contact resistance. Then optionally, a barrier or adhesion layer (not shown) selected from Ti, Ta, TiN, TaN, and combinations thereof is formed by PECVD, MOCVD, MBE, ALD, evaporation, sputtering on the metal silicide 6C1, using Blocking the diffusion of the upper metal (eg, Al, etc.) into the source and drain regions affects the device performance and at the same time enhances the adhesion with the metal silicide 6C1. Next, a metal, metal alloy or metal nitride is formed in the remaining portion of the opening 4T2 to form a source-drain contact 6C2, wherein the metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, etc. and combinations thereof. Preferably, CMP planarization of the contact 6C2 is performed until the top of the insulating layer 4 is exposed. As shown on the left side of FIG. 13 , the metal is not only filled over the source and drain regions but also formed on the substrate 1 to form a contact line 6C.

The resulting FinFET device, as shown in FIG. 13 , includes a plurality of fins 2F extending along the first direction on the substrate 1 , and a plurality of gates extending along the second direction on the substrate 1 and spanning the plurality of fins 2F The electrode stack 5G and the plurality of contact lines 6C, in the plurality of fins 2F, the source and drain regions 2S and 2D distributed on both sides of the plurality of gate stacks 5G, there are one or more adjacent gate stacks 5G between the source and drain regions 2S and 2D. A contact line 6C is formed, and the contact line 6C forms a source-drain contact on the source-drain region. Other specific structures and materials and corresponding forming processes have been listed in the above description with reference to the accompanying drawings, and will not be repeated here.

According to the semiconductor device and its manufacturing method of the present invention, a double patterning process is used to form spaced sacrificial gate lines and sacrificial source-drain contact lines across the fin structure, and the two are sequentially removed by selective etching to fill the final gate The electrode and the final source-drain contact improve the reliability of the source-drain contact.

Although the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structure without departing from the scope of the invention. In addition, many modifications, as may be adapted to a particular situation or material, may be made from the disclosed teachings without departing from the scope of the invention. Therefore, the present invention is not intended to be limited to the particular embodiments disclosed as the best mode for carrying out the present invention, and the disclosed device structures and methods of making the same are to include all embodiments that fall within the scope of the present invention .

Claims (11)

1. A semiconductor device manufacturing method, comprising:

forming a plurality of fins extending in a first direction on a substrate;

forming a plurality of sacrificial gate stacks and a plurality of sacrificial contact stacks extending in a second direction on the substrate, spanning the plurality of fins, each sacrificial gate stack and each sacrificial contact stack having equal widths in the first direction;

forming source and drain regions in the plurality of fins and on two sides of the plurality of sacrificial gate stacks;

forming an insulating layer between the plurality of sacrificial gate stacks and the plurality of sacrificial contact stacks;

selectively etching to remove the sacrificial gate stacks, leaving a first opening in the insulating layer, and filling the gate stacks in the first opening;

and selectively etching to remove the sacrificial contact stacks, leaving a second opening in the insulating layer, filling the second opening with a plurality of contact lines, and leaving no additional device side wall between the gate stacks and the contact lines.

2. The semiconductor device manufacturing method of claim 1, wherein the step of forming a plurality of sacrificial gate stacks and a plurality of sacrificial contact stacks further comprises:

forming a sacrificial stack on the substrate, wherein the sacrificial stack comprises a liner layer, a sacrificial layer and a cover layer, and spans and covers the fins;

forming a plurality of gate masks extending in a second direction on the sacrificial stack;

etching the sacrificial stack until the sacrificial layer is exposed, and leaving a plurality of cover layer lines extending along the second direction;

forming one or more contact masks between the plurality of cap layer lines;

the sacrificial stack is etched until the plurality of fins are exposed, leaving a plurality of sacrificial gate stacks comprised of a liner layer, a sacrificial layer, and a cap layer that are conformal to the plurality of gate masks, and a plurality of sacrificial contact stacks comprised of a liner layer and a sacrificial layer that are conformal to the contact masks.

3. The manufacturing method of a semiconductor device according to claim 2, wherein the liner layer comprises silicon oxide, the sacrificial layer comprises amorphous silicon, polysilicon, amorphous germanium, amorphous carbon, diamond-like amorphous carbon (DLC), and combinations thereof, and the cap layer comprises silicon nitride, silicon oxynitride, and combinations thereof.

4. The manufacturing method of a semiconductor device according to claim 1, wherein the plurality of sacrificial gate stacks and the plurality of sacrificial contact stacks have the same pitch, and start positions and/or lengths in the second direction are the same.

5. The manufacturing method of a semiconductor device according to claim 1, wherein the ion implantation forms lightly doped source-drain regions and/or heavily doped source-drain regions.

6. A method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer is formed by a conformal deposition process.

7. The manufacturing method of a semiconductor device according to claim 2, wherein the step of leaving the first opening in the insulating layer further comprises: and selectively etching the cover layer, the sacrificial layer and the liner layer of the sacrificial gate stacks in sequence until the fins are exposed, wherein the sacrificial contact stacks are protected from etching by the insulating layer.

8. The manufacturing method of a semiconductor device according to claim 1, wherein each of the plurality of gate stacks comprises a gate insulating layer of a high-k material and a gate conductive layer of a metal material.

9. A method for manufacturing a semiconductor device according to claim 2, wherein the step of leaving the second opening in the insulating layer further comprises: and planarizing the insulating layer by CMP until the sacrificial layers of the sacrificial contact stacks are exposed, and selectively etching the sacrificial layers and the liner layers of the sacrificial contact stacks in sequence until the fins are exposed.

10. The semiconductor device manufacturing method according to claim 1, wherein the filling of the plurality of contact lines in the second opening further comprises: forming metal silicide on the source drain region; forming a barrier layer on the metal silicide; and forming source and drain contacts on the barrier layer.

11. The manufacturing method of a semiconductor device according to claim 7 or 9, wherein the etching process for etching away the cap layer, the sacrificial layer, and the pad layer is selective dry etching or wet etching.

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