CN105789110B - Mems switch high boosting multiple charge pump circuit and its manufacturing method - Google Patents

Abstract

The present invention is a high boost multiple charge pump circuit for MEMS switch. Its structure is that the layout of the second Trench structure and the layout of the third Trench structure respectively surround the layout of the first Trench structure. The SOI wafer is top layer silicon from top to bottom. Silicon oxide layer, high-resistance carrier; Trench structure is performed on the top silicon of SOI wafer to realize electrical isolation of each MOS tube substrate. The MOS tube and the third capacitor are interconnected to form a charge pump sub-circuit unit. The circuit unit and the output stage are cascaded to form the entire charge pump circuit. The advantages of the invention: the circuits all adopt CMOS technology, which has the advantages of high integration, low power consumption, easy to obtain high boost multiples and the like.

Description

High boost multiple charge pump circuit for MEMS switch and its manufacturing method

technical field

The present invention relates to a high boost multiple charge pump circuit for MEMS switches and a manufacturing method thereof, belonging to the technical field of semiconductor integrated circuits.

Background technique

RF_MEMS switches have become the key components to improve the performance of RF systems due to their advantages of high linearity, high bandwidth, high isolation, and low power consumption. Its drive also has the characteristics of high voltage and low current, especially in the case of high reliability contact, the driving voltage is required to reach 30~90V, and the current is below the nanoamp level. However, the power supply voltage of increasingly miniaturized RF systems, especially hand-held micro systems, is only within a few volts, which cannot directly provide a high enough driving voltage to make MEMS switches work reliably. Therefore, a booster circuit chip with a high boost multiple is required to convert the power supply voltage to a higher voltage output, and at the same time, the power consumption of the chip is required to be as low as possible and easy to integrate with other circuits. In view of the small drive current of MEMS switches, CMOS charge pump circuits are undoubtedly the best choice. However, the boost multiple of common CMOS charge pump circuits is only a few times, and there are few reports of charge pump circuits with high boost multiples of more than ten times. Relatively speaking, a charge pump with a low boost multiple is relatively easy to implement. With the increase of the boost multiple, the number of charge pump stages is required to increase, and the parasitic effect is intensified. Finally, the continuous improvement of the boost multiple cannot be achieved by increasing the number of charge pump stages. , it will decrease it. At this time, it is necessary to improve the circuit to reduce the influence of parasitic effects, so as to realize the continuous improvement of the boost multiple. On the other hand, with the increase of the boost ratio, the high voltage breakdown in the circuit will also become a problem. These are the problems faced by the design of the high boost ratio charge pump circuit. The present invention greatly reduces the parasitic coupling effect of the circuit by adopting the SOI material of the high-resistance carrier, making full use of the Trench structure, and optimizing the layout as a whole. Several stages of charge pump sub-circuits are cascaded. Under the excitation of a differential square wave signal of several megahertz and a load of several hundreds of megaohms, the charge pump circuit can increase the power supply voltage by more than ten times, which can basically meet the requirements of electrostatically driven MEMS switches. needs. By configuring the differential square wave excitation circuit and the output control circuit, the formed high-voltage drive circuit can be suitable for devices that require large voltage and low current drive, especially for MEMS switches, as well as phase shifters, filters, digital attenuators, etc. based on MEMS switches. Device module driver control.

SUMMARY OF THE INVENTION

The present invention proposes a high boost multiple charge pump circuit for MEMS switch and a manufacturing method thereof. The purpose of the invention is to solve the problem that the high boost multiple of the driving circuit formed by the charge pump circuit is low, which is difficult to apply to electrostatic drive MEMS devices or other Problems such as the need for high-voltage micro-current drive devices.

The technical solution of the present invention: a high boost multiple charge pump circuit for MEMS switches, the structure of which includes an SOI wafer 1, a top layer silicon 2, a Trench structure 3, a high resistance carrier 4, a silicon dioxide layer 5, and a first Trench structure. Layout 6, layout 7 of the second Trench structure, layout 8 of the third Trench structure, MOS transistor 9, MOS transistor capacitor; wherein, the layout 7 of the second Trench structure and the layout 8 of the third Trench structure respectively surround the first Trench structure Layout 6; SOI wafer 1 from top to bottom is top silicon 2, silicon dioxide layer 5, high resistance carrier 4 Trench structure 3 is carried out on the top silicon 2 of SOI wafer 1 to realize the electrical properties of each MOS tube 9 substrate For isolation, the MOS tube 9 and the MOS tube capacitor are interconnected to form a charge pump sub-circuit unit, and several stages of charge pump sub-circuit units and output stages are cascaded to form the entire charge pump circuit.

Its manufacturing method includes the following steps:

1) The production of SOI wafer 1, the carrier 4 of SOI wafer 1 selects a high-resistance silicon wafer or an insulating dielectric substrate (such as glass); above the carrier 4 is a silicon dioxide dielectric layer 5; above the silicon dioxide dielectric layer 5 It is the top layer silicon 2, and the manufacturing process is the SOI wafer manufacturing method adopted by the industry;

2) Formation of the Trench structure, the Trench structure is fabricated on the top layer silicon 2 of the SOI wafer 1 by a common manufacturing method in the industry. Specifically, the pattern transfer is realized by techniques such as photolithography, and the layout of the first Trench structure of the transistor 6 shape and the second The shape of the layout 7 of the Trench structure and the layout of the third Trench structure 8 are transferred to the top layer silicon 2 of the SOI wafer 1, and the layout of the first Trench structure 6, the layout 7 of the second Trench structure, and the first Trench structure are completely etched by etching technology. The top layer silicon 2 in the shape of layout 8 of the three-trench structure forms a trench in the shape of layout 6 of the first trench structure, layout 7 of the second trench structure, and layout 8 of the third trench structure, and then fills the trenches Enter the insulating medium, and perform a planarization process to form a Trench structure 3. The depth of the cross-section of the Trench structure 3 is to silicon dioxide 5. The shape of the plane pattern of the Trench structure 3 is the layout of the first Trench structure 6 and the second Trench structure. Layout 7 , the shape of the layout 8 of the third Trench structure; wherein the planar shape of the MOS tube Trench structure in the Trench structure 3 is the shape of the layout 6 of the first Trench structure, and the MOS tube Trench structure is essentially a closed dielectric ring surrounding the MOS tube; the closed dielectric ring; The dielectric ring and the silicon dioxide dielectric 5 work together, so that each MOS tube substrate is surrounded by an insulating medium to achieve complete electrical isolation of the transistor substrate, and the voltage of each transistor substrate is biased at any value below the breakdown voltage of the surrounding insulating medium ;

3) The CMOS circuit is realized, and the circuit is completed in and above the top layer silicon 2 of the SOI wafer 1 using a common manufacturing method in the industry.

The present invention has the following advantages:

1) The circuit adopts CMOS technology, which has the advantages of high integration, low power consumption and simple preparation process;

2) The adoption of the SOI wafer and the Trench structure around each MOS tube makes the circuit structure simple and reliable. Compared with the well isolation technology, the parasitic effect is greatly reduced, and the withstand voltage of the MOS tube substrate is higher;

3) The high-resistance carrier reduces the parasitic effect of the charge pump, improves the efficiency, and reduces the loss of microwave radio frequency signals, which is beneficial to the monolithic integration of MEMS radio frequency devices;

4) The voltage at both ends of each capacitor in the circuit always works at a low voltage, and there is no risk of breakdown. At the same time, a capacitor with a larger capacitance value per unit area can be used, and the chip area is significantly reduced.

Description of drawings

Figure 1 is a schematic diagram of a CMOS process on an SOI wafer.

Figure 2 is the topology of the charge pump subunit.

Figure 3 is a schematic diagram of the charge pump.

Figure 4 is an overall layout of the cascade of charge pump subcircuits.

1 is the SOI wafer, 2 is the top layer silicon, 3 is the Trench structure, 4 is the high resistance carrier, 5 is the silicon dioxide layer, 6 is the layout of the first Trench structure, 7 is the layout of the second Trench structure, 8 is the layout of the third Trench structure, and 9 is the MOS tube.

Detailed ways

With reference to the accompanying drawings, a high boost multiple charge pump circuit for MEMS switches is characterized by including SOI wafer 1, top layer silicon 2, Trench structure 3, high resistance carrier 4, silicon dioxide layer 5, and layout 6 of the first Trench structure , the layout 7 of the second Trench structure, the layout 8 of the third Trench structure, the MOS transistor 9, the MOS transistor capacitor; wherein, the layout 7 of the second Trench structure and the layout 8 of the third Trench structure respectively surround the layout of the first Trench structure 6; SOI wafer 1 from top to bottom is top silicon 2, silicon dioxide layer 5, high resistance carrier 4 to perform Trench structure 3 on top silicon 2 of SOI wafer 1 to realize electrical isolation of each MOS tube 9 substrate, The MOS tube 9 and the MOS tube capacitor are interconnected to form a charge pump sub-circuit unit, and several stages of charge pump sub-circuit units and output stages are cascaded to form the entire charge pump circuit.

The layout 6 of the first Trench structure surrounds each MOS transistor 9 .

The layout 7 of the second Trench structure encloses the A part of the charge pump circuit, the layout 8 of the third Trench structure encloses the B part of the charge pump circuit, and the A and B parts adopt a top-bottom symmetrical structure. details as follows:

In parts A and B, the layout 6 of the first Trench structure of the MOS transistor in the charge pump sub-circuit unit CP ₁ is formed by four closed patterns 6_1, 6_2, 6_3 and 6_4 arranged in two rows and two columns. The tube Mp ₁ and the first NMOS tube Mn ₁ are placed in the two closed figures of the first row 6_1 and 6_2 respectively, and the order of the front and back is not divided. The first capacitor C ₁ is placed above the closed figures 6_1 and 6_2, and the second MOS tube Mp _2. The second NMOS transistor Mn ₂ is placed in the two closed patterns of the second row 6_3 and 6_4 respectively, and the sequence is not divided. The second capacitor C ₂ is placed under the closed patterns 6_3 and 6_4. All the charge pump subcircuits CP ₁ ~ The internal layouts of CP _n are all laid out in this way, and all the charge pump subcircuit layouts are placed side by side in a compact order. A capacitor C ₁ ˜ C _{1_n} , the first PMOS transistors Mp ₁ ˜ Mp _{1_n} , and the first MOS transistors Mn ₁ ˜ Mn _{1_n} are all included in the layout 7 of the second trench structure, so that the second capacitors C ₂ ˜ C _{2_n} , the first MOS transistors Mn 1 ˜ Mn 1_n are all included in the layout 7 of the second trench structure The two PMOS transistors Mp ₂ to Mp _{2_n} and the second MOS transistors Mn ₂ to Mn _{2_n} are all included in the layout 8 of the third Trench structure. The layout 7 of the second Trench structure and the layout 8 of the third Trench structure are symmetrical up and down, as shown in the figure 4 shown.

The MOS tube 9 and the MOS tube capacitor are interconnected to form a charge pump sub-circuit, and several stages of charge pump sub-circuits and output stages are cascaded to form the entire charge pump circuit.

As shown in Figure 2, the PMOS transistors and NMOS transistors in the topological structure of the charge pump sub-circuit unit are common CMOS transistors, and the capacitors are low breakdown voltage capacitors with higher capacitance values per unit area.

In the topology of the charge pump sub-circuit unit, the source of the first PMOS transistor Mp ₁ is connected to the input ₁ terminal, the drain of the first PMOS transistor Mp ₁ is connected to the drain of the second NMOS transistor Mn ₂ , and the first PMOS transistor Mp ₁ The gate of the Mp2 is connected to the input ₂ terminal, the substrate bias is connected to the output ₁ terminal; the source of the second PMOS transistor Mp ₂ is connected to the input ₂ terminal, and the drain of the second PMOS transistor Mp ₂ is connected to the first NMOS transistor Mn The drain of ₁ is connected to the drain of 1, the gate of the second PMOS transistor Mp ₂ is connected to the input ₁ terminal, the substrate bias is connected to the output ₂ terminal; the source of the first NMOS transistor Mn ₁ is connected to the output ₁ terminal, and the first NMOS transistor is connected to the output 1 terminal. The drain of the tube Mn ₁ is connected to the drain of the _second PMOS tube Mp ₂ , the gate of the first NMOS tube Mn ₁ is connected to the output ₂ terminal, and the substrate bias electrode is connected to the input ₁ terminal ; The source is connected to the output ₂ terminal, the drain of the second NMOS transistor Mn ₂ is connected to the drain of the first PMOS transistor Mp ₁ , the gate of the second NMOS transistor Mn ₂ is connected to the output ₁ terminal, and the substrate bias is connected to The input ₂ end is connected; one end of the first capacitor C ₁ is connected to the input ₁ end, the other end is connected to the output ₁ end, one end of the second capacitor C ₂ is connected to the input ₂ end, and the other end is connected to the output ₂ end.

As shown in Figure 3, a total of 25 charge pump sub-circuit units are cascaded in charge pump sub-units. The input ₁ and input ₂ terminals of each sub-circuit unit are respectively connected to the output ₁ and output ₂ terminals of the previous stage. The output ₁ and output ₂ terminals of the circuit unit are respectively connected to the input ₁ and input ₂ terminals of the subsequent stage, and the output terminals output ₁ and output ₂ of the charge pump sub-circuit unit of the last stage are respectively connected with the drain of the PMOS transistor Mp ₃ , Mp ₄ is connected to the drain, the source of the PMOS tube Mp ₃ is connected to the output terminal, the gate is connected to the drain of Mp ₄ , the substrate bias is connected to the output terminal, the source of the PMOS tube Mp ₄ is connected to the output terminal, The gate is connected to the drain of Mp ₃ , and the substrate bias is connected to the output .

When the circuit is working, a pair of differential square wave signals are input from the outside to the two input ports input ₁ and input ₂ of the charge pump respectively;

When the voltage of the input ₁ port is high and the voltage of the input ₂ port is low, the PMOS transistor Mp ₁ and the NMOS transistor Mn ₂ are turned on, and the PMOS transistor Mp ₂ and the NMOS transistor Mn ₁ are turned off, so that the input ₁ port charges the capacitor C ₂ ;

Similarly, when the voltage of the input ₁ port is low and the voltage of the input ₂ port is high, the input ₂ port can charge the capacitor C ₁ ;

After several stages of charge pump sub-units are cascaded, the capacitor of the previous stage can be alternately charged to the capacitor of the subsequent stage, and the charge pump is boosted step by step;

Since the output of the charge pump is a differential voltage, the output structure shown in Figure 3 is used at the output end of the charge pump to convert the differential voltage into a single-ended output voltage, which improves the stability of the charge pump output and the ability to carry a load.

The characteristic of the charge pump structure is that the voltage between each capacitor plate does not exceed the power supply voltage in any period, so that no matter how much the charge pump voltage of each stage rises, the voltage between the capacitor plates can be easily controlled at its maximum breakdown. voltage below. An additional benefit of the lower capacitor-to-electrode voltage is that a low-breakdown-voltage capacitor with a larger capacitance per unit area can be selected, saving a larger area.

A manufacturing method of a high boost multiple charge pump circuit for a MEMS switch, comprising the following steps:

1) The production of SOI wafer 1, the carrier 4 of SOI wafer 1 selects a high-resistance silicon wafer or an insulating dielectric substrate (eg glass); above the carrier 4 is a silicon dioxide dielectric layer 5 or other insulating medium; silicon dioxide Above the dielectric layer 5 is the top layer silicon 2, and the manufacturing process is the SOI wafer manufacturing method adopted in the industry;

2) Formation of the Trench structure, the Trench structure is fabricated on the top layer silicon 2 of the SOI wafer 1 by a common manufacturing method in the industry. Specifically, the pattern transfer is realized by techniques such as photolithography, and the layout of the first Trench structure of the transistor 6 shape and the second The shape of the layout 7 of the Trench structure and the layout of the third Trench structure 8 are transferred to the top layer silicon 2 of the SOI wafer 1, and the layout of the first Trench structure 6, the layout 7 of the second Trench structure, and the first Trench structure are completely etched by etching technology. The top layer silicon 2 in the shape of layout 8 of the three-trench structure forms a trench in the shape of layout 6 of the first trench structure, layout 7 of the second trench structure, and layout 8 of the third trench structure, and then fills the trenches Enter the insulating medium, and perform a planarization process to form a Trench structure 3. The depth of the cross-section of the Trench structure 3 is to silicon dioxide 5. The shape of the plane pattern of the Trench structure 3 is the layout of the first Trench structure 6 and the second Trench structure. Layout 7 , the shape of the layout 8 of the third Trench structure; wherein the planar shape of the MOS tube Trench structure in the Trench structure 3 is the shape of the layout 6 of the first Trench structure, and the MOS tube Trench structure is essentially a closed dielectric ring surrounding the MOS tube; the closed dielectric ring; The dielectric ring and the silicon dioxide dielectric 5 work together, so that each MOS tube substrate is surrounded by an insulating medium to achieve complete electrical isolation of the transistor substrate, and the voltage of each transistor substrate is biased at any value below the breakdown voltage of the surrounding insulating medium ;

3) The CMOS circuit is realized, and the circuit is completed in and above the top layer silicon 2 of the SOI wafer 1 using a common manufacturing method in the industry.

Example 1

High boost multiple charge pump circuit for MEMS switch: its structure includes: SOI wafer 1, top silicon 2, Trench structure 3, high resistance carrier 4, silicon dioxide layer 5, layout of the first Trench structure 6, second Trench Layout 7 of the structure, layout 8 of the third Trench structure, MOS tube 9, MOS tube capacitor; among them, SOI wafer 1 is divided into top layer silicon 2, silicon dioxide layer 5, high resistance carrier 4 from top to bottom, in SOI The Trench structure 3 is performed on the top silicon 2 of the wafer 1 to realize the electrical isolation of the substrate of each MOS tube 9. The MOS tube 9 and the MOS tube capacitor are interconnected to form a charge pump sub-circuit, and several stages of charge pump sub-circuits and output stages are cascaded to form the entire charge pump circuit.

The overall layout of the charge pump circuit adopts an up-down symmetrical structure, the layout 6 of the first Trench structure surrounds each MOS transistor 9, the layout 7 of the second Trench structure, and the layout 8 of the third Trench structure respectively surround the A of the charge pump circuit. and part B to reduce the coupling between AB.

The thickness of the high-resistance carrier 4 of the SOI wafer 1 is 400-600 microns, and the resistivity is 5000-6000 ohm·cm.

The thickness of the silicon dioxide layer 5 is 1-3 microns.

The thickness of the top layer silicon 2 is 2-4 microns.

The CMOS transistors are fabricated in the top layer silicon 2 , and the Trench structure 3 is also completed in the top layer silicon 2 .

1) The production of SOI wafer 1. The carrier 4 of SOI wafer 1 selects a high-resistance silicon wafer or an insulating dielectric substrate (eg glass); above the carrier 4 is a silicon dioxide dielectric layer 5; above the silicon dioxide dielectric layer 5 It is the top layer silicon 2, and the manufacturing process is the SOI wafer manufacturing method adopted by the industry;

2) Formation of the Trench structure. The Trench structure is fabricated on the top layer silicon 2 of the SOI wafer 1 by using the industry's common manufacturing method. Specifically, the pattern transfer is realized by techniques such as photolithography, and the layout 6 of the transistor Trench structure is shaped and the shape of the large Trench structure. The shapes of the layouts 7 and 8 are transferred to the top silicon 2 of the SOI wafer 1, and the top silicon 2 of the shapes of the layouts 6, 7 and 8 is completely etched by the etching technology to form the grooves in the shape of the layouts 6, 7 and 8. , and then fill the insulating medium into the trench, and perform a planarization process to form a dielectric ring Trench structure 3 with a certain width and depth in cross-section and a plane pattern in the shape of layouts 6, 7, and 8; the MOS transistor Trench structure in Trench structure 3 The essence is a closed dielectric ring surrounding the MOS tube in the shape of the layout 6; the closed dielectric ring and the silicon dioxide dielectric 5 work together to make each MOS tube substrate surrounded by an insulating medium to achieve complete electrical isolation of the transistor substrate. The substrate voltage can be biased at any value below the breakdown voltage of the surrounding insulating medium;

3) The CMOS circuit is realized, and the circuit is completed in and above the top layer silicon 2 of the SOI wafer 1 using a common manufacturing method in the industry.

The overall circuit design uses software to extract parasitic parameters and post-simulation. The results show that the circuit boost multiple can reach more than ten times under a certain load.

Claims (4)

1. mems switch charge pump circuit, it is characterized in that including SOI wafer, the domain of the first Trench structure, second The domain of Trench structure, the domain of the 3rd Trench structure, metal-oxide-semiconductor, metal-oxide-semiconductor capacitor；Wherein, the version of the 2nd Trench structure Scheme, the domain of the 3rd Trench structure surrounds the domain of the first Trench structure respectively；SOI wafer is top layer silicon from top to bottom, Silicon dioxide layer, dielectric substrate；Trench structure is carried out in the top layer silicon of SOI wafer, realizes each metal-oxide-semiconductor substrate electricity Isolation is learned, metal-oxide-semiconductor and the interconnection of metal-oxide-semiconductor capacitor constitute substructure circuit unit, several grades of substructure circuit units and output Grade cascade constitutes entire charge pump circuit；

The domain of the 2nd Trench structure surrounds the part A of charge pump circuit, and the domain of the 3rd Trench structure surrounds The part B of charge pump circuit, and A and part B use structure symmetrical above and below, it is specific as follows:

In A and part B, substructure circuit unitCP ₁In the first Trench structure of metal-oxide-semiconductor domain by 6_1,6_2,6_ 3, two modes arranged arrange to be formed tetra- closed figures of 6_4 in two rows, the first PMOS tubeMp ₁, the first NMOS tubeMn ₁It is respectively put into In two closed figures of the first row 6_1,6_2, succession is placed on above 6_1,6_2 closed figure regardless of, first capacitor, the Two PMOS tubeMp ₂, the second NMOS tubeMn ₂It is respectively put into two closed figures of second row 6_3,6_4, succession is regardless of second Capacitor is placed below 6_3,6_4 closed figure, all substructure circuitsCP ₁~CP _nThe whole according to said method cloth of inside domain Innings, it is successively compact placed side by side between all substructure circuit layouts, after completing above-mentioned laying out pattern, re-form second The domain of the domain of Trench structure and the 3rd Trench structure makes first capacitor, the first PMOS tubeMp ₁, the first NMOS tubeMn ₁ It is integrally incorporated in the domain of the 2nd Trench structure, makes the second capacitor, the second PMOS tubeMp ₂, the second NMOS tubeMn ₂All packets It is contained in the domain of the 3rd Trench structure, it is right above and below the domain of the 2nd Trench structure and the domain of the 3rd Trench structure Claim；All substructure circuitsCP ₁~CP _nInside domain be all according to said method laid out.

2. mems switch charge pump circuit according to claim 1, it is characterized in that the first Trench structure Domain surrounds each metal-oxide-semiconductor.

3. mems switch charge pump circuit according to claim 1, it is characterized in that the substructure circuit unit First PMOS tube in topological structureMp ₁Source electrode withinput ₁End is connected, the first PMOS tubeMp ₁Drain electrode and the second NMOS tubeMn ₂ Drain electrode be connected, the first PMOS tubeMp ₁Grid withinput ₂End is connected, the first PMOS tubeMp ₁Substrate bias pole withoutput ₁End is connected；Second PMOS tubeMp ₂Source electrode withinput ₂End is connected, the second PMOS tubeMp ₂Drain electrode and the first NMOS PipeMn ₁Drain electrode be connected, the second PMOS tubeMp ₂Grid withinput ₁End is connected, the second PMOS tubeMp ₂Substrate bias pole withoutput ₂End is connected；First NMOS tubeMn ₁Source electrode withoutput ₁End is connected, the first NMOS tubeMn ₁Drain electrode and the 2nd PMOS PipeMp ₂Drain electrode be connected, the first NMOS tubeMn ₁Grid withoutput ₂End is connected, the first NMOS tubeMn ₁Substrate bias pole withinput ₁End is connected；Second NMOS tubeMn ₂Source electrode withoutput ₂End is connected, the second NMOS tubeMn ₂Drain electrode and the first PMOS PipeMp ₁Drain electrode be connected, the second NMOS tubeMn ₂Grid withoutput ₁End is connected, the second NMOS tubeMn ₂Substrate bias pole withinput ₂End is connected；First capacitor (C ₁) one end withinput ₁End be connected, the other end withoutput ₁End is connected, the second capacitor (C ₂) One end withinput ₂End be connected, the other end withoutput ₂End is connected.

4. mems switch charge pump circuit according to claim 1, it is characterized in that several grades of substructure circuits Unit has 25 substructure circuit unit cascades, each sub-circuit unitinput ₁、input ₂End respectively with previous stageoutput ₁、output ₂End is connected, each sub-circuit unitoutput ₁、output ₂End respectively with rear stageinput ₁、input ₂End is connected, the output end of afterbody substructure circuit unitoutput ₁、output ₂Respectively with PMOS tubeMp ₃'s Drain electrode,Mp ₄Drain electrode be connected, PMOS tubeMp ₃Source electrode withoutputEnd is connected, PMOS tubeMp ₃Grid withMp ₄Drain electrode phase Even, PMOS tubeMp ₃Substrate bias pole withoutputEnd is connected, PMOS tubeMp ₄Source electrode withoutputEnd is connected, PMOS tubeMp ₄ Grid withMp ₃Drain electrode be connected, PMOS tubeMp ₄Substrate bias pole withoutputEnd is connected.