CN105789180A - Semiconductor element, manufacturing method and stack structure thereof - Google Patents

Abstract

The present invention discloses a semiconductor element, a manufacturing method and a stacking structure thereof, wherein the semiconductor element includes a substrate, a redistribution wiring layer, a plurality of through-silicon vias, a plated seed crystal layer, an anti-oxidation layer and a buffer layer. The substrate has a first surface and a second surface opposite to each other and a plurality of openings. The redistribution wiring layer is disposed on the first surface, and the through-silicon vias are respectively disposed in the openings. The plated seed crystal layer is disposed between the hole wall of each opening and the corresponding through-silicon via. In addition, the anti-oxidation layer is disposed between the plated seed crystal layer and the corresponding through-silicon via. The buffer layer covers the first surface and exposes the redistribution wiring layer. In addition, a manufacturing method and a stacking structure of a semiconductor element are also mentioned.

Description

Semiconductor element, manufacturing method and stacked structure thereof

technical field

The present invention relates to a semiconductor element, and in particular to a semiconductor element with TSVs, a manufacturing method and a stacking structure thereof.

Background technique

With the rapid development of integrated circuit and semiconductor industry technology, the integration density of the manufacturing process of various electronic components continues to increase. The increase in integration density comes from the reduction of the minimum feature size (minimum feature size), so that more components can be integrated in limited chip area. Although the lithography process has been significantly developed in the fabrication of two-dimensional integrated circuits, there are physical limits to the density of component circuits that can be achieved on two-dimensional integrated circuits. As the number of components increases, the number of interconnections between components also increases significantly. When the length and number of interconnection wires increase, the RCdelay and power consumption of the circuit will increase significantly. Therefore, electronic components need new structures and technologies such as three-dimensional integrated circuits (3DIC) to improve the aforementioned problems. In the current semiconductor industry, the technology of three-dimensional integrated circuits refers to stacking chips vertically and connecting their signals with Through-Silicon Vias (TSVs) technology, which can effectively shorten the wire distance between chips, Reduce component size and increase operating speed.

Three-dimensional integrated circuits use through-silicon vias to connect high-density vertical stacks between integrated circuits, so that the distance between two chips is only tens of microns. Furthermore, with the development of solder ball packaging technology in a finer direction, the smaller solder ball pitch means that the surface area of each solder ball connection will be further reduced. Therefore, compared with the case of using larger solder balls and looser spacing, the challenges brought by the product reliability test of the 3D integrated circuit are becoming more and more severe. The aforementioned situation also makes the cost of the three-dimensional integrated circuit manufacturing technology remain high, especially in the electroplating manufacturing process of through-silicon vias, which accounts for a very large part of the manufacturing cost.

Contents of the invention

An object of the present invention is to provide a semiconductor device with TSVs for electrically connecting signals in semiconductor electronic devices.

Another object of the present invention is to provide a method for manufacturing a semiconductor device, which uses a single-step TSV electroplating method to simultaneously form a redistribution wiring layer, a TSV, and a micron bump.

Another object of the present invention is to provide a semiconductor element stack structure, which has a plurality of semiconductor elements vertically stacked on a substrate and electrically connected to each other through a plurality of connectors.

To achieve the above object, an embodiment of the present invention provides a semiconductor device including a substrate, a redistribution layer, a plurality of TSVs, an electroplating seed layer, an anti-oxidation layer and a buffer layer. The substrate has a first surface and a second surface opposite to each other, wherein the openings are respectively connected to the first surface and the second surface. In addition, the redistribution wiring layer is configured on the first surface. Furthermore, the TSV is disposed in the opening and has a first end and a second end opposite to each other, wherein the first end of each TSV is connected to the redistribution wiring layer, and the second end protrudes on the second surface. The electroplating seed layer is disposed between the wall of each opening and the corresponding TSV. In addition, the anti-oxidation layer is disposed between the electroplating seed layer and the corresponding TSVs, and covers the second ends of the corresponding TSVs. In addition, the buffer layer covers the first surface and exposes the redistribution circuit layer, wherein the redistribution circuit layer has a third surface, and the buffer layer has a fourth surface, and the third surface and the fourth surface are flush with each other.

An embodiment of the present invention provides a method for manufacturing a semiconductor device, including providing a substrate, wherein the substrate has a first surface and a plurality of openings. Next, an electroplating seed layer is formed on the first surface and on the wall of the hole. In addition, an anti-oxidation layer is formed on the electroplating seed layer, and a plurality of TSVs are formed in the corresponding openings, wherein the TSVs have a first end located on the first surface and opposite to the first end. a second end of . Next, a redistribution circuit layer is formed on the first surface, wherein the first end of the TSV is connected to the redistribution circuit layer. Furthermore, the backside of the substrate is thinned relative to the first surface, the thinned substrate has an opposite first surface and a second surface, and the second end of each TSV protrudes from the second surface. A dielectric layer is formed on the second surface and on the second end of each TSV.

An embodiment of the present invention provides a stacked structure of semiconductor elements, wherein the stacked structure includes a substrate, a plurality of semiconductor elements, and a plurality of connectors. The semiconductor elements are vertically stacked on the substrate, wherein each semiconductor element includes a plurality of TSVs and at least one RDL. In addition, TSVs are provided in each of the semiconductor elements, and at least one redistribution wiring layer is disposed on a first surface of one of the semiconductor elements, and the at least one redistribution wiring layer is connected to the first surface through the first surface. The TSV connections of one of the semiconductor devices. A plurality of connectors are disposed in the TSVs and between one of the semiconductor elements and the substrate, wherein the TSVs and the RDL of each semiconductor element are electrically connected to each other through the connectors.

Based on the above, the semiconductor device of the present invention includes an upper layer of metal lines, a lower layer of micron bumps, and a middle TSV. In the manufacturing method of the semiconductor element of the present invention, the redistribution circuit layer, the TSV layer and the micron bump of the semiconductor element can be formed simultaneously in a single electroplating manufacturing process. In addition, compared with the yellow light lithography manufacturing process of the traditional semiconductor element, the manufacturing method of the semiconductor element of the present invention only needs one photomask procedure, and the anti-oxidation layer of the conductive micron bump has been completed during the process of electroplating through-silicon crystal through-holes. . Therefore, the manufacturing method of the present invention can greatly reduce the manufacturing process cost of photomask and electroplating. Furthermore, in the substrate thinning manufacturing process of the present invention, etching technology can be used to reveal the bottom of the through-silicon crystal through hole, and use it as a conductive bump to directly bond with the chip or substrate, which can effectively reduce the thickness of the conductive bump. size and gap, and make the semiconductor element of the present invention applicable to miniaturized circuit design.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;

2A to 2M are schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

3A is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;

FIG. 3B is a schematic cross-sectional view of the stacked structure of the semiconductor device in FIG. 3A .

Symbol Description

100: Semiconductor components

110, 210: Substrate

112: First Surface

114: second surface

116: opening

116a: hole wall

120: Redistribute the wiring layer

130: TSV

132: First End

134: second end

140: electroplating seed layer

150: anti-oxidation layer

152: Adhesive layer

160: buffer layer

121: Third Surface

161: Fourth Surface

170: Underlayment

180: dielectric layer

190: Patterned photoresist layer

194: carrier board

196: release film

200: Semiconductor element stack structure

230, 232: connectors

240: insulating layer

IA: current

detailed description

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. Referring to FIG. 1 , the semiconductor device 100 includes a substrate 110 , a redistribution wiring layer 120 , a plurality of TSVs 130 , an electroplating seed layer 140 , an anti-oxidation layer 150 and a buffer layer 160 . In this embodiment, the substrate 110 has a first surface 112 and a second surface 114 opposite to each other and a plurality of openings 116 , wherein the openings 116 connect the first surface 112 and the second surface 114 respectively. In addition, a redistribution layer (Redistribution layer, RDL) 120 is disposed on the first surface 112 . A plurality of TSVs 130 are disposed in the corresponding openings 116 and respectively have opposite first ends 132 and second ends 134 . In this embodiment, the first end 132 of the TSV 130 is connected to the redistribution wiring layer 120 , and the second end 134 of the TSV 130 protrudes from the second surface 114 of the substrate 110 . Furthermore, the electroplating seed layer 140 is disposed between the hole wall 116a of each opening 116 and the corresponding TSV 130. In this embodiment, the electroplating seed layer 140 may include a titanium-copper composite layer, and titanium The copper composite layer further includes a titanium (Ti) layer and a copper (Cu) layer, which are sequentially disposed on the hole wall 116 a of the hole 116 and the first surface 112 . However, the present invention is not limited thereto, and the electroplating seed layer 140 in this embodiment may also be composed of other suitable metal materials.

On the other hand, the anti-oxidation layer 150 of this embodiment is disposed between the electroplating seed layer 140 and the corresponding TSV 130 . In addition, the anti-oxidation layer 150 covers the corresponding TSV 130 and includes the protruding second end 134 . In this embodiment, the anti-oxidation layer 150 includes a gold (Au) layer, but the invention is not limited thereto. In another unillustrated embodiment of the present invention, the anti-oxidation layer 150 may also include other anti-oxidation metal material layers such as a composite metal layer of nickel/palladium (Pd)/gold or tin (Sn) or other available The metal layer that is bonded to the conductive bump. In addition, in this embodiment, a metal layer such as a nickel layer can be disposed between the anti-oxidation layer 150 and the electroplating seed layer 140 to serve as the adhesion layer 152 between the anti-oxidation layer 150 and the electroplating seed layer. On the other hand, the buffer layer 160 is disposed on the substrate 110 , covers the first surface 112 of the substrate 110 , and exposes the redistribution circuit layer 120 . The redistribution wiring layer 120 has a third surface 121 , and the buffer layer 160 has a fourth surface 161 , and the third surface 121 and the fourth surface 161 are flush with each other.

Please refer to FIG. 1 again. In this embodiment, the first surface 112 of the substrate 110 and the opening 116a can be configured with a liner layer (liner) 170, and the liner layer (liner) 170 is configured between the substrate 110 and the plating seed. Between crystal layers 140. In addition, the dielectric layer 180 can be disposed on the second surface 114 of the substrate 110 to insulate and protect the substrate 110 . In addition, in another unillustrated embodiment of the present invention, at least one build-up structure can be further configured on the third surface 121 of the redistribution wiring layer 120 and the fourth surface 161 of the buffer layer 160 to increase the semiconductor device 100 wiring space. In the semiconductor device 100 of the present embodiment, the second end 134 of the TSV 130 protruding from the second surface 114 is covered by the anti-oxidation layer 150 , or can be completely covered. At the same time, the second end 134 of the TSV 130 can serve as a conductive bump electrically connected to other semiconductor elements or external devices. In the semiconductor device 100 of this embodiment, the second end 134 of the TSV 130 is directly used as a conductive bump. Therefore, compared with the conductive bumps of general semiconductor elements, the conductive bumps in this embodiment can have a relatively flat surface, the conductive bumps themselves can also have a smaller size, and the conductive bumps can be spaced between the conductive bumps. with smaller gaps. In addition, using the semiconductor device 100 of this embodiment in a stacked structure of a three-dimensional integrated circuit can further reduce the volume of the overall three-dimensional integrated circuit and achieve the design effect of miniaturization of electronic devices.

2A to 2M are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Please refer to FIG. 2A , in this embodiment, firstly, a substrate 110 having a plurality of openings 116 is provided. In this embodiment, the substrate 110 may be composed of, for example, silicon or a chip containing silicon, which may be used as an inner substrate of a stacked structure of semiconductor devices. In the illustration of FIG. 2B , in this embodiment, the liner layer 170 may be pre-formed on the first surface 112 of the substrate 110 and on the wall 116 a of the opening 116 . Next, an electroplating seed layer 140 is formed on the first surface 112 of the substrate 110 and the hole walls 116 a by, for example, sputtering. In this embodiment, the electroplating seed layer 140 includes a titanium-copper composite layer, and the titanium-copper composite layer may further include a titanium layer and a copper layer, and the titanium layer and the copper layer are sequentially sputtered on the first surface 112 and the hole wall 116a superior. In addition, referring to FIG. 2C , a patterned photoresist layer 190 is deposited on the first surface 112 of the substrate 110 . Next, a gold layer is electroplated on the electroplating seed layer 140 by means of electroless electroplating to serve as the anti-oxidation layer 150 . In this embodiment, an adhesive layer 152 such as a nickel layer can be further disposed between the electroplating seed layer 140 and the anti-oxidation layer 150 . Furthermore, please refer to the illustrations in FIG. 2D and FIG. 2E , in this embodiment, the conductive copper pillars through the TSVs 130 and the redistribution wiring layer 120 thereon are formed by electroplating. Then, the patterned photoresist layer 190 is removed from the first surface 112 .

On the other hand, please refer to FIG. 2F , after the patterned photoresist layer 190 is removed, the photoresist layer located on the first surface 112 and not covering the redistribution lines is removed by, for example, wet etching. Electroplating seed layer 140 underlying layer 120 . Next, as shown in FIG. 2G , a buffering layer 160 covering the first surface 112 and the redistribution wiring layer 120 is formed on the substrate 110 . In this embodiment, the material of the buffer layer 160 may be, for example, a polybenzoxazole (PBO) insulation protection material. In addition, referring to FIG. 2H , in this embodiment, a part of the buffer layer 160 and a part of the redistribution wiring layer 120 may be further removed by means of, for example, mechanical polishing, and the redistribution wiring layer 120 and the redistribution wiring layer 120 may be further removed. The buffer layer 160 respectively forms the third surface 121 and the fourth surface 161 , and the third surface 121 and the fourth surface 161 are flush with each other. Furthermore, please refer to FIG. 2I , the semiconductor element 100 is attached to the carrier 194 through the third surface 121 and the fourth surface 161 at the same time, so as to perform the subsequent thinning process on the back side of the substrate 110 . In this embodiment, the release film 196 can be further arranged between the third surface 121 and the fourth surface 161 and the carrier 194, so that the carrier 194 can be subsequently removed by the release film 196, and the semiconductor The third surface 121 of the element 100 is separated from the fourth surface 161 . In this embodiment, due to the configuration of the aforementioned release film 196 , there is no need to use a relatively complicated etching process, which simplifies the manufacturing process of the overall semiconductor device 100 and reduces the cost of the manufacturing process.

In this embodiment, please refer to FIG. 2J , in this embodiment, the substrate 110 can be thinned by grinding, chemical mechanical polarization (CMP) process and dry etching (dryetching) process. The back side of the substrate 110 relative to the first surface 112 can be thinned to form the second surface 114, and the second end 134 of the TSV 130 protrudes from the second surface 114 to form a plurality of protrusions on the second surface. Microbumps on surface 114 . In addition, as shown in FIG. 2K , a dielectric layer 180 may be formed on the formed micro-bump surface and the second surface 114 of the substrate to insulate and protect the second surface 114 of the substrate 110 . Next, as shown in FIG. 2L , in this embodiment, the liner layer 170 and the dielectric layer 180 of the formed micro-bump portion are removed by a chemical mechanical planarization process, and the electroplating is removed by wet etching. The seed layer 140 and the adhesive layer 152 are used to expose the second ends 134 of the TSVs 130 covered by the anti-oxidation layer 150 as a plurality of micron bumps. Finally, as shown in FIG. 2M , the carrier 194 is removed, that is, the manufacturing process of the overall semiconductor device 100 is completed. In the present embodiment, the redistribution circuit layer 120 , the TSV 130 and the micron bumps can be completed simultaneously by using the single-step electroplating and filling method of the TSV 130 . In other words, in this embodiment, the fabrication of the redistribution wiring layer 120 and the conductive copper pillars in the TSVs 130 can be completed simultaneously through a single electroplating fabrication process. In addition, through the thinning of the substrate 110 , the second ends 134 of the TSVs 130 can be exposed on the second surface 114 of the thinned substrate 110 to serve as micron bumps electrically connected to external devices. Therefore, compared with the conductive bumps of general semiconductor elements, the micron bumps formed by this manufacturing method have a relatively flat surface and a relatively small size, which helps to increase the flatness of the overall substrate 110 configuration and reduce the size. Bump-to-bump gap. Furthermore, the anti-oxidation layer 150 deposited in the opening 116 can protect the conductive copper pillars of the TSVs 130 . Therefore, the manufacturing method of this embodiment can effectively simplify the overall manufacturing process of the semiconductor device 100 and further reduce the manufacturing cost of the semiconductor device 100 .

FIG. 3A is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. In this embodiment, the same or similar elements as those in the previous embodiments will be denoted by the same reference numerals, and description and description will not be repeated here. Please refer to FIG. 3A. In this embodiment, the second ends 134 of the TSVs 130 of the semiconductor element 100 can respectively have connectors 232, so that a plurality of semiconductor elements 100 or between the semiconductor element 100 and the substrate or other external The devices are electrically connected to each other. In this embodiment, the connecting member 232 is, for example, entirely or partially composed of a solder layer or other metal suitable for bonding. In addition, FIG. 3B is a schematic cross-sectional view of the stacked structure of the semiconductor device in FIG. 3A . Please refer to FIG. 3B , the semiconductor device stack structure 200 includes a substrate 210 , a plurality of semiconductor devices 100 , at least one redistribution layer 120 and a plurality of connectors 230 , 232 . In this embodiment, a plurality of semiconductor elements 100 are vertically stacked on the substrate 210, and in another embodiment not shown, the semiconductor element stack structure 200 of the present invention can also be different semiconductor elements such as dynamic random Access memory (Dynamic Random Access Memory, DRAM), flash memory (flash memory) or logic (logic) elements are stacked with each other. In addition, as described in the foregoing embodiments, the semiconductor devices 100 may respectively have a plurality of TSVs 130 penetrating therein. Moreover, in this embodiment, at least one redistribution wiring layer 120 and buffer layer 160 are disposed on the first surface 112 of the uppermost semiconductor device 100 of the semiconductor device stack structure 200 . In addition, the redistribution wiring layer 120 and the buffer layer 160 respectively have a third surface 121 and a fourth surface 161 , and the third surface 121 and the fourth surface 161 are flush with each other. On the other hand, a plurality of connecting elements 230 and 232 are respectively disposed in the TSV 130 and between one of the semiconductor devices 100 and the substrate 210 . In the stacked structure 200 of the present embodiment, the connecting elements 230 , 232 can be, for example, a plurality of solder balls and solder layers for electrically connecting the TSV 130 and the redistribution wiring layer 120 of the semiconductor device 100 .

Please refer to FIG. 3B again. In this embodiment, a multi-layer insulating layer 240 can be further arranged between the plurality of semiconductor elements 100, and the semiconductor element 100 at the bottom of the semiconductor element stack structure 200 and the Between the substrates 210. In this embodiment, the insulating layer 240 may be composed of a material such as benzocyclobutene (BCB). On the other hand, the substrate 210 of this embodiment may be made of materials such as a silicon substrate or a glass substrate, and the substrate 210 may have a plurality of conductive bumps 220 such as copper bumps disposed thereon. In detail, in this embodiment, a plurality of vertically stacked semiconductor elements 100 are electrically connected to each other through connection members 230, 232 such as solder balls, solder or other solder materials, so that the current IA passes through a plurality of TSVs 130 and conductive bumps 220 are transferred between a plurality of vertically stacked semiconductor devices 100 . Therefore, through the semiconductor element stack structure 200 of this embodiment, the wire distance between the semiconductor elements 100 can be effectively shortened, and the volume of the overall semiconductor device can be further reduced, thereby increasing the operating speed of the overall device.

To sum up, the present invention discloses a semiconductor device, its manufacturing method and a stacked structure, wherein the semiconductor device stacked structure in this case includes an upper redistribution wiring layer, a lower micron bump, and a through-silicon via in the middle. In addition, the present invention utilizes the single-step electroplating and filling method of through-silicon crystal vias, which can simultaneously complete the redistribution circuit layer, the through-silicon crystal vias, and the manufacture of micron bumps, which can greatly reduce the number and cost of electroplating manufacturing processes, and the present invention In the process of electroplating the through-silicon vias, the anti-oxidation layer of the conductive copper pillars of the through-silicon vias has been completed. In addition, the manufacturing process of the semiconductor element of the present invention can also reduce the original two or more yellow photolithography manufacturing processes into one. In the present invention, due to the integration of the above-mentioned manufacturing process and the improvement of the process, and the size of the conductive bumps of the semiconductor element and their distribution gaps are greatly reduced, the structure and manufacturing method of the semiconductor element of the present invention are in line with the current miniaturization of electronic elements and products. development trend, and can further reduce the manufacturing cost of semiconductor elements and their three-dimensional stacked structures.

Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the appended claims.

Claims (20)

1. a semiconductor element, including:

Substrate, has relative first surface, second surface and multiple perforate, and wherein those perforates connect this first surface and this second surface respectively；

Reroute road floor, be configured on this first surface；

Multiple straight-through silicon wafers are bored a hole, and are configured in those perforates, and are respectively provided with the first relative end and the second end, and this first end of those straight-through silicon wafers of each of which perforation is connected to this rewiring road floor, and this second distal process is on this second surface；

Plating seed layer, is configured between the hole wall of those perforates each and those corresponding straight-through silicon wafers perforation；

Antioxidation coating, is configured between this plating seed layer with those corresponding straight-through silicon wafers perforation, and this antioxidation coating of part covers this second end of corresponding those straight-through silicon wafers perforation；And

Cushion, is configured on this substrate, and covers this first surface, and exposes this rewiring road floor.

2. semiconductor element as claimed in claim 1, wherein this plating seed layer includes titanium copper composite bed, and wherein this titanium copper composite bed includes titanium layer and layers of copper.

3. semiconductor element as claimed in claim 1, wherein this antioxidation coating includes layer gold.

4. semiconductor element as claimed in claim 1, also includes adhesion layer, is configured between this plating seed layer and this antioxidation coating, and wherein this adhesion layer is nickel dam.

5. semiconductor element as claimed in claim 1, also includes dielectric layer, is configured on this second surface and on this second end of respectively those straight-through silicon wafers perforation.

6. semiconductor element as claimed in claim 1, wherein this rewiring road floor has the 3rd surface, and this cushion has the 4th surface, and the 3rd surface is mutually flush with the 4th surface.

7. a manufacture method for semiconductor element, including:

Thering is provided a substrate, wherein this substrate has first surface and multiple perforate；

Form a plating seed layer on this first surface and the hole wall of those perforates；

Form an antioxidation coating on this plating seed layer；

Forming multiple straight-through silicon wafer and bore a hole in those corresponding perforates, wherein the perforation of those straight-through silicon wafers is respectively provided with the first end being positioned on first surface and the second end relative to this first end；

Forming a rewiring road floor on this first surface, this first end of those straight-through silicon wafers of each of which perforation is connected to this rewiring road floor；

This substrate of thinning is relative to the dorsal part of this first surface, and this substrate after thinning has the second surface relative to this first surface, and this second distal process of those straight-through silicon wafers each perforation is for this second surface；And

Form a dielectric layer on this second end that this second surface and those straight-through silicon wafers each are bored a hole.

8. the manufacture method of semiconductor element as claimed in claim 7, before being additionally included in this antioxidation coating of formation, forms a patterning photoresist oxidant layer on this first surface, and after forming this rewiring road floor, removes this patterning photoresist oxidant layer.

9. the manufacture method of semiconductor element as claimed in claim 8, is additionally included in after removing this patterning photoresist oxidant layer, etches this plating seed layer.

10. the manufacture method of semiconductor element as claimed in claim 9, after being additionally included in this plating seed layer of etching, forms a cushion on the first surface.

11. the manufacture method of semiconductor element as claimed in claim 10, after being additionally included in this cushion of formation, this cushion of part is removed in the way of mechanical lapping, to expose this rewiring road floor of a part, wherein this rewiring road floor has the 3rd surface, and this cushion has the 4th surface, the 3rd surface and the 4th surface are mutually flush.

12. the manufacture method of semiconductor element as claimed in claim 11, also include being attached on a support plate via the 3rd surface and the 4th surface by this substrate, and in forming this dielectric layer after this second surface, remove this support plate.

13. the manufacture method of semiconductor element as claimed in claim 7, wherein this plating seed layer includes titanium copper composite bed, and wherein this titanium copper composite bed includes titanium layer and layers of copper.

14. the manufacture method of semiconductor element as claimed in claim 7, wherein this antioxidation coating includes layer gold.

15. the manufacture method of semiconductor element as claimed in claim 7, also including forming an adhesion layer between this plating seed layer and this antioxidation coating, wherein this adhesion layer is a nickel dam.

16. a semiconductor element stacked structure, including:

Substrate；

Multiple semiconductor elements, are stacked on this substrate mutual vertically, and those semiconductor elements of each of which include the perforation of multiple straight-through silicon wafer, are arranged in those semiconductor elements each；

At least one rewiring road floor, is configured at a first surface of one of them those semiconductor element, and this at least one rewiring road floor is bored a hole via those straight-through silicon wafers of these those semiconductor elements of first surface and one of them and is connected；And

Multiple connectors, being embedded in the perforation of those straight-through silicon wafers and between one of them those semiconductor elements and this substrate, those straight-through silicon wafers perforation of those semiconductor elements of each of which and this at least one rewiring road floor are electrically connected to each other by those connectors.

17. semiconductor element stacked structure as claimed in claim 16, wherein those connectors include multiple soldered ball and soldering-tin layer.

18. semiconductor element stacked structure as claimed in claim 16, also include multilayer dielectric layer and be respectively arranged between those semiconductor elements.

19. semiconductor element stacked structure as claimed in claim 16, also include insulating barrier, be configured between those semiconductor elements and this substrate.

20. semiconductor element stacked structure as claimed in claim 16, wherein this substrate is a silicon substrate, and this substrate has multiple conductive projection and is configured thereon that.