CN105930242B - A kind of multi-core processor random verification method and device for supporting accurate memory access detection - Google Patents

Abstract

The present invention proposes a random verification method and device for a multi-core processor that supports accurate memory access detection. The method includes step 1, combining user constraints in the multi-core processor to be verified with an instruction library to generate a memory access conflict The parallel program is used as a verification vector; run the verification vector, record the execution result of the verification vector and the time information of the memory access operation; step 2, perform a storage consistency design correctness check according to the execution result and the time information of the memory access operation , if the storage consistency design of the multi-core processor to be verified conforms to the storage consistency model, then perform step 3; step 3, send the verification vector and the time information of the memory access operation to the instruction level simulator, The instruction level simulator executes the verification vector according to the chronological sequence of the memory access operation, and compares the result with the execution result after the simulation of the multi-core processor, and if the comparison results are consistent, continues to perform random verification of the multi-core processor.

Description

A random verification method and device for a multi-core processor supporting accurate memory access detection

technical field

The invention relates to the field of VLSI design verification, in particular to a multi-core processor random verification method and device thereof supporting accurate memory access detection.

Background technique

The semantics of the memory model of a single-core processor are intuitive, that is, a read operation to any memory unit will return the value written to the unit by the most recent write operation, and the write operation uniquely determines the result of subsequent read operations on the same unit . When random verification of a single-core processor is performed by a simulation method, the reference model is usually used to give the reference execution result of the verification vector, and the result of the reference model is compared with the actual RTL (register-transfer level) execution result to judge whether it is right or wrong , for a serial program in a single-core processor environment, the result of each run is uniquely deterministic, which makes the random verification of the processor go smoothly.

Different from single-core processors, on-chip multi-core processors use a shared memory system, and multiple processor cores can read and write the same storage unit. The correctness is determined by the storage consistency model. As the interface between hardware and software, operating system and application program of the multi-core processor on chip, the storage consistency model specifies the sequence requirements between memory access events in the shared storage system in detail, ensuring the system Correctness, the academic community has conducted a lot of research on the complexity of storage consistency verification. It is believed that the correctness of parallel program execution results in the case of multi-core shared storage depends on the access order of conflicting operations in the program, and the correctness of parallel program execution is given. The standard of: the directed graph of the parallel program results represented by the global order is acyclic (reference: Hu Weiwu, "Shared Storage System Structure", Higher Education Press, 2001). At the same time, academic circles have also proved that memory consistency verification without any restrictions is an NP-hard problem, which makes the correctness verification of on-chip multi-core processors a highly difficult problem.

Later, some scholars proposed that in multi-core processors, each memory access operation has a period of execution time: this time starts when the operation enters the processor and ends when the operation is submitted. It is observed that only operations with overlapping execution times have sequence uncertainty. Due to the size limitations of the operation window, memory access queue, write cache and other components when implementing a multi-core processor, and a memory access operation The number of operations whose execution time overlaps is also limited. Therefore, when verifying storage consistency, the derivation of the sequence relationship and the detection of loops in the execution graph can be limited to a certain range of operations, which makes the storage consistency of multi-core processors Consistency verification can be reduced to linear time complexity (reference: Yunji Chen, etc. "Fast Complete Memory Consistency Verification", in Proceedings of the 15th IEEE International Symposium on High-Performance Computer Architecture, 2009.), this conclusion makes in practice It is possible to verify the memory consistency of multi-core processors. According to this method, it can be detected whether the directed graph of the parallel program memory access sequence of multi-core processors within a limited range is acyclic, and based on this, it can be judged whether the memory consistency design of multi-core processors is correct.

However, the above method cannot solve the problem of correctness comparison in the simulation verification of multi-core processors. Even if it is proved that the directed graph of the parallel program memory access sequence of multi-core processors is acyclic, it can only show that the memory consistency design of multi-core processors conforms to The storage consistency model specification, and the multi-core processor memory access sequence and results in the case of conforming to the storage consistency model specification can still be non-unique. When the memory access instruction is randomly combined with more complex instructions in the parallel program, this access The non-uniqueness of the stored results will cause the state space explosion of the execution results, making it difficult to judge the correctness of the instruction execution results when the multi-core processor performs random simulation verification.

Random verification technology is an important supporting technology in the process of processor simulation verification. Figure 1 describes the common framework of processor random verification methods, combining user constraints 102 and instruction library 101, and generating verification vectors through random generation engine 103, generating The verification vectors are respectively sent to the instruction level simulator 104 and the design simulation environment 105 to be verified for execution, and the execution results are compared. When the comparison results are inconsistent, errors in the processor design can be detected. For multi-core processors, When the memory access instruction is randomly combined with other complex instructions in a parallel program, the non-uniqueness of the memory access result will cause the state space explosion of the execution result, making it difficult to complete the result comparison during random verification, making it difficult to directly use the traditional random Verification techniques for multi-core processor simulation verification, this problem has not been resolved. At present, the commonly used mode for verifying multi-core processors is: firstly use the traditional random verification technology to verify each processor core in the multi-core processor, then perform simulation verification for the on-chip network connecting each processor core, and finally store the multi-core processor system. Consistency verification, this multi-core processor verification mode often causes design error escape, especially when the multi-core processor storage consistency design is correct, and errors will occur when multi-core interleaved memory access and other instructions are mixed and executed, multi-core processor verification often Errors cannot be accurately detected and localized.

To sum up, in the current multi-core processor simulation verification, the non-uniqueness of memory access results causes the result state space explosion problem, which makes it difficult to complete the result comparison link during random verification, and cannot accurately detect and locate errors. In the actual operation of multi-core processor chips When , due to the scheduling of the operating system and the randomness of shared memory access conflicts, the execution results of parallel programs cannot be uniquely determined.

Contents of the invention

Aiming at the deficiencies of the prior art, the present invention proposes a multi-core processor random verification method and device thereof supporting accurate memory access detection.

The present invention proposes a multi-core processor random verification method supporting accurate memory access detection, including:

Step 1. Combine the user constraints and the instruction library in the multi-core processor to be verified, and generate a parallel program with memory access conflicts as a verification vector through the parallel program generator; The verification vector, recording the execution result of the verification vector and the time information of the memory access operation;

Step 2, according to the execution result and the time information of the memory access operation, check the correctness of the storage consistency design, if the storage consistency design of the multi-core processor to be verified conforms to the storage consistency model, then perform the step 3. Otherwise, if a design error is found, stop this random verification and perform error debugging;

Step 3, sending the time information of the verification vector and the memory access operation into the instruction level simulator, the instruction level simulator executes the verification vector according to the time sequence of the memory access operation, and compares the result with the multi-core processor The execution results after the simulation are compared. If the comparison results are consistent, the random verification is passed, and the multi-core processor random verification is continued, otherwise, error debugging is performed.

Also include before the step 1:

Step 11, setting a global clock for recording the time information of the memory access operation;

Step 12, setting the parallel program generator to support generating the verification vector through a pseudo-random method;

Step 13, record the entry time and submission time of each memory access operation and write them into the file;

Step 14, check the correctness of the storage consistency design through the file;

Step 15, improve the instruction level simulator, so that the instruction level simulator can execute the verification vector according to the time sequence of the memory access operation, and compare the execution result with the execution result after the multi-core processor simulation.

The step 14 includes detecting whether the directed graph of the verification vector memory access sequence of the multi-core processor to be verified within a limited range is acyclic, and judging whether the storage consistency design of the multi-core processor to be verified is correct.

The global clock includes setting a 64-bit counter, which increments by 1 every clock beat from time 0.

The step 13 includes monitoring the entry time and submission time of each memory access operation of each processor core of the multi-core processor to be verified through wires.

The present invention also proposes a multi-core processor random verification device that supports accurate memory access detection, including:

Obtain the verification vector module, which is used to combine the user constraints in the multi-core processor to be verified with the instruction library, and generate parallel programs with memory access conflicts as verification vectors through the parallel program generator; in the simulation of the multi-core processor to be verified Running the verification vector in the environment, recording the execution result of the verification vector and the time information of the memory access operation;

A storage consistency check module, configured to check the correctness of the storage consistency design according to the execution result and the time information of the memory access operation, if the storage consistency design of the multi-core processor to be verified meets the storage consistency model, enter the execution result comparison module, otherwise design errors are found, stop this random verification and perform error debugging;

The execution result comparison module is used to send the verification vector and the time information of the memory access operation into the instruction-level simulator, and the instruction-level simulator executes the verification vector according to the time sequence of the memory access operation, and outputs the result Compare with the execution result after the simulation of the multi-core processor, if the comparison result is consistent, then this random verification is passed, and continue to perform the random verification of the multi-core processor, otherwise, perform error debugging.

Before the module of obtaining the verification vector, it also includes:

Setting a global clock module for setting a global clock for recording the time information of the memory access operation;

Setting the parallel program generator module for setting the parallel program generator to support generating the verification vector through a pseudo-random method;

The entry time and submission time module is used to record the entry time and submission time of each memory access operation and write them into the file;

A check module, configured to check the correctness of the storage consistency design through the file;

The improved instruction level simulator module is used to improve the instruction level simulator, so that the instruction level simulator can execute the verification vector according to the time sequence of the memory access operation, and perform the execution result with the execution result after the multi-core processor simulation Compare.

The inspection module includes detecting whether the directed graph of the verification vector memory access sequence of the multi-core processor to be verified within a limited range is acyclic, and judging whether the storage consistency design of the multi-core processor to be verified is correct.

The global clock includes setting a 64-bit counter, which increments by 1 every clock beat from time 0.

The entry time and commit time module includes monitoring the entry time and commit time of each memory access operation of each processor core of the multi-core processor to be verified through wires.

As can be seen from the above scheme, the present invention has the advantages of:

The present invention proposes a multi-core processor random verification method and its device supporting accurate memory access detection. By setting a global clock and a post-run comparison mechanism in the random verification environment, it supports the comparison of accurate results in the random verification of the multi-core processor and solves the problem of The problem of accurate detection and localization of errors in stochastic verification of multi-core processors has long been plagued.

Description of drawings

Fig. 1 is a schematic structural diagram of a single-core processor random verification system in the prior art;

Fig. 2 is an example diagram of the improvement process of multi-core processor random verification environment in the present invention;

FIG. 3 is a schematic diagram of a random verification execution flow of a multi-core processor in the present invention.

Detailed ways

The purpose of the present invention is to solve the problem of accurate result comparison in the random verification of multi-core processors, and to support the accurate detection and positioning of errors in the random verification of multi-core processors. In order to solve the above technical problems, a multi-core processor supporting accurate memory access detection is proposed Random verification method and device thereof.

In order to achieve the above object, the present invention proposes a multi-core processor random verification method and its device supporting accurate memory access detection, including two parts: a multi-core processor random verification environment improvement method and a multi-core processor random verification execution method, through the following technical solutions accomplish:

The multi-core processor random verification environment improvement method includes the following steps:

1. Set the global clock in the top module of the random verification test platform;

2. Transform the random generation engine in the random verification environment of single-core processors into a parallel program generator, and support the use of pseudo-random methods to generate parallel programs with memory access conflicts;

3. Set the monitoring mechanism for the memory access operation of each processor core in the multi-core processor to be verified in the top module of the random verification test platform, record the entry time and submission time of each memory access operation and write it into the file;

4. Add a storage consistency design correctness detection mechanism in the result comparison of the random verification environment, and use the above-mentioned files that record the entry time and submission time of each memory access operation to check the correctness of the storage consistency design;

5. Improve the instruction-level simulator so that it can execute parallel programs according to the time sequence of the previously recorded memory access operations, and compare the results with the execution results of the multi-core processor to be verified after simulation.

The multi-core processor random verification execution method includes the following steps:

1. Combining user constraints and instruction libraries, through the parallel program generator, use the pseudo-random method to generate parallel programs with memory access conflicts as verification vectors;

2. Run the aforementioned parallel program with memory access conflict in the multi-core processor simulation environment to be verified, and record the execution result of the parallel program and the time information of the memory access operation;

3. According to the execution result of the aforementioned parallel program and the time information of the memory access operation, the correctness of the storage consistency design is checked. If the storage consistency design of the multi-core processor to be verified does not meet the storage consistency model required by the requirements specification, a design error is found, and this random verification execution error debugging is stopped; otherwise, continue to the next step;

4. Send the aforementioned parallel program with memory access conflict and the time information of the memory access operation to the instruction-level simulator, and the instruction-level simulator executes the parallel program according to the time sequence of the previously recorded memory access operation, and compares the result with the multi-core to be verified The execution results after the processor simulation are compared. If the comparison results are consistent, the simulation verification is passed, and the random verification of the multi-core processor is continued; if the comparison results are inconsistent, a design error is found and error debugging is performed.

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

A multi-core processor random verification method and device supporting precise memory access detection, the specific implementation process includes two parts: a multi-core processor random verification environment improvement process and a multi-core processor random verification execution process.

The improvement process of multi-core processor random verification environment is shown in Figure 2:

Step S201. Set the global clock in the top module of the random verification test platform. In the specific implementation, a 64-bit counter can be set in the top module of the random verification test platform, and the global clock can be obtained by incrementing by 1 every clock tick from time 0;

Step S202. Transform the random generation engine in the random verification environment of the single-core processor into a parallel program generator, and support pseudo-random method to generate parallel programs with memory access conflicts. The memory address accessed in the parallel program is a virtual address, and the access conflict refers to the access to the same physical memory address. It is necessary to map the same memory access virtual address to the same physical address in the actual operation of the program, so that it will generate The real conflict is that there is no operating system support in the random verification environment of the multi-core processor to be verified. In the specific implementation, the code segments of each process in the parallel program can be assigned to different physical addresses in the random verification environment, and the The data segments of all processes are allocated to the same physical address in order to generate real memory access conflicts;

Step S203. In the top-level module of the random verification test platform, a monitoring mechanism for each processor core memory access operation in the multi-core processor to be verified is set, and the entry time and submission time of each memory access operation are recorded and written into a file. In actual implementation, the top-level module of the random verification test platform can monitor the memory access information of each processor core module through wires, for example: to set the monitor for a certain processor core cache write operation in the top-level module, use assign dcw_valid=top .cpu_core1......dcache_0.dcw_valid, other memory access operation monitoring methods can be deduced by analogy;

Step S204. Add a storage consistency design correctness detection mechanism to the result comparison of the random verification environment, and use the above-mentioned file recording the entry time and submission time of each memory access operation to check the correctness of the storage consistency design. In the specific implementation, the directed graph of the parallel program memory access sequence of the multi-core processor to be verified in a limited range is detected by traditional methods, and whether the directed graph of the memory access sequence of the multi-core processor to be verified is acyclic, and based on this, it is judged whether the storage consistency design of the multi-core processor to be verified is correct;

Step S205. Improve the instruction level simulator so that it can execute the parallel program according to the time sequence of the previously recorded memory access operation, and compare the result with the execution result after the simulation of the multi-core processor to be verified.

Multi-core processor random verification execution process, as shown in Figure 3:

Step S301. Combining the user constraints with the instruction library, and using a pseudo-random method to generate parallel programs with memory access conflicts as verification vectors through the parallel program generator;

Step S302. Run the aforementioned parallel program with memory access conflict in the multi-core processor simulation environment to be verified, and record the execution result of the parallel program and the time information of the memory access operation;

Step S303. According to the execution result of the aforementioned parallel program and the time information of the memory access operation, check the correctness of the storage consistency design;

Step S304. Determine whether the storage consistency design of the multi-core processor to be verified conforms to the storage consistency model required by the requirements specification. If it does not meet the storage consistency model required by the requirements specification, a design error is found, and this random verification execution is stopped. Error debugging; otherwise, execute step S305;

Step S305. Sending the aforementioned parallel programs with memory access conflicts and time information of memory access operations to the instruction level simulator;

Step S306. The instruction level simulator executes the parallel program according to the time sequence of the previously recorded memory access operation, and compares the result with the execution result after the simulation of the multi-core processor to be verified;

Step S307. Judging whether the aforementioned comparison results are consistent, if the comparison results are consistent, then perform step S308; if the comparison results are inconsistent, then find a design error, and perform error debugging;

In step 308, the current simulation verification is passed, and the multi-core processor random verification is continued.

The present invention also proposes a multi-core processor random verification device that supports accurate memory access detection, including:

Obtain the verification vector module, which is used to combine the user constraints in the multi-core processor to be verified with the instruction library, and generate parallel programs with memory access conflicts as verification vectors through the parallel program generator; in the simulation of the multi-core processor to be verified Running the verification vector in the environment, recording the execution result of the verification vector and the time information of the memory access operation;

A storage consistency check module, configured to check the correctness of the storage consistency design according to the execution result and the time information of the memory access operation, if the storage consistency design of the multi-core processor to be verified meets the storage consistency model, enter the execution result comparison module, otherwise design errors are found, stop this random verification and perform error debugging;

The execution result comparison module is used to send the verification vector and the time information of the memory access operation into the instruction-level simulator, and the instruction-level simulator executes the verification vector according to the time sequence of the memory access operation, and outputs the result Compare with the execution result after the simulation of the multi-core processor, if the comparison result is consistent, then this random verification is passed, and continue to perform the random verification of the multi-core processor, otherwise, perform error debugging.

Before the module of obtaining the verification vector, it also includes:

Setting a global clock module for setting a global clock for recording the time information of the memory access operation;

Setting the parallel program generator module for setting the parallel program generator to support generating the verification vector through a pseudo-random method;

The entry time and submission time module is used to record the entry time and submission time of each memory access operation and write them into the file;

A check module, configured to check the correctness of the storage consistency design through the file;

The improved instruction level simulator module is used to improve the instruction level simulator, so that the instruction level simulator can execute the verification vector according to the time sequence of the memory access operation, and perform the execution result with the execution result after the multi-core processor simulation Compare.

The inspection module includes detecting whether the directed graph of the verification vector memory access sequence of the multi-core processor to be verified within a limited range is acyclic, and judging whether the storage consistency design of the multi-core processor to be verified is correct.

The global clock includes setting a 64-bit counter, which increments by 1 every clock beat from time 0.

The entry time and commit time module includes monitoring the entry time and commit time of each memory access operation of each processor core of the multi-core processor to be verified through wires.

Claims (10)

1. a kind of multi-core processor random verification method for supporting accurate memory access detection, which is characterized in that including：

Step 1, the user in multi-core processor to be verified is constrained and be combined with instruction database, by concurrent program generator, It generates there are the concurrent program of memory access conflict as verification vectors；In multi-core processor simulated environment to be verified described in operation Verification vectors record the implementing result of the verification vectors and the temporal information of accessing operation；

Step 2, according to the implementing result and the temporal information of the accessing operation, storage consistency design correctness inspection is carried out It looks into, if the storage consistency design of the multi-core processor to be verified meets memory consistency model, performs step 3, Otherwise it finds design mistake, stop this accidental validation and performs wrong debugging；

Step 3, the temporal information of the verification vectors and the accessing operation is sent into instruction-level simulator, described instruction grade mould Intend device and perform the verification vectors according to the time sequencing of accessing operation, and by result and holding after multi-core processor analog simulation Row result is compared, if comparison result is consistent, this accidental validation passes through, and continues to execute multi-core processor and tests at random Otherwise card carries out wrong debugging；

Generation to be specifically included there are the concurrent program of memory access conflict as verification vectors wherein in step 1：In accidental validation environment The middle code segment by process each in concurrent program is assigned to different physical address, and the data segment of all processes is all distributed To identical physical address, to generate memory access conflict.

2. the multi-core processor random verification method of accurate memory access detection is supported as described in claim 1, which is characterized in that institute It is further included before stating step 1：

Step 11, global clock is set, for recording the temporal information of the accessing operation；

Step 12, the concurrent program generator is set, supports to generate the verification vectors by pseudo-random method；

Step 13, the entry time of every accessing operation and submission time are recorded and is written in file；

Step 14, by the file, storage consistency design Correctness checking is carried out；

Step 15, instruction-level simulator is improved, described instruction grade simulator is enable to be performed according to the time sequencing of accessing operation The verification vectors, and implementing result and the implementing result after multi-core processor analog simulation are compared.

3. the multi-core processor random verification method of accurate memory access detection is supported as claimed in claim 2, which is characterized in that institute State step 14 include detection limited range in the multi-core processor to be verified the verification vectors memory access sequence it is oriented Whether figure is acyclic, and judges whether the multi-core processor storage consistency design to be verified is correct.

4. the multi-core processor random verification method of accurate memory access detection is supported as claimed in claim 2, which is characterized in that institute The counter that global clock includes setting one 64 is stated, each timeticks increase 1 certainly since 0 moment.

5. the multi-core processor random verification method of accurate memory access detection is supported as claimed in claim 2, which is characterized in that institute Step 13 is stated to include monitoring every memory access behaviour of each processor core of the multi-core processor to be verified by gage system The entry time and submission time of work.

6. a kind of multi-core processor accidental validation device for supporting accurate memory access detection, which is characterized in that including：

Verification vectors module is obtained, for user's constraint in multi-core processor to be verified to be combined with instruction database, is passed through Concurrent program generator is generated there are the concurrent program of memory access conflict as verification vectors；It is imitated in multi-core processor to be verified The verification vectors are run in true environment, record the implementing result of the verification vectors and the temporal information of accessing operation；

Consistency check module is stored, for the temporal information according to the implementing result and the accessing operation, is stored Consistency designs Correctness checking, if the storage consistency design of the multi-core processor to be verified meets storage consistency Model then into implementing result comparison module, otherwise finds design mistake, stops this accidental validation and performs wrong debugging；

Implementing result comparison module, for the temporal information of the verification vectors and the accessing operation to be sent into instruction level simulation Device, described instruction grade simulator perform the verification vectors, and result and multinuclear are handled according to the time sequencing of accessing operation Implementing result after device analog simulation is compared, if comparison result is consistent, this accidental validation passes through, and continues to execute more Otherwise core processor accidental validation carries out wrong debugging；

Generation in verification vectors module is wherein obtained to specifically include as verification vectors there are the concurrent program of memory access conflict：With The code segment of process each in concurrent program is assigned to different physical address in machine verification environment, and by the number of all processes Identical physical address is all assigned to according to section, to generate memory access conflict.

7. the multi-core processor accidental validation device of accurate memory access detection is supported as claimed in claim 6, which is characterized in that institute It states and is further included before obtaining verification vectors module：

Global clock module is set, for setting global clock, for recording the temporal information of the accessing operation；

The concurrent program generator block is set, and for setting the concurrent program generator, support passes through pseudo-random method Generate the verification vectors；

Entry time and submission time module, for recording the entry time of every accessing operation and submission time and being written to text In part；

It checks module, for passing through the file, carries out storage consistency design Correctness checking；

Instruction-level simulator module is improved, for improving instruction-level simulator, enables described instruction grade simulator according to memory access The time sequencing of operation performs the verification vectors, and by the implementing result after implementing result and multi-core processor analog simulation into Row compares.

8. the multi-core processor accidental validation device of accurate memory access detection is supported as claimed in claim 7, which is characterized in that institute It states and checks that the verification vectors memory access sequence that module includes the multi-core processor to be verified in detection limited range has It is whether acyclic to scheming, and judge whether the multi-core processor storage consistency design to be verified is correct.

9. the multi-core processor accidental validation device of accurate memory access detection is supported as claimed in claim 7, which is characterized in that institute The counter that global clock includes setting one 64 is stated, each timeticks increase 1 certainly since 0 moment.

10. the multi-core processor accidental validation device of accurate memory access detection is supported as claimed in claim 7, which is characterized in that The entry time includes monitoring each place of the multi-core processor to be verified by gage system with submission time module Manage the entry time and submission time of every accessing operation of device core.