CN105931965B - A kind of semiconductor device and its manufacturing method - Google Patents
A kind of semiconductor device and its manufacturing method Download PDFInfo
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- CN105931965B CN105931965B CN201610272425.7A CN201610272425A CN105931965B CN 105931965 B CN105931965 B CN 105931965B CN 201610272425 A CN201610272425 A CN 201610272425A CN 105931965 B CN105931965 B CN 105931965B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
- H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6731—Top-gate only TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
- H10D30/6745—Polycrystalline or microcrystalline silicon
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Abstract
The embodiment of the invention discloses a kind of semiconductor devices and its manufacturing method, which includes: to provide semiconductor substrate, and the channel region to be formed between active area, drain region and source region and drain region is corresponding on semiconductor base；Light shield layer is formed on the semiconductor base for being correspondingly formed covering source region, drain region and channel region；Insulating layer is formed on light shield layer；Amorphous silicon layer is formed on the insulating layer, and by amorphous silicon layer crystallization to be converted into polysilicon layer.The high heat of amor phous silicon layer is exported using the thermally conductive function of light shield layer in the embodiment of the present invention, compared with prior art, the smaller size crystal grain of polysilicon layer can effectively hinder the flowing of carrier in semiconductor devices, to achieve the effect that inhibit leakage current.It is not necessarily to LDD processing procedure in the present invention, simplifies the production procedure of semiconductor devices, extends the service life of semiconductor devices, also improve the reliability of semiconductor devices.
Description
Technical field
The present embodiments relate to semiconductor technology more particularly to a kind of semiconductor devices and its manufacturing methods.
Background technique
MOS device (metal (metal)-oxide (oxide)-semiconductor (semiconductor) field effect transistor)
It is voltage-controlled device, is chiefly used in switch application, with the fast advantage of switching speed.Influence MOS device service life it is main because
Element is leakage current, and the electrical property of MOS device is poor when leakage current is larger and service life is shorter.
MOS device includes P-channel MOS device (abbreviation PMOS) and N-channel MOS device (abbreviation NMOS), and PMOS leans on hole
Flowing transport electric current, compared with NMOS, have be not necessarily to lightly doped drain (LDD) processing procedure and cheap advantage.Theoretically
LDD processing procedure is needed in the manufacturing process of NMOS to achieve the effect that reduce hot carrier's effect and then inhibit leakage current, and PMOS
Manufacturing process in be also able to suppress leakage current without LDD processing procedure, wherein LDD processing procedure is in channels near drain electrode
One low-doped drain region is set so that the low-doped drain region is also subjected to portion voltage.
If however in actual production in the manufacturing process of PMOS cancel LDD processing procedure, the leakage current of PMOS is bigger than normal, influence
The service life of PMOS.In order to overcome the problem, PMOS product is still required to reach by increasing LDD processing procedure in existing manufacturing process
To the effect for reducing hot carrier's effect and then inhibition leakage current.Therefore, the manufacturing process of existing PMOS compares NMOS,
Lose the advantage for saving LDD processing procedure.
Summary of the invention
The embodiment of the present invention provides a kind of semiconductor devices and its manufacturing method, needs to pass through LDD to solve existing PMOS
Processing procedure inhibits the problem of leakage current.
In a first aspect, the embodiment of the invention provides a kind of manufacturing method of semiconductor devices, which includes:
There is provided semiconductor substrate, wherein corresponded on the semiconductor base active area, drain region and the source region and
Channel region between the drain region；
Light shield layer is formed on the semiconductor base of the correspondence source region, the drain region and the channel region；
Insulating layer is formed on the light shield layer；
It is formed on the insulating layer amorphous silicon layer, and by the amorphous silicon layer crystallization to be converted into polysilicon layer.
Second aspect, the embodiment of the invention also provides a kind of semiconductor devices, which uses such as first party
Manufacturing method described in face is manufactured.
Semiconductor devices provided in an embodiment of the present invention and its manufacturing method, by corresponding source region, drain region and channel region
Semiconductor base on form light shield layer, the high heat of amor phous silicon layer is exported using the thermally conductive function of light shield layer.With it is existing
There is technology to compare, a large amount of high heat of crystallization process are exported by light shield layer, therefore reduce the crystallite dimension of polysilicon layer, polycrystalline
The smaller size crystal grain of silicon layer can effectively hinder the flowing of carrier in semiconductor devices, to reach the effect for inhibiting leakage current
Fruit.It is not necessarily to LDD processing procedure in the embodiment of the present invention, simplifies the production procedure of semiconductor devices accordingly, extends semiconductor device
The service life of part also inhibits the leakage current of semiconductor devices, also improves the reliability of semiconductor devices.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing does one and simply introduces, it should be apparent that, drawings in the following description are some embodiments of the invention, for this
For the those of ordinary skill of field, without creative efforts, it can also be obtained according to these attached drawings others
Attached drawing.
Fig. 1 is the flow chart of the manufacturing method of semiconductor devices provided in an embodiment of the present invention；
Fig. 2A~Fig. 2 H is the schematic diagram of the manufacturing method of semiconductor devices provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, hereinafter with reference to attached in the embodiment of the present invention
Figure, clearly and completely describes technical solution of the present invention by embodiment, it is clear that described embodiment is the present invention one
Section Example, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
It is as shown in Figure 1 the flow chart of the manufacturing method of semiconductor devices provided by one embodiment of the present invention, this implementation
The technical solution of example, which is suitable for reaching by simplified process for fabrication of semiconductor device, inhibits the phenomenon that leakage current.The semiconductor devices
It is chosen as MOS device, preferably PMOS device.
The manufacturing method of semiconductor devices provided in this embodiment, specifically comprises the following steps:
Step 101, provide semiconductor substrate, wherein corresponded on semiconductor base active area, drain region and source region and
Channel region between drain region.
There is provided first in the present embodiment corresponded on a semiconductor base and the semiconductor base active area, drain region, with
And the channel region between source region and drain region.It will be understood by those skilled in the art that can be used as there are many materials of semiconductor base,
In the present invention without concrete restriction.
It will be understood by those skilled in the art that corresponding source region, drain region and channel region needs pass through on a semiconductor substrate
Subsequent technique could be formed, and be only used for restriction semiconductor base herein is used to form source region, drain region and ditch in the subsequent process
The basal region in road area does not indicate that source region, drain region and channel region in actual semiconductor devices.
Step 102 forms light shield layer on the semiconductor base of corresponding source region, drain region and channel region.
Light shield layer is formed on a semiconductor substrate in the present embodiment, specific light shield layer formed on a semiconductor substrate and
Source region, drain region and channel region on corresponding semiconductor base.Chemical vapor deposition process, physics can be used in the present embodiment
The manufacturing process such as gas-phase deposition or sputtering technology form light shield layer, it will be understood by those skilled in the art that forming light shield layer
Technique include but is not limited to above-mentioned specific example technique, the manufacturing process of light shield layer is not limited specifically in the present invention
System.The function of light shield layer is to block the light from backlight in the present embodiment, avoids the occurrence of the increasing of light direct projection channel region
The phenomenon that adding photo-generated carrier that leakage current is caused to increase.It will be understood by those skilled in the art that being suitable for semiconductor devices and rising
The film material of effect of shutting out the light each falls within protection scope of the present invention, does not have in the present invention to the material of light shield layer
Body limitation.
Step 103 forms insulating layer on light shield layer.
In the present embodiment insulation layer stackup be formed in light shield layer on the side of semiconductor base, in the present embodiment
In can form insulating layer using the manufacturing process such as chemical vapor deposition process, physical gas-phase deposition or sputtering technology.This
Field technical staff is appreciated that the technique to form insulating layer includes but is not limited to above-mentioned specific example technique, in the present invention
Concrete restriction is not carried out to the manufacturing process of insulating layer.
Insulating layer plays a part of to be dielectrically separated from the present embodiment, therefore is suitable for semiconductor devices and rises to be dielectrically separated from work
Film material each falls within protection scope of the present invention, does not carry out concrete restriction to the material of insulating layer in the present invention.
Amorphous silicon layer is formed on the insulating layer in step 104, and by amorphous silicon layer crystallization to be converted into polysilicon layer.
In the present embodiment polysilicon layer stacking be formed in insulating layer on the side of light shield layer.Specifically, at this
It needs first insulating using manufacturing process such as chemical vapor deposition process, physical gas-phase deposition or sputtering technologies in embodiment
Amorphous silicon layer is formed on layer, then so that amorphous silicon is converted to polysilicon by crystallization technology.It will be understood by those skilled in the art that
There are many ways to amorphous silicon layer is formed on the insulating layer, including but not limited to above-mentioned example, the furthermore side of amor phous silicon layer
Method also there are many, such as laser crystallization and solid-phase crystallization do not carry out concrete restriction to amorphous silicon crystallization method in the present invention.Example
Laser irradiation is carried out so that recrystallized amorphous silicon is converted into polycrystalline to amorphous silicon using laser crystallization technology as optional in the present embodiment
Silicon.It will be understood by those skilled in the art that the semiconductor devices for using above-mentioned manufacturing method to produce is low-temperature polysilicon film
Transistor (LTPS-TFT).
It will be understood by those skilled in the art that polysilicon layer can be used as semiconductor after polysilicon layer is formed on the insulating layer
The active area of device can form source region, drain region and the channel region of semiconductor devices by subsequent doped polycrystalline silicon technology, in this hair
Process flow after the polysilicon layer for forming semiconductor devices is not specifically described and is limited in bright.
It will be understood by those skilled in the art that there are many ways to amor phous silicon layer, but each crystallization method
Crystallization temperature can all generate high heat on the semiconductor device, and high heat leads to the crystalline substance of the polysilicon layer of existing semiconductor devices
Particle size becomes larger, after subsequent technique forms source region, drain region and channel region, the source region of semiconductor devices and the large scale in drain region
Crystal grain to reduce the inhibition of carrier, thus causes the leakage current of semiconductor devices bigger than normal.
In the present embodiment light shield layer be formed in semiconductor base on the side of polysilicon layer, it is therefore intended that block
The light of backlight enters channel region, and it is known that light shield layer can not only shut out the light, also there is thermally conductive, heat dissipation and buffering etc.
Function, therefore the thermally conductive function of light shield layer can effectively export the crystallization mistake that amorphous silicon layer crystallization is polysilicon layer in the present embodiment
The high heat generated in journey.
Specifically, when the high heat generated during amor phous silicon layer enters light shield layer by insulating layer, shading
The thermally conductive function of layer effectively exports the high heat in crystallization process, reduces the crystallite dimension of polysilicon layer, thus this implementation
The polysilicon grain size of semiconductor devices is smaller in example.The crystallite dimension of polysilicon layer is smaller, to the current-carrying of semiconductor devices
The inhibition of son is bigger, therefore the little crystallite size of the polysilicon layer of semiconductor devices can effectively hinder current-carrying in the present embodiment
The flowing of son, the source region for improving semiconductor devices and drain region can reach to the inhibition of carrier, and then without LDD support
The effect for inhibiting the leakage current of semiconductor devices, also extends the service life of semiconductor devices, and improve semiconductor accordingly
The reliability of device.
The manufacturing method of semiconductor devices provided in this embodiment passes through partly leading in corresponding source region, drain region and channel region
Light shield layer is formed in body substrate, is exported the high heat of amor phous silicon layer using the thermally conductive function of light shield layer.With the prior art
Compare, a large amount of high heat of crystallization process are exported by light shield layer, therefore reduce polysilicon layer crystallite dimension, polysilicon layer compared with
Small-size grains can effectively hinder the flowing of carrier in semiconductor devices, to achieve the effect that inhibit leakage current.The technology
It is not necessarily to LDD processing procedure in scheme, simplifies the production procedure of semiconductor devices accordingly, extend semiconductor devices uses the longevity
Life, also inhibits the leakage current of semiconductor devices, also improves the reliability of semiconductor devices.
Illustratively, based on the above technical solution, the optional semiconductor base includes: substrate；It is formed in substrate
First buffer layer on opposite light shield layer side, wherein light shield layer is formed in the first buffering of corresponding source region, drain region and channel region
On layer.For the manufacturing method of more detailed description above-mentioned semiconductor device, combines partly led shown in Fig. 2A~Fig. 2 H herein
The manufacturing method of semiconductor devices is described in detail in the separate structure schematic diagram of body device.It is as shown in Figure 2 A semiconductor-based
The schematic diagram at bottom.
Substrate 110 is chosen as Si substrate in the present embodiment, it will be understood by those skilled in the art that the lining of semiconductor devices
Bottom includes but is not limited to Si substrate, does not carry out concrete restriction to the material of substrate in the present invention.
First buffer layer 120, first buffer layer are formed on the side of the opposite light shield layer of substrate 110 in the present embodiment
120 have shockproof, buffering and an isolation performance, for example, the impurity that can completely cut off in substrate 110 enter semiconductor devices source region 111,
Drain region 112 or channel region 113, avoid foreign ion from having an impact the electrical property of semiconductor devices.
Optional first buffer layer 120 is silicon nitride material in the present embodiment, and silicon nitride material has thermal stability high, anti-
The excellent performances such as oxidability is strong, product size accuracy is high and is not easy to be corroded.Using the first buffering of silicon nitride material
Layer 120 can be formed by low-pressure chemical vapor deposition technology, alternatively, can pass through plasma enhanced chemical vapor deposition technology shape
At.It will be understood by those skilled in the art that the technique for forming first buffer layer includes but is not limited to both the above, and first buffers
The other materials that layer also can be selected other than silicon nitride is formed, in the present invention not to the manufacturing process of first buffer layer and material
Carry out concrete restriction.It will be understood by those skilled in the art that first buffer layer forms on substrate and extends to semiconductor devices
Active area periphery.
Illustratively, based on the above technical solution, the formation of light shield layer 130 in the semiconductor devices as shown in Figure 2 B
In the first buffer layer 120 of corresponding source region 111, drain region 112 and channel region 113.The optional light shield layer 130 be metal material or
Heat sink material.
In the present embodiment, light shield layer 130 be formed in first buffer layer 120 on the side of substrate 110, it is known that after
Insulating layer is also formed on light shield layer 130 in continuous technique, preferably in the subsequent process to the insulating layer of semiconductor devices and shading
Layer 130 performs etching simultaneously, simplifies production procedure.In other embodiments, directly pass through photoetching after also optional formation light shield layer
Or dry etching technology etching light shield layer, to form corresponding source region, drain region and the light shield layer of channel region, those skilled in the art can manage
Solution etches light shield layer to form the only etching technics of the light shield layer of corresponding covering source region, drain region and channel region and etching process and have
It is a variety of, in the present invention without concrete restriction.
Light shield layer 130 is preferably metal material or heat sink material in the present embodiment, and metal material usually has excellent
Heat-conductive characteristic, and the materials such as heat sink material such as boron nitride also have excellent heat-conductive characteristic.Those skilled in the art can be with
Understand, various metals material and heat sink material all have excellent heat-conductive characteristic, therefore in the present invention not to light shield layer
Material carries out concrete restriction.
Light shield layer 130, which can not only play, in the present embodiment stops the light of backlight to enter channel region by substrate 110
113, prevent channel region 113 from increasing photo-generated carrier, additionally it is possible to play to the high fever away from one side of substrate from light shield layer 130
Amount carries out thermally conductive effect, reduces the crystallite dimension of polysilicon layer.
Illustratively, based on the above technical solution, the formation of insulating layer 140 in the semiconductor devices as shown in Figure 2 C
On side of the light shield layer 130 away from first buffer layer 120.Optional insulating layer 140 is silica material.Silica has nanometer
Effect shows the properties such as brilliant reinforcement, thickening, thixotroping, insulation, delustring, resist sagging in the material, thus is widely applied
In the macromolecules industrial circle such as rubber, plastics, coating, adhesive, sealant.Preferred insulating layer 140 is oxygen in the present embodiment
Silicon nitride material, it will be understood by those skilled in the art that the material of insulating layer includes but is not limited to silica material, other are suitable for
Semiconductor devices and protection scope of the present invention is each fallen with the film material of insulating effect, in the present invention not to insulating layer
Material carry out concrete restriction.
In the present embodiment, preferably in the subsequent process using an etching technics to the insulating layer 140 of semiconductor devices
It is performed etching simultaneously with light shield layer 130, simplifies production procedure.In other embodiments, directly logical after also optional formation insulating layer
Photoetching or dry etching technology etching insulating layer are crossed to form corresponding source region, drain region and the insulating layer of channel region, those skilled in the art
It is appreciated that there are many etching technics and etching processes, in the present invention without concrete restriction.
Illustratively, based on the above technical solution, as shown in Figure 2 D in the semiconductor devices, perpendicular to partly leading
On the direction of body substrate, the thickness of the insulating layer 140 being formed on the light shield layer 130 of corresponding channel region 113, which is greater than, to be formed in pair
Answer the thickness of the insulating layer 140 on the light shield layer 130 in source region 111 and drain region 112.
After forming insulating layer 140 in the present embodiment, processing is performed etching to insulating layer 140, so that with 113 weight of channel region
The thickness in folded insulating film layer region is greater than the insulating film layer region Chong Die with source region 111 and drain region 112.Those skilled in the art
It is appreciated that the insulating layer of deposited formation perform etching handle so that the method in uneven thickness of insulating layer have it is more
Kind, in the present invention without concrete restriction.It is Chong Die with channel region 113 exhausted in settable insulating layer 140 in the present embodiment
Velum layer region is insulating film layer Chong Die with source region 111 and drain region 112 in the first insulating film layer region and insulating layer 140
Region is the second insulating film layer region, therefore the thickness in the first insulating film layer region is greater than the second insulating film layer in insulating layer 140
Region.
The thickness of insulating layer 140 forms gradient in the present embodiment and the thickness in the first insulating film layer region is greater than the second insulation
When film layer area, when there is high heat importing in the side away from light shield layer 130 of insulating layer 140, the second relatively thin insulating film layer
The heat in region, which can quickly introduce, makes light shield layer 130 radiate to the heat rapidly in light shield layer 130, avoid heat poly-
Collection, and it is slower than the heat dissipation of light shield layer 130 slightly
The corresponding light shield layer 130 of source region 111 and drain region 112.Therefore source region 111 is corresponded in semiconductor devices and the heat in drain region 112 is few
In the heat of corresponding channel region 113, so that the crystallite dimension of the polysilicon layer in corresponding source region 111 and drain region 112 is less than pair
Answer the crystallite dimension of the polysilicon layer of channel region 113, the crystalline substance of the relative small size of the polysilicon layer in source region 111 and drain region 112
Grain can significantly more efficient obstructions carrier to the flowing outside semiconductor devices, thus effectively inhibition semiconductor devices electric leakage
Stream, improves the service life of semiconductor devices.
Illustratively, based on the above technical solution, in order to realize the insulation of semiconductor devices as shown in Figure 2 D
The thickness step of layer 140, the optional thickness step as shown in Figure 2 E that insulating layer is formed using intermediate tone mask technique.
Photoresist 150 is formed on insulating layer 140 in the present embodiment, then is covered using the halftoning with different light transmittances
Film realizes different degrees of exposure development, so that photoresist 150 forms thickness step, then by etching technics realizes source region
111 and the corresponding insulating layer 140 in drain region 112 thickness step to meet the needs of polysilicon layer various grain sizes, Jin Erda
To the effect for inhibiting leakage current.
In the present embodiment in order to realize the insulating film layer region Chong Die with channel region 113 thickness be greater than and source region 111
The insulating film layer region being overlapped with drain region 112, light transmittance of the optional intermediate tone mask at source region 111 and drain region 112 is big herein
In light transmittance of the intermediate tone mask at channel region 113, preferably light transmittance of the intermediate tone mask at source region 111 and drain region 112
It is identical.Thus thickness of the photoresist 150 at source region 111 with drain region 112 is equal after exposure development and is less than photoresist 150 in ditch
Thickness at road area 113, then by etching stripping photoresist 150 so that insulating layer 140 forms different thickness gradients, specifically
The thickness in the insulating film layer region that channel region 113 is overlapped is greater than the insulating film layer region Chong Die with source region 111 and drain region 112.
It will be understood by those skilled in the art that light transmittance of the intermediate tone mask at source region, drain region and channel region can basis
The polysilicon layer grain size of required semiconductor devices is voluntarily selected, and the thickness gradient of insulating layer is thus reached, at this
Concrete restriction is not carried out to the light transmittance of intermediate tone mask in invention.
Carry out source region 111,112 and of drain region of insulating layer 140 by photoresist 150 using the half-tone mask technique herein
After the exposure of channel region 113, development and etching, the thickness of the corresponding insulating layer 140 of source region 111 and drain region 112 is smaller, channel region
The thickness of 113 corresponding insulating layers 140 is larger, and the rate of etching insulating layer 140 is different with the etching rate of photoresist 150,
Therefore channel region 113 is by the thickness of the insulating layer 140 corresponding with the both sides of the edge in drain region 112 of source area 111 in slowly reduction shape
State.
Illustratively, based on the above technical solution, the use intermediate tone mask technique of semiconductor devices is formed absolutely
The process of the thickness step of edge layer 140 includes:
Step 1: providing an intermediate tone mask with different light transmittances, wherein intermediate tone mask is corresponded on channel region 113
The light transmittance of masked areas of insulating layer 140 be less than the masked areas of corresponding source region 111 and the insulating layer 140 on drain region 112
Light transmittance.
Step 2: as shown in Figure 2 E, light is arranged on source region 111, drain region 112 and the corresponding insulating layer 140 of channel region 113
Photoresist 150.Using the intermediate tone mask with different light transmittances as exposure mask, after being exposed development to photoresist 150, photoresist
150 form required image and thickness gradient.It is optional in the present embodiment that photoresist 150 is exposed using ultraviolet light, it is purple
The expression way of outside line volume unit is mJ/cm2(millijoule/square centimeter), does not have exposure light in the present invention
Body limitation.
Step 3: being carried out as shown in Figure 2 D using the intermediate tone mask with different light transmittances as exposure mask to photoresist 150
The thickness step of insulating layer 140 is formed after exposure development and etching.The light transmittance of intermediate tone mask is different, therefore exposure development
Photoresist 150 forms thickness step afterwards, and the thickness gradient of insulating layer 140 is formed when stripping photoresist 150.
Herein with the intensity of ultraviolet light for 420~480mj/cm2Energy for, if insulating layer with a thickness of's
In the case of, the crystallite dimension of the polysilicon layer of semiconductor devices is whole all in 250nm or less.And when the thickness of insulating layer thickensWhen, when the energy of ultraviolet light is more than 445mj/cm2, the crystallite dimension of the polysilicon layer of semiconductor devices is integrally greater than
350nm.It can thus be appreciated that the principal element for influencing the crystallite dimension of the polysilicon layer of semiconductor devices is the thickness of insulating layer, exposure
Influence of the intensity of the ultraviolet light of development to polysilicon layer crystallite dimension is smaller.It will be understood by those skilled in the art that of the invention
It can also realize smaller polysilicon grain size, need to be adjusted according to thickness of the required crystallite dimension to insulating layer herein
Section, is no longer described in detail herein.
It should be noted that passing through the technique of photoresist 150 exposure development and etching, source region 111, drain region 112 and channel
The extra light shield layer 130 and insulating layer 140 of the exterior domain in area 113 has been etched removal, and source region 111, drain region 112 and channel
The insulating layer 140 in 113 region of area has formed thickness gradient.It will be appreciated by those skilled in the art that photoresist exposure, development and quarter
The process flow and method of erosion, the present invention in without specifically describe.
It will be understood by those skilled in the art that other works in addition to intermediate tone mask also can be used in other embodiments
Skill realizes the thickness step of insulating layer, does not carry out concrete restriction to this in the present invention.
Based on the above technical solution, after forming the thickness step of insulating layer 140 as shown in Figure 2 F, in insulating layer
Amorphous silicon layer 160 is formed on 140, there are many techniques for forming amorphous silicon layer 160, herein not specific example.It should be noted that
Light shield layer 130, insulating layer 140 and amorphous silicon layer 160 only need to be formed on source region 111, drain region 112 and channel region 113, therefore also
It needs to perform etching to remove extra amorphous silicon region the amorphous silicon layer 160 except source region 111, drain region 112 and channel region 113
Domain.It will be understood by those skilled in the art that the process of etching light shield layer 130, insulating layer 140 and amorphous silicon layer 160, can form
Direct etching after each film layer can also individually etch extra amorphous silicon region after the thickness gradient for forming insulating layer 140, carve
The sequence of step is lost in the present invention without concrete restriction.After being preferably formed as 140 thickness gradient of insulating layer in the present embodiment,
It forms amorphous silicon layer 160 and etches extra amorphous silicon region.
Crystallization is carried out to amorphous silicon layer 160 by the way of laser crystallization, so that amorphous silicon layer 160 is converted into polysilicon layer
(marking polysilicon layer with 160' in subsequent figures).The thickness of the corresponding insulating layer 140 of known source region 111 and drain region 112 is small
In the thickness of the corresponding insulating layer 140 of channel region 113, therefore light shield layer 130 is to the corresponding polysilicon of source region 111 and drain region 112
The rate of heat dispation of layer is greater than the rate of heat dispation to the corresponding polysilicon layer of channel region 113, therefore source region 111 and drain region 112 are corresponding
The temperature of polysilicon layer be lower than the temperature of the corresponding polysilicon layer of channel region 113, correspondingly, source region 111 and drain region 112 are corresponding
Polysilicon layer crystallite dimension be less than the corresponding polysilicon layer of channel region 113 crystallite dimension.
Illustratively, based on the above technical solution, after above-mentioned technique is completed, the manufacture of optional semiconductor devices
Method further include: form second buffer layer 170 as shown in Figure 2 G.Optional second buffer layer 170 is silicon nitride material.In order to protect
The internal structure of semiconductor devices, avoids internal structure from being corroded, and can form second buffer layer on the semiconductor device herein
170, second buffer layer 170 is identical with the material of first buffer layer 120, no longer illustrates herein.Optionally buffered in formation second
After layer 170, metal layer 180 is formed in the corresponding second buffer layer 170 of channel region 113 as illustrated in figure 2h, in the present invention not
It is specifically described.It will be understood by those skilled in the art that being formed after polysilicon layer, it is also necessary to form source by subsequent technique
Area, drain region and channel region, and source electrode, the drain and gate of semiconductor devices are formed, ability can be used in subsequent technique and process
The conventional technical means in domain manufactures, in the present invention without specifically describing.
In another embodiment, a kind of semiconductor devices is additionally provided, which uses as above-mentioned
Manufacturing method described in technical solution is manufactured.Light shield layer in the semiconductor devices serves not only as light blocking layer, while also making
For heat-conducting layer, one of intermediate tone mask technique can be completed thickness step and the light shield layer forming of insulating layer, pass through insulating layer
Thickness step realize semiconductor devices source region, drain region and the corresponding polysilicon layer of channel region crystal size difference, reach
The effect for inhibiting leakage current, improves the service life of semiconductor devices.It compared with prior art, can without increasing additional process
To play the role of similar LDD processing procedure.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (9)
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| CN113485075B (en) * | 2021-07-08 | 2022-09-30 | 中国科学技术大学 | Preparation method of wedge-shaped structure in mode spot converter and wedge-shaped structure |
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| WO2003105236A1 (en) * | 2002-06-07 | 2003-12-18 | ソニー株式会社 | Display unit and production method therefor, and projection type display unit |
| CN104538310A (en) * | 2015-01-16 | 2015-04-22 | 京东方科技集团股份有限公司 | Preparation method of low-temperature polycrystalline silicon film, TFT, array base plate and display device |
| CN104900532A (en) * | 2015-06-15 | 2015-09-09 | 京东方科技集团股份有限公司 | Thin film transistor, producing method thereof, array substrate, and display device |
| CN105097940A (en) * | 2014-04-25 | 2015-11-25 | 上海和辉光电有限公司 | Thin film transistor array substrate structure and manufacturing method thereof |
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| WO2003105236A1 (en) * | 2002-06-07 | 2003-12-18 | ソニー株式会社 | Display unit and production method therefor, and projection type display unit |
| CN105097940A (en) * | 2014-04-25 | 2015-11-25 | 上海和辉光电有限公司 | Thin film transistor array substrate structure and manufacturing method thereof |
| CN104538310A (en) * | 2015-01-16 | 2015-04-22 | 京东方科技集团股份有限公司 | Preparation method of low-temperature polycrystalline silicon film, TFT, array base plate and display device |
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