CN105977264A - Double-gate array substrate and manufacturing method thereof, display panel and display device - Google Patents

Abstract

The invention provides a double-gate array substrate, a manufacturing method thereof, a display panel, and a display device. In the array substrate provided by the embodiment of the present invention, the gate line can receive the gate drive signal transmitted by the gate drive circuit through several guide lines on the same layer as the data line and in the same direction as the data line, so that the array substrate can be used in display When installing, it is only necessary to set the fan-out area of the guide line at the side of the array substrate in the row direction, which effectively reduces the space occupied by both sides of the display device, thereby facilitating the realization of a frameless design of the display device.

Description

Double-gate array substrate and manufacturing method thereof, display panel, and display device

technical field

The invention relates to the field of display technology, in particular to a double-gate array substrate and a manufacturing method thereof, a display panel, and a display device.

Background technique

The current mainstream display device generally adopts the scan driving method, that is, the gate driving circuit sequentially applies signals to the gate lines connected to the sub-pixels in each row to turn on the sub-pixels in each row sequentially, and uses the data driving circuit to connect the sub-pixels in each column. A data voltage is applied on the data line so that the data voltage corresponding to each sub-pixel is written into each sub-pixel, and corresponding light emission control is completed.

Since the cost of the data driving circuit is much higher than that of the gate driving circuit, a dual-gate display device is proposed in the prior art, as shown in FIG. 1 , which includes several column data lines and several row gate lines. Wherein, every two rows of gate lines control the turn-on of a row of sub-pixel units, and each column of data lines is used to write data voltages in the turned-on sub-pixel units on adjacent sides thereof. This cuts the number of required data lines in half. In addition, each gate line is connected to the gate drive circuit through the gate line flexible connection circuit 1', so that the gate drive circuit provides a drive signal for the gate line. Each data line is connected to the data driving circuit through the data line flexible connection circuit 2', so that the data driving circuit provides the data voltage signal for the data line.

However, as shown in FIG. 1 , in a double-gate display device, since the gate lines fan out at the side frame of the display device, the gate line flexible connection circuit 1' for crimping the gate lines needs to be provided on the display device. In this way, a part of the space in the side frame of the display device is occupied by the grid line flexible connection circuit 1 ′, which is not conducive to the frameless design of the display device.

Contents of the invention

The purpose of the present invention is to solve the problem that the grid lines fan out at the side frame in the existing double-gate display device, and correspondingly make the grid line flexible connection circuit be arranged in the side frame of the display device, resulting in a part of the space in the side frame being covered by the grid line. The occupation of the flexible connection circuit is unfavorable for the frameless design of the display device.

In order to solve the above problems, the present invention provides a double-gate array substrate, a manufacturing method thereof, a display panel, and a display device.

In the first aspect, the present invention provides a double-gate array substrate, including sub-pixel units distributed in an array, several data lines and several gate lines,

Wherein, two gate lines are arranged between two adjacent rows of sub-pixel units, two columns of sub-pixel units are included between two adjacent data lines, and each data line is connected to two sub-pixel units in each row. sub-pixel units on both sides of the data line and adjacent to the data line;

The array substrate also includes several guide lines arranged on the same layer as the data lines, and each guide line is correspondingly arranged at a first gap area, and the first gap area is two adjacent data lines. In the gap area between the columns of sub-pixel units, each guide line is correspondingly connected to a gate line through a via hole, and is used to transmit a gate signal to the corresponding gate line.

Optionally,

The array substrate also includes several common electrode lines, each common electrode line is correspondingly arranged in a first void area; and the first void area where the common electrode lines are located is different from the first void area where the guide lines are located;

A common electrode is also formed on the array substrate, and the common electrode is connected to the common electrode line through a via hole.

Optionally, each guide line and each data line fan out in the same area.

Optionally, there are multiple fan-out areas for each guide line and multiple fan-out areas for each data line, and the fan-out areas for each guide line and the fan-out areas for each data line are arranged alternately.

In a second aspect, the present invention provides a method for manufacturing a double-gate array substrate, including:

An array of sub-pixel units distributed in an array, several data lines and several gate lines are formed on the array substrate; wherein, two gate lines are arranged between two adjacent rows of sub-pixel units, and two adjacent data lines contain two A row of sub-pixel units, each data line is connected to two sub-pixel units located on both sides of the data line and adjacent to the data line at the position of the sub-pixel unit in each row;

A number of guide lines arranged on the same layer as the data lines are also formed on the array substrate, and each guide line is correspondingly arranged at a first gap area, and the first gap area is two adjacent data lines. In the gap area between the two columns of sub-pixel units, each guide line is correspondingly connected to a gate line through a transfer hole, and is used to transmit a gate signal to the corresponding gate line.

Optionally, several common electrode lines are also formed on the array substrate, and each common electrode line is correspondingly formed in a first void area; the first void area is different;

A common electrode is also formed on the array substrate, and the common electrode is connected to the common electrode line through a via hole.

In a third aspect, the present invention provides a display panel, including the above-mentioned double-gate array substrate.

In a fourth aspect, a display device includes the above-mentioned display panel.

Optionally, the double-gate array substrate is an array substrate in which each guide line and each data line are fanned out in the same area; the display device further includes a gate drive circuit, a data drive circuit and a flexible connection circuit; The gate drive circuit and the data drive circuit are respectively connected to each guide line or each data line on the array substrate through the same flexible connection circuit.

Optionally, the double-gate array substrate has a plurality of fan-out areas of each guide line and a plurality of fan-out areas of each data line, and the fan-out area of each guide line and each data line An array substrate with alternately arranged fan-out areas; the display device also includes a gate drive circuit, a data drive circuit, and a flexible connection circuit; the gate drive circuit and the data drive circuit are respectively connected to the array substrate through different flexible connection circuits Each guide line or each data line on the grid is connected; wherein, the flexible connection circuits connected to the gate drive circuit and the flexible connection circuits connected to the data drive circuit are arranged alternately.

In the array substrate provided by the embodiment of the present invention, the gate line can receive the gate drive signal transmitted by the gate drive circuit through several guide lines on the same layer as the data line and in the same direction as the data line, so that the array substrate can be used in display When installing, it is only necessary to set the fan-out area of the guide line at the side of the array substrate in the row direction, which effectively reduces the space occupied by both sides of the display device, thereby facilitating the realization of a frameless design of the display device.

Description of drawings

The characteristic information and advantages of the present invention will be more clearly understood by referring to the accompanying drawings, which are schematic and should not be construed as limiting the present invention in any way, in the accompanying drawings:

FIG. 1 is a schematic structural view of a display device including a double-gate array substrate in the prior art;

FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a display device provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another display device provided by an embodiment of the present invention.

detailed description

In order to understand the above-mentioned purpose, features and advantages of the present invention more clearly, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described here. Therefore, the protection scope of the present invention is not limited by the specific details disclosed below. EXAMPLE LIMITATIONS.

In a first aspect, the embodiment of the present invention provides a double-gate array substrate, including sub-pixel units distributed in an array, several data lines and several gate lines.

Wherein, two gate lines are arranged between two adjacent rows of sub-pixel units, two columns of sub-pixel units are included between two adjacent data lines, and each data line is connected to two sub-pixel units in each row. Sub-pixel units on both sides of the data line and adjacent to the data line.

The double-gate array substrate also includes several guiding lines arranged on the same layer as the data lines, and each guiding line is correspondingly arranged at a first gap area. Wherein, the first gap area here is the gap area between two columns of sub-pixel units between two adjacent data lines. In addition, each guide line is correspondingly connected to a gate line through a transfer hole, and is used for transmitting a gate signal to the corresponding gate line.

In the array substrate provided by the embodiment of the present invention, the gate line can receive the gate drive signal transmitted by the gate drive circuit through several guide lines on the same layer as the data line and in the same direction as the data line, so that the array substrate can be used in display When installing, it is only necessary to set the fan-out area of the guide line at the side of the array substrate in the row direction, which effectively reduces the space occupied by both sides of the display device, thereby facilitating the realization of a frameless design of the display device.

In practical applications, the sub-pixel units here may be red sub-pixel units, green sub-pixel units or blue sub-pixel units.

During specific implementation, the structure of the above-mentioned double-gate array substrate may be expressed in many different forms. Some of the implementation manners will be specifically described below in conjunction with the accompanying drawings.

Referring to FIG. 2 , the array substrate shown in FIG. 2 includes sub-pixel units P and several gate lines G distributed in an array. Wherein, two gate lines G are arranged between two adjacent rows of sub-pixel units P. For each row of sub-pixel units P, one of the gate lines adjacent to the row of sub-pixel units P is connected to the even-numbered column pixel units in the row of sub-pixel units P, and the other gate line is connected to the row of sub-pixel units P. The odd-numbered column of pixel units, so that the row of sub-pixel units P is turned on at the time when it should be turned on in each frame under the common control of the two gate lines. For example, the first row of sub-pixel units P in FIG. 2 is jointly controlled by gate lines G1 and G2, and the second row of sub-pixel units P is jointly controlled by gate lines G3 and G4. Meanwhile, the array substrate shown in FIG. 2 also includes several data lines D. As shown in FIG. Wherein, two columns of sub-pixel units P are included between two adjacent data lines D, and each data line D is connected to two adjacent sub-pixel units P for inputting a data voltage to the sub-pixel units P when turned on.

In addition, the double-gate array substrate also includes several guide lines L arranged on the same layer as the data lines. Wherein, each guide line L is correspondingly arranged in the gap area between two columns of sub-pixel units P between two adjacent data lines D. Each guide line L is correspondingly connected to a gate line G through the transfer hole O, for example, the guide line L1 is connected to the gate line G1 through the transfer hole O1, so that the guide line L is connected to the gate drive circuit The gate signal is transmitted to each corresponding gate line G under the control of .

It can be understood that when the above-mentioned array substrate is applied to a display device, since the gate lines are connected to the gate drive circuit through guide lines, it is only necessary to connect the fan-out lines of the guide lines to the gate drive circuit. The gate drive circuit transmits signals to the gate lines. And the guide lines are arranged in the same direction as the data lines, so the guide lines can be fanned out on the side where the data lines are fanned out, so that there is no need to set a fan-out area for the gate lines at the side of the display device, so that there is It is beneficial to the frameless design of the display device.

During specific implementation, the array substrate provided by the embodiment of the present invention may further include several common electrode lines. Referring to FIG. 2, in the array substrate provided by the embodiment of the present invention, each common electrode line COM is correspondingly arranged in a first gap area, that is, in the area between two columns of sub-pixel units P between two columns of data lines D , and the area where the common electrode line COM is located is different from the area where the guide line L is located. That is to say, only one common electrode line COM or one guiding line L can be arranged between every two columns of sub-pixel units P. Correspondingly, a common electrode (not shown in FIG. 2 ) is also formed on the array substrate. Wherein, the common electrode and the common electrode line COM may be connected through a via hole, so as to transmit a common electrode signal to the common electrode.

It can be understood that the number of gate lines and common electrode lines in the array substrate provided by the present invention can be designed according to the number of rows and columns of sub-pixel units in the array substrate. Specifically, if the array substrate includes M rows and N columns of sub-pixel units, since it adopts a double-gate design, only N/2 data lines and 2M gate lines need to be provided. Furthermore, it is necessary to arrange 2M guide lines in the same layer and in the same direction as the data lines in any 2M first void regions of the array substrate, so that all 2M gate lines are connected to corresponding guide lines. It is not difficult to understand that after the 2M guide lines are provided, there are still N/2-2M first void areas on the array substrate where no guide lines are provided. At this time, the common electrode lines can be arranged in these first gap regions. Therefore, the number of common electrode lines included on the array substrate can be N/2-2M, so that the structure of the array substrate provided by the present invention can meet the basic display requirements including the array substrate.

In a specific implementation, there may be many ways to implement the fan-out of each guide line and each data line on the side of the array substrate in the row direction. Two optional fan-out modes are described below with reference to FIG. 3 and FIG. 4 .

Figure 3 shows a fan-out mode of guide lines and data lines. Since the guide lines L and data lines D in the array substrate are arranged in the same direction, each guide line and each data line can be in the same 3 shows the lower fan-out of the array substrate. Wherein, there are multiple fan-out areas for each guide line L and each data line D, and the fan-out areas for each guide line L and the fan-out areas for each data line D are arranged alternately. When the array substrate is applied to a display device, the alternately fanned-out guide lines L and data lines D may be respectively connected to corresponding driving circuits through different flexible connection circuits. For example, the guide line L can be connected to the gate drive circuit through the flexible connection circuit 1, and the data line D can be connected to the data drive circuit through the flexible connection circuit 1, so that the gate line G can receive the gate drive circuit through the guide line L. According to the driving signal, the sub-pixel unit P of the corresponding row is controlled to be turned on. The data line D receives the data voltage provided by the data driving circuit and writes the data voltage when the sub-pixel unit P is turned on.

Fig. 4 shows another fan-out method of guide lines and data lines. Different from Fig. 3, each guide line L and each data line D in the array substrate shown in Fig. 4 can be in the same area Fan-out. When the array substrate is applied to a display device, the guide line L and the data line D fanned out in the same area can be connected to the gate driving circuit or the data driving circuit through the same flexible connection circuit 3 . The advantage of doing this is that it facilitates the crimping of the guide wire and the data wire, thereby reducing the difficulty of making the crimping part.

Of course, the guide lines and the data lines in the array substrate provided by the embodiment of the present invention may also be fanned out in other ways, which is not specifically limited in the present invention.

It is not difficult to understand that the illustrations in the above embodiments are only for better understanding of the array substrate provided in the embodiments of the present invention, and cannot constitute a specific limitation of the present invention. Moreover, the above-mentioned preferred implementation modes will not affect each other, and the solution obtained by any combination of the preferred implementation modes shall fall within the scope of protection of the present invention.

In the second aspect, the embodiment of the present invention also provides a method for manufacturing a double-gate array substrate, including:

S101, forming an array of sub-pixel units distributed in an array, a plurality of data lines and a plurality of gate lines on the array substrate;

Wherein, two gate lines are arranged between two adjacent rows of sub-pixel units, two columns of sub-pixel units are included between two adjacent data lines, and each data line is connected to two sub-pixel units in each row. sub-pixel units on both sides of the data line and adjacent to the data line;

S102. Several guiding lines arranged on the same layer as the data lines are also formed on the array substrate, and each guiding line is correspondingly arranged at a first gap area, and the first gap area is between two adjacent data lines In the gap area between two columns of sub-pixel units, each guide line is correspondingly connected to a gate line through a via hole, and is used to transmit a gate signal to the corresponding gate line.

In the array substrate manufactured by the above manufacturing method, the gate line can receive the gate drive signal transmitted by the gate drive circuit through several guide lines on the same layer as the data line and in the same direction as the data line, so that the array substrate can be used in display When installing, it is only necessary to set the fan-out area of the guide line at the side of the array substrate in the row direction, which effectively reduces the space occupied by both sides of the display device, thereby facilitating the realization of a frameless design of the display device.

In specific implementation, in order to enable the array substrate manufactured by the above manufacturing method to control the luminous intensity in each sub-pixel unit, the manufacturing method provided in the embodiment of the present invention further includes:

S201. Several common electrode lines are further formed on the array substrate, and each common electrode line is correspondingly formed in a first void area; and the first void area where the common electrode line is located and the first void area where the guide line is located different;

S202, a common electrode is further formed on the array substrate, and the common electrode is connected to the common electrode line through a via hole.

Since the fabrication method provided in the embodiment of the present invention is fabricated according to the structure of the double-gate array substrate provided by the present invention, those skilled in the art can know the method of fabricating the substrate according to the structure of the double-gate array substrate introduced above, so The method for manufacturing the double-gate array substrate provided by the present invention will not be repeated here.

In a third aspect, the embodiment of the present invention further provides a display panel, including the above-mentioned double-gate array substrate. Since in the double-gate array substrate, the data lines and the guide lines connected to the gate lines are fanned out on the side in the row direction, there is no need to set the fan-out area of the gate lines on the side, so that the display of the display panel applied The device can realize the purpose of frameless design.

In a fourth aspect, an embodiment of the present invention further provides a display device, which includes the above-mentioned display panel.

Wherein, the double-gate array substrate included in the display panel here is the double-gate array substrate as described in the first aspect. In addition, the display device herein may further include a gate driving circuit, a data driving circuit and a flexible connection circuit. It can be understood that both the gate drive circuit and the data drive circuit are arranged on the PCB outside the display panel, therefore, the gate drive circuit and the data drive circuit need to be connected to the corresponding guide lines and data lines through a flexible connection circuit .

It can be understood that there are many ways in which the gate driving circuit and the data driving circuit need to be connected to the guide line and the data line through the flexible connection circuit. For example, as shown in FIG. 3 , the gate driving circuit and the data driving circuit can be respectively connected to each guiding line or each data line on the array substrate through different flexible connection circuits. In addition, the flexible connection circuits connected to the gate driving circuit and the flexible connection circuits connected to the data driving circuit are arranged alternately. Specifically, the gate drive circuit arranged on the PCB is connected to the guide line L through the flexible connection circuit 1 , so as to transmit the gate drive signal to the gate line G corresponding to the guide line L. The data driving circuit arranged on the PCB is connected to the data line D through the flexible connection circuit 2 , so as to transmit the data voltage signal to the data line D. Each flexible connection circuit 1 and each flexible connection circuit 2 are arranged alternately, so that the display device can meet basic display requirements.

For another example, as shown in FIG. 4 , the gate driving circuit and the data driving circuit can be respectively connected to each guiding line or each data line on the array substrate through the same flexible connection circuit. Specifically, the gate driving circuit and the data driving circuit arranged on the PCB can be respectively connected to the guide line L or the data line D on the array substrate through the flexible connection circuit 3 . The advantage of doing this is that it facilitates the crimping of the guide wires and the data wires, thereby making it difficult to manufacture the crimping parts and simplifying the manufacturing process of the entire display device.

In a specific implementation, the flexible connection circuit here may be COF (Chip On Flex, or Chip On Film, commonly referred to as chip-on-film), or may be FPC (Flexible Printed Circuit board, flexible circuit board). The present invention does not specifically limit it.

In addition, the display device here may be: electronic paper, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator and any other product or component with display function.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (10)

1. a double grid array base palte, it is characterised in that: include the sub-pixel list of array distribution Unit, some data line and some grid lines,

Wherein, two grid lines, adjacent two data it are provided with between adjacent rows sub-pixel unit Comprising two row sub-pixel unit between line, each data line is in the sub-pixel unit position of every a line The place of putting connects two both sides being positioned at this data wire and all adjacent with this data wire sub-pixel list Unit；

Described array base palte also includes some the guide wires arranged with data wire with layer, each Guide wire is correspondingly arranged at first void area, and described first void area is adjacent two Void area between two row sub-pixel unit between data line, each guide wire all passes through Transfer hole is corresponding connected with a grid line, for corresponding grid line transmission signal.

Array base palte the most according to claim 1, it is characterised in that

Described array base palte also includes some public electrode wires, each public electrode wire correspondence It is arranged in first void area；And first void area at public electrode wire place with lead First void area at lead-in wire place is different；

Public electrode, described public electrode and described common electrical it is also formed with on described array base palte Polar curve is connected by via.

3. according to the arbitrary described array base palte of claim 1-2, it is characterised in that each bar is led Lead-in wire and pieces of data line are in the same area fan-out.

4. according to the arbitrary described array base palte of claim 1-2, it is characterised in that each bar is led The fan-out area of lead-in wire is multiple with the fan-out area of pieces of data line, and each bar guide wire Fan-out area is alternately arranged with the fan-out area of pieces of data line.

5. the manufacture method of a double grid array base palte, it is characterised in that including:

Array base palte is formed the sub-pixel unit of array distribution, if some data line and Dry bar grid line；Wherein, between adjacent rows sub-pixel unit, it is provided with two grid lines, adjacent two Comprising two row sub-pixel unit between data line, each data line is at the sub-pixel of every a line Two both sides being positioned at this data wire and all adjacent with this data wire is connected at cell position Pixel cell；

Described array base palte is also formed with some the guide wires arranged with layer with data wire, Each guide wire is correspondingly arranged at first void area, and described first void area is Void area between two row sub-pixel unit between adjacent two data line, each guide wire All corresponding connected with a grid line by transfer hole, for corresponding grid line transmission grid letter Number.

Method the most according to claim 5, it is characterised in that including:

Described array base palte is also formed with some public electrode wires, each public electrode Line is correspondingly formed in first void area；And first interstice coverage at public electrode wire place Territory is different from first void area at guide wire place；

Described array base palte is also formed with public electrode, described public electrode and described public Electrode wires is connected by via.

7. a display floater, it is characterised in that include as described in claim 1-4 is arbitrary Double grid array base palte.

8. a display device, it is characterised in that include display surface as claimed in claim 7 Plate.

9. display device as claimed in claim 8, it is characterised in that described double grid array base Plate is array base palte as claimed in claim 4；Described display device also includes raster data model electricity Road, data drive circuit and flexibly connect circuit；Described gate driver circuit drives with described data Galvanic electricity road by identical flexibly connect circuit respectively with each bar guide wire on array base palte or Pieces of data line is connected.

10. display device as claimed in claim 8, it is characterised in that described double grid array Substrate is array base palte as claimed in claim 5；Described display device also includes raster data model Circuit, data drive circuit and flexibly connect circuit；Described gate driver circuit and described data Drive circuit by different flexibly connect circuit respectively with each bar guide wire on array base palte Or pieces of data line is connected；Wherein, what gate driver circuit connected flexibly connects circuit and data It is alternately arranged that what drive circuit connected flexibly connects circuit.