CN105978498B - A kind of low-noise amplifier of the adjustable gain of single ended input both-end output - Google Patents
A kind of low-noise amplifier of the adjustable gain of single ended input both-end output Download PDFInfo
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- CN105978498B CN105978498B CN201610435063.9A CN201610435063A CN105978498B CN 105978498 B CN105978498 B CN 105978498B CN 201610435063 A CN201610435063 A CN 201610435063A CN 105978498 B CN105978498 B CN 105978498B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
- H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/372—Noise reduction and elimination in amplifier
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Abstract
The invention discloses a kind of low-noise amplifiers of the adjustable gain of single ended input both-end output, belong to radio communication circuit field, including：Single-turn difference amplifying circuit (100) and buffer circuit (200)；Single-turn difference amplifying circuit (100) includes that differential amplification multiple adjusts sub-circuit (100)；Further comprise：The grid amplifier tube (Mg) being connect with single ended inputs (In1), the source electrode amplifier tube (Ms) being connect with grid amplifier tube (Mg)；Source electrode amplifier tube (Ms) includes multiple NMOS units, pass through the NMOS units for selecting to be connected to different numbers, to adjust size multiple of the source electrode amplifier tube (Ms) relative to grid amplifier tube (Mg), and then adjust to single ended signal (SIn) differential amplification multiple, obtain the differential signal of different amplification；Buffer circuit (200) is used to receive the differential signal by differential input end (In2 ±), and handles it, to obtain new differential signal for exporting；Realize adjustable gain and balance difference output.
Description
Technical field
The present invention relates to the low-noise amplifier fields of radio communication circuit more particularly to a kind of single ended input both-end to export
Adjustable gain low-noise amplifier.
Background technology
In recent years, wireless communication technique is constantly developing, to meet the different demands of all trades and professions.Low noise amplification
Device (LNA, Low Noise Amplifier) is usually used in the front end of radio-frequency receiving system, and the overall performance to receiving system plays
Vital effect needs certain gain to amplify the small-signal and suppression system late-class circuit that antenna receives
Noise jamming, while the noise coefficient of itself wants the low, linearity to want high, and needs the single-ended signal that will be received from antenna
Be converted to differential output signal.The design difficulty of low-noise amplifier is that how the above index to be compromised.
LNA currently on the market is broadly divided into two kinds, will be from antenna one is single-ended transfer difference transformer is used outside piece
The signal received, which is converted to be sent in LNA after differential signal, carries out signal processing, and LNA is designed to differential-input differential at this time
Export structure, this structure has good symmetry, but the outer transformer of broadband sheet increases cost；Another is in piece
Single ended input, difference output network are inside done, this LNA does not need the outer transformer of piece, and noise may be used and eliminate, is non-linear
It the technologies such as offsets and improves noise coefficient and the linearity, but often there is difference output end impedance unbalance in this structure, and
The problem of causing LNA to export unbalanced differential signal.
Invention content
For the present invention for existing in the prior art, the signal gain amplifier that single ended input both-end exports LNA is insufficient and not
Adjustable and output the unbalanced technical problem of differential signal provides a kind of adjustable gain of single ended input both-end output
Low-noise amplifier, can realize the differential amplification processing that adjustable gain is carried out to the single-ended signal of input, and output is flat
The technique effect of the differential signal of weighing apparatus.
The present invention provides a kind of low-noise amplifiers of the adjustable gain of single ended input both-end output, including：Single-turn is poor
Amplifying circuit and first order buffer circuit；
The single-turn difference amplifying circuit includes that the single ended inputs being sequentially communicated, differential amplification multiple adjust sub-circuit and the
One difference output end, the first order buffer circuit include the first differential input end and the second difference output end；
The single-turn difference amplifying circuit is used to receive single ended signal by the single ended inputs, and passes through the difference
Point amplification factor adjusts that sub-circuit is filtered enhanced processing to the single ended signal and phase amplitude adjusts, to obtain the
One differential signal, and first differential signal is exported by first difference output end；
Wherein, the differential amplification multiple adjusting sub-circuit includes：The grid amplifier tube being connect with the single ended inputs,
The source electrode amplifier tube being connect with the grid amplifier tube, one-to-one correspondence are connect with the grid amplifier tube and the source electrode amplifier tube
First resistor and second resistance；The source electrode amplifier tube includes multiple NMOS units, and the source electrode amplification is connected to by selecting
The NMOS units of different numbers in pipe, to adjust size multiple of the source electrode amplifier tube relative to the grid amplifier tube, into
And adjust the differential amplification multiple and adjust sub-circuit to the differential amplification multiple of the single ended signal, obtain different amplifications
First differential signal of multiple；
The first order buffer circuit is used to receive first differential signal by first differential input end, and right
First differential signal is filtered and enhanced processing, to obtain the second differential signal, and passes through second difference output
End exports second differential signal.
Optionally, the differential amplification multiple adjusting sub-circuit further includes：
Correspond the first NMOS tube and the second NMOS tube being connect with the grid amplifier tube and the source electrode amplifier tube；
Wherein, the grid amplifier tube is connect by first NMOS tube with the first resistor, and the source electrode amplifier tube passes through institute
The second NMOS tube is stated to connect with the second resistance；
Second NMOS tube includes multiple NMOS units, when the source electrode amplifier tube is relative to the grid amplifier tube
When size multiple is conditioned, by selecting to be connected to the NMOS units of different numbers in second NMOS tube, institute is adjusted with corresponding
State size multiple of second NMOS tube relative to first NMOS tube.
Optionally, the first resistor is adjustable resistance；When the source electrode amplifier tube is relative to the grid amplifier tube
When size multiple is conditioned, the corresponding resistance multiple for adjusting the first resistor relative to the second resistance.
Optionally, the differential amplification multiple adjusting sub-circuit further includes：First power input, the first bias voltage are defeated
Enter end, the second bias voltage input, third bias voltage input, 3rd resistor, the first capacitance, the second capacitance and the first electricity
Sense；
First power input is respectively connected to one end of the first resistor and the second resistance, and described first
The other end of resistance connects the drain electrode of first NMOS tube, and the other end of the second resistance connects second NMOS tube
Drain electrode；The grid of first NMOS tube is connect with first bias voltage input, for passing through first biased electrical
Input terminal is pressed to input the first bias voltage；The grid of second NMOS tube is connect with second bias voltage input, is used
In pass through second bias voltage input input the second bias voltage；The source electrode of first NMOS tube connects the grid
The drain electrode of amplifier tube；The source electrode of second NMOS tube connects the drain electrode of the source electrode amplifier tube；The grid of the grid amplifier tube
Pole connects the third bias voltage input；The grid of the source electrode amplifier tube connects the third by 3rd resistor and biases
Voltage input end or 0V voltages；The source electrode of the grid amplifier tube is separately connected one end of first capacitance, second electricity
One end of one end of appearance and first inductance, the other end of first capacitance is for inputting the single ended signal, institute
The other end for stating the second capacitance connects the grid of the source electrode amplifier tube, the other end ground connection of first inductance；The source electrode
The source electrode of amplifier tube is grounded.
Optionally, the low-noise amplifier further includes：Second level buffer circuit；
The second level buffer circuit includes the second differential input end and third difference output end；Second Differential Input
End is connect with second difference output end；
The second differential signal that the second level buffer circuit is used to export the first order buffer circuit is into traveling one
The filter amplifying processing and phase amplitude of step adjust, to obtain third differential signal, and it is defeated by the third difference output end
Go out the third differential signal；
Two outputs of second difference output end and the third difference output end as the low-noise amplifier
Port, the differential output signal for selectively exporting the low-noise amplifier.
Optionally, the low-noise amplifier further includes：Switch selection circuit；
The switch selection circuit is connect with second difference output end and the third difference output end, for opening
Off status selects the difference of second differential signal or the third differential signal as the low-noise amplifier when changing
Output signal.
Optionally, the first order buffer circuit includes：High-pass filter and fully-differential amplifier；The high-pass filter
Differential input end connect first differential input end, the difference output end of the high-pass filter connects the fully differential and puts
The differential input end of big device；The difference output end of the fully-differential amplifier connects second difference output end.
Optionally, the high-pass filter includes：Third capacitance, the 4th capacitance, the 4th resistance, the 5th resistance and the 4th are partially
Set voltage input end；One end of the third capacitance and the 4th capacitance is for inputting first differential signal, and described the
The other end of three capacitances connects one end of the 4th resistance, also connect with the fully-differential amplifier, the 4th capacitance
The other end connects one end of the 5th resistance, also connect with the fully-differential amplifier, the 4th resistance and the 5th resistance
The other end is connected and is connect with the 4th bias voltage input.
Optionally, the fully-differential amplifier includes：Second source input terminal, the 6th resistance, the 7th resistance, the 3rd NMOS
Pipe, the 4th NMOS tube, the 5th NMOS tube and the 5th bias voltage input；
The second source input terminal is respectively connected to one end of the 6th resistance and the 7th resistance, and the described 6th
The other end of resistance and the 7th resistance is separately connected the drain electrode of the third NMOS tube and the 4th NMOS tube；Described
The grid of three NMOS tubes connects the third capacitance；The grid of 4th NMOS tube connects the 4th capacitance；The third
The source electrode of NMOS tube connects the drain electrode of the 5th NMOS tube；The source electrode of 4th NMOS tube connects the 5th NMOS tube
Drain electrode；5th bias voltage input connects the grid of the 5th NMOS tube；The source electrode of 5th NMOS tube is grounded.
Optionally, the structure of the second level buffer circuit is identical as the structure of first order buffer circuit.
The one or more technical solutions provided in the present invention, have at least the following technical effects or advantages：
Due in the present invention, the low-noise amplifier of the adjustable gain of single ended input both-end output, including：Single-turn difference is put
Big circuit and first order buffer circuit；The single-turn difference amplifying circuit includes the single ended inputs being sequentially communicated, differential amplification times
Number adjusts sub-circuit and the first difference output end, and the first order buffer circuit includes that the first differential input end and the second difference are defeated
Outlet；The single-turn difference amplifying circuit is used to receive single ended signal by the single ended inputs, and passes through the difference
Amplification factor adjusts sub-circuit and carries out differential amplification to the single ended signal, to obtain the first differential signal, and passes through institute
It states the first difference output end and exports first differential signal；Wherein, the differential amplification multiple adjusting sub-circuit includes：With institute
State the grid amplifier tube of single ended inputs connection, the source electrode amplifier tube being connect with the grid amplifier tube；The source electrode amplifier tube
Including multiple NMOS units, by selecting to be connected to the NMOS units of different numbers in the source electrode amplifier tube, to adjust the source
Size multiple of the pole amplifier tube relative to the grid amplifier tube, and then adjust the differential amplification multiple and adjust sub-circuit to institute
The differential amplification multiple for stating single ended signal obtains the first differential signal of different amplification；Further, the first order
Buffer circuit is used to receive first differential signal by first differential input end, and to first differential signal into
Row filter amplifying processing and phase amplitude adjustment to obtain the second differential signal, and are exported by second difference output end
Second differential signal.The signal gain amplifier for efficiently solving single ended input both-end output LNA in the prior art is insufficient
And non-adjustable and output the unbalanced technical problem of differential signal, the single-ended signal progress gain realized to input can
The differential amplification of tune is handled, and the differential signal of balance is exported after buffer circuit is handled.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the low-noise amplifier of the adjustable gain of the first single ended input both-end provided in an embodiment of the present invention output
Structural schematic diagram；
Fig. 2 is a kind of structural schematic diagram of single-turn difference amplifying circuit of low-noise amplifier provided in an embodiment of the present invention；
Fig. 3 is a kind of circuit diagram of specific implementation mode of single-turn difference amplifying circuit shown in Fig. 2；
Fig. 4 is a kind of structural representation for the source electrode amplifier tube being made of four NMOS units provided in an embodiment of the present invention
Figure；
Fig. 5 A are the low noise amplification of the adjustable gain of second of single ended input both-end provided in an embodiment of the present invention output
The structural schematic diagram of device；
Fig. 5 B are that a kind of structure of specific implementation mode of the switch selection circuit of low-noise amplifier shown in Fig. 5 A is shown
It is intended to；
Fig. 6 is a kind of structural schematic diagram of the first order buffer circuit of low-noise amplifier provided in an embodiment of the present invention；
Fig. 7 is a kind of structural schematic diagram of the second level buffer circuit of low-noise amplifier provided in an embodiment of the present invention.
Specific implementation mode
The embodiment of the present invention is solved by providing a kind of low-noise amplifier of the adjustable gain of single ended input both-end output
It is existing in the prior art, single ended input both-end export LNA signal gain amplifier is insufficient and non-adjustable and the difference that exports
The unbalanced technical problem of sub-signal realizes the differential amplification processing that adjustable gain is carried out to the single-ended signal of input, and
Export the technique effect of the differential signal of balance.
The technical solution of the embodiment of the present invention is in order to solve the above technical problems, general thought is as follows：
An embodiment of the present invention provides a kind of low-noise amplifiers of the adjustable gain of single ended input both-end output, including：
Single-turn difference amplifying circuit and first order buffer circuit；The single-turn difference amplifying circuit includes the single ended inputs being sequentially communicated, difference
Point amplification factor adjusts sub-circuit and the first difference output end, and the first order buffer circuit includes the first differential input end and the
Two difference output ends；The single-turn difference amplifying circuit is used to receive single ended signal by the single ended inputs, and passes through
The differential amplification multiple adjusts sub-circuit and carries out differential amplification to the single ended signal, to obtain the first differential signal,
And first differential signal is exported by first difference output end；Wherein, the differential amplification multiple adjusts sub-circuit
Including：The grid amplifier tube being connect with the single ended inputs, the source electrode amplifier tube being connect with the grid amplifier tube, one is a pair of
The first resistor and second resistance that should be connect with the grid amplifier tube and the source electrode amplifier tube；The source electrode amplifier tube includes
Multiple NMOS units are put by selecting to be connected to the NMOS units of different numbers in the source electrode amplifier tube with adjusting the source electrode
Big size multiple of the pipe relative to the grid amplifier tube, and then adjust the differential amplification multiple and adjust sub-circuit to the list
The differential amplification multiple for holding input signal, obtains the first differential signal of different amplification；The first order buffer circuit is used
In receiving first differential signal by first differential input end, and amplification is filtered to first differential signal
Processing and phase amplitude adjustment, to obtain the second differential signal, and it is poor by second difference output end output described second
Sub-signal.
As it can be seen that in embodiments of the present invention, the single-turn difference amplifying circuit of low-noise amplifier includes differential amplification multiple tune
Knot circuit.The differential amplification multiple adjusts sub-circuit and further comprises：The grid amplifier tube being connect with single ended inputs makees 50
The input resistant matching of ohm；The source electrode amplifier tube being connect with the grid amplifier tube, to the single ended signal that receives into
The reversed amplification of row；The first resistor and second resistance being connect with the grid amplifier tube and the source electrode amplifier tube are corresponded,
Make the load resistance of the grid amplifier tube and the source electrode amplifier tube respectively；The source electrode amplifier tube includes multiple NMOS mono-
Member, by selecting to be connected to the NMOS units of different numbers in the source electrode amplifier tube, with adjust the source electrode amplifier tube relative to
The size multiple of the grid amplifier tube, and then adjust the differential amplification multiple and adjust sub-circuit to the single ended signal
Differential amplification multiple, obtain the first differential signal of different amplification；Wherein, when the size of source electrode amplifier tube is put for grid
N times (N is random natural number) of big pipe, bias voltage is equal, and N times that first resistor is second resistance, can ensure in this way
In the forward signal of difference output end and the noise cancellation equal, and that grid amplifier tube is generated of the amplification factor of reverse signal,
Enough gains can be provided as needed simultaneously, come the noise for inhibiting late-class circuit to generate.Further, pass through low noise amplification
The first order buffer circuit of device is filtered enhanced processing to first differential signal and phase amplitude adjusts, to obtain second
Differential signal, using when needed as the final differential output signal of the low-noise amplifier.Efficiently solve the prior art
The signal gain amplifier of middle single ended input both-end output LNA is insufficient and non-adjustable and the unbalanced skill of differential signal of output
Art problem realizes the differential amplification processing for carrying out adjustable gain to the single-ended signal of input, and is handled by buffer circuit
The differential signal of balance is exported afterwards.
In order to better understand the above technical scheme, in conjunction with appended figures and specific embodiments to upper
It states technical solution to be described in detail, it should be understood that the specific features in the embodiment of the present invention and embodiment are to the application
The detailed description of technical solution, rather than to the restriction of technical scheme, in the absence of conflict, the present invention is implemented
Technical characteristic in example and embodiment can be combined with each other.
Referring to FIG. 1, an embodiment of the present invention provides a kind of low noises of the adjustable gain of single ended input both-end output to put
Big device, including：Single-turn difference amplifying circuit 100 and first order buffer circuit 200；
Single-turn difference amplifying circuit 100 includes the single ended inputs In1 being sequentially communicated, differential amplification multiple adjusting sub-circuit
101 and first difference output end (OUT1+, OUT1-), first order buffer circuit 200 include the first differential input end (In2+,
) and the second difference output end (OUT2+, OUT2-) In2-；
Single-turn difference amplifying circuit 100 is used to receive single ended signal S by single ended inputs In1In, and pass through the difference
Amplification factor is divided to adjust sub-circuit 101 to the single ended signal SInDifferential amplification is carried out, to obtain the first differential signal, and
First differential signal is exported by the first difference output end (OUT1+, OUT1-)；
Wherein, differential amplification multiple adjusting sub-circuit 101 includes：The grid amplifier tube Mg being connect with single ended inputs In1,
Make 50 ohm of input resistant matching；The source electrode amplifier tube Ms being connect with grid amplifier tube Mg believes the single ended input received
Number SInReversely amplified；It corresponds and the electricity of grid amplifier tube Mg and source electrode amplifier tube Ms the first resistor R1 connecting and second
R2 is hindered, makees the load resistance of the grid amplifier tube and the source electrode amplifier tube respectively；Source electrode amplifier tube Ms includes multiple N-type gold
Belong to oxide semiconductor (NMOS, N-Mental-Oxide-Semiconductor) unit and referred to as " NMOS units " passes through selection
The NMOS units of different numbers in source electrode amplifier tube Ms are connected to, to adjust rulers of the source electrode amplifier tube Ms relative to grid amplifier tube Mg
Very little multiple, and then adjust differential amplification multiple and adjust sub-circuit 101 to single ended signal SInDifferential amplification multiple, obtain not
With the first differential signal of amplification factor；
First order buffer circuit 200 is used to receive the first difference letter by the first differential input end (In2+, In2-)
Number, and enhanced processing and phase amplitude adjustment are filtered to first differential signal, to obtain the second differential signal, and lead to
It crosses the second difference output end (OUT2+, OUT2-) and exports second differential signal.
It please refers to Fig.1 and Fig. 2, in specific implementation process, differential amplification multiple adjusts sub-circuit 101 and further includes：One by one
It corresponds to and grid amplifier tube Mg and source electrode amplifier tube Ms the first NMOS tube M1 connecting and the second NMOS tube M2；Wherein, grid is put
Big pipe Mg is connect by the first NMOS tube M1 with first resistor R1, and source electrode amplifier tube Ms passes through the second NMOS tube M2 and second resistance
R2 connections.
Further, referring still to Fig. 2, differential amplification multiple adjusts sub-circuit 101 and further includes：First power input
VDD1, the first bias voltage input VB1, the second bias voltage input VB2, third bias voltage input VB3, third electricity
Hinder R3, the first capacitance C1, the second capacitance C2 and the first inductance Lext.
First power input VDD1 is respectively connected to one end of first resistor R1 and second resistance R2, first resistor R1's
The other end connects the drain electrode of the first NMOS tube M1, and the other end of second resistance R2 connects the drain electrode of the second NMOS tube M2；First
The grid of NMOS tube M1 is connect with the first bias voltage input VB1, for passing through the first bias voltage input VB1 input the
One bias voltage；The grid of second NMOS tube M2 is connect with the second bias voltage input VB2, for passing through the second bias voltage
Input terminal VB2 inputs the second bias voltage；The drain electrode of the source electrode connection grid amplifier tube Mg of first NMOS tube M1；Second NMOS tube
The drain electrode of the source electrode connection source electrode amplifier tube Ms of M2；The grid connection third bias voltage input VB3 of grid amplifier tube Mg；Source
The grid of pole amplifier tube Ms passes through 3rd resistor R3 connection third bias voltage inputs VB3 or 0V electricity under the control of control bit
Pressure；The source electrode of grid amplifier tube Mg is separately connected one end of the first capacitance C1, one end of the second capacitance C2 and the first inductance Lext
One end, the other end of the first capacitance C1 is for inputting single ended signal SIn, the second capacitance C2 the other end connection source electrode put
The grid of big pipe Ms, the other end ground connection of the first inductance Lext；The source electrode of source electrode amplifier tube Ms is grounded.
Further, in specific implementation process, the structure base of sub-circuit 101 is adjusted in above-mentioned existing differential amplification multiple
On plinth, feedback circuit can be increased to improve the equivalent transconductance of grid amplifier tube Mg, in the performance for not influencing to have circuit
Under the premise of, reduce the power consumption of grid amplifier tube Mg.Specifically, 50 ohm of input impedance, needs grid amplifier tube Mg to have
The mutual conductance (gm) of 20mA；So, if the gain of feedback circuit is A, the mutual conductance (gm) of 20mA/ (1+A) is only needed, such as work as gain
When A is 4, then the mutual conductance (gm) of 4mA is only needed, reduces the power consumption of grid amplifier tube Mg.
It should be pointed out that in fig. 2, source electrode amplifier tube Ms, the 3rd resistor R3 and the second capacitance C2 that dotted line frame is confined
Three's generally changing cell 102.Specifically, referring to FIG. 3, source electrode amplifier tube Ms include k NMOS unit (Ms1~
Msk), wherein k is positive integer；When the size of grid amplifier tube Mg is the NMOS units of 1 unit area, source electrode amplifier tube
The size of i-th of NMOS units M4i is 2 in Msi-1A unit area, wherein i is the integer more than or equal to 1 and less than or equal to k.
Specifically, in Fig. 3 the size of the 1st NMOS units Ms1 be 1 unit area, the 2nd NMOS units Ms2 size be 2 lists
Plane product ..., the size of k-th NMOS units Msk be 2k-1A unit area.
In fig. 2, the common connecting point of the first capacitance C1, grid amplifier tube Mg and first tri- devices of inductance Lext are demarcated
For A, the tie point of the source electrode of changing cell 102 and the second NMOS tube M2 is B；In conjunction with Fig. 3, on circuit structure, source electrode amplification
The drain electrode of k NMOS unit (Ms1~Msk) is connected with B points in pipe Ms, source level is grounded；When i on section [1, k] value
When, the grid of i-th of NMOS units Msi is connected by capacitance C2i with A points, and the grid and electricity of i-th of NMOS units Msi are demarcated
The tie point held on the connecting line of C2i is A1i, and the grid of i-th of NMOS units Msi also passes through point A1i and resistance R3i phases
Even, and further it is connected to third bias voltage input VB3 or 0V voltage.According to different gain requirements, selected based on control bit
The grid of i-th of NMOS units Msi of control of selecting property is connected with third bias voltage input VB3 or 0V voltage, wherein when
When the grid of i NMOS units Msi is connected with third bias voltage input VB3, NMOS units conducting, at this point, source electrode is put
Big pipe Ms is all NMOS units in the conduction state in source electrode amplifier tube Ms relative to the size multiple of grid amplifier tube Mg
Unit area summation.
In specific implementation process, referring to FIG. 4, by taking source electrode amplifier tube Ms includes 4 NMOS units as an example, source electrode is put
The size of NMOS units (Ms1~Ms4) is respectively 1,2,4,8 unit area in big pipe Ms.When NMOS units Ms3 grid with
When third bias voltage input VB3 connects and accesses bias voltage, the grid of other NMOS units accesses 0V voltages, source electrode
Amplifier tube Ms is 2 relative to the size multiple of grid amplifier tube Mg3-1=4；When the grid and third of NMOS units Ms1, Ms3 are inclined
When setting that voltage input end VB3 connects and access bias voltage, the grid of other NMOS units accesses 0V voltages, source electrode amplifier tube
Ms is 2 relative to the size multiple of grid amplifier tube Mg1-1+23-1=5；The rest may be inferred for other situations, no longer repeats one by one here.
Further, in specific implementation process, the second NMOS tube M2 includes multiple NMOS units, and the second NMOS tube M2's is interior
Portion's structure is similar with source electrode amplifier tube Ms, no longer repeats one by one here.When source electrode amplifier tube Ms is relative to grid amplifier tube Mg's
When size multiple is conditioned, the NMOS units of different numbers in the second NMOS tube M2 are connected to by selection, described in corresponding adjust
Size multiples of the second NMOS tube M2 relative to the first NMOS tube M1.Specifically, the second NMOS tube M2 is relative to first
The size multiple of NMOS tube M1 is identical relative to the size multiple of grid amplifier tube Mg as source electrode amplifier tube Ms；I.e. when source electrode amplifies
Pipe Ms is N (N is natural number) relative to the size multiple of grid amplifier tube Mg, and the second NMOS tube M2 is relative to the first NMOS tube M1
Size multiple also be N.
Further, first resistor R1 is adjustable resistance；When sizes times of the source electrode amplifier tube Ms relative to grid amplifier tube Mg
When number is conditioned, the corresponding resistance multiple for adjusting first resistor R1 relative to second resistance R2.Specifically, first resistor R1 is opposite
In the resistance multiple of second resistance R2 be inverses of the source electrode amplifier tube Ms relative to the size multiple of grid amplifier tube Mg；Work as source
Pole amplifier tube Ms is N (N is natural number) relative to the size multiple of grid amplifier tube Mg, and first resistor R1 is relative to second resistance
The resistance multiple of R2 is 1/N.
In single-turn difference amplification grade circuit 100, due to its positive output signal (signal exported from port OUT1+)
The product of mutual conductance and first resistor R1 that gain amplifier is grid amplifier tube Mg, the reverse signal (letter exported from port OUT1-
Number) gain amplifier be source electrode amplifier tube Ms mutual conductance and second resistance R2 product.Pass through above-mentioned first NMOS tube M1, second
NMOS tube M2, grid amplifier tube Mg, the dimension scale design of source electrode amplifier tube Ms and first resistor R1 and second resistance R2
Resistance value designs, it is ensured that equal in the difference output end signal amplification factor of single-turn difference amplification grade circuit 100.Further, when
Tune up source electrode amplifier tube Ms relative to grid amplifier tube Mg size multiple, tune up the second NMOS tube M2 relative to the first NMOS tube
The size multiple of M1 and when tuning up resistance multiples of the second resistance R2 relative to first resistor R1, can be single-turn difference amplifying stage
The late-class circuit of circuit 100 provides the differential input signal of enough large gains.Since late-class circuit is equivalent (i.e. single to whole system
The system that slip amplification grade circuit 100 and following stage circuit are constituted) noise factor, the increasing with single-turn difference amplification grade circuit 100
Benefit is inversely proportional, therefore, when single-turn difference amplification grade circuit 100 provides the differential input signal of enough large gains for late-class circuit,
The noise factor of following stage circuit equivalent to whole system is reduced, that is, the noise for inhibiting late-class circuit to generate.
In order to further increase low-noise amplifier differential output signal balance, please refer to Fig. 5 A, the low noise
Acoustic amplifier further includes：Second level buffer circuit 300；
Second level buffer circuit 300 include the second differential input end (In3+, In3-) and third difference output end (OUT3+,
OUT3-)；Second differential input end (In3+, In3-) is connect with the second difference output end (OUT2+, OUT2-)；
Second level buffer circuit 300 is used to carry out the second differential signal that first order buffer circuit 200 exports further
Filter amplifying processing and phase amplitude adjustment, to obtain third differential signal, and by third difference output end (OUT3+,
OUT3- the third differential signal) is exported；
Second difference output end (OUT2+, OUT2-) and third difference output end (OUT3+, OUT3-) are used as the low noise
Two output ports of acoustic amplifier, for selectively exporting second differential signal and the third differential signal conduct
Differential output signal (the S of the low-noise amplifierout+, Sout-)。
In specific implementation process, referring still to Fig. 5 A, first order buffer circuit 200 includes：High-pass filter 201 and complete
Difference amplifier 202；The differential input end of high-pass filter 201 connects the first differential input end (In2+, In2-), high-pass filtering
The differential input end of the difference output end connection fully-differential amplifier 202 of device 201；The difference output end of fully-differential amplifier 202
Connect the second difference output end (OUT2+, OUT2-).
Further, referring to FIG. 6, high-pass filter 201 includes：Third capacitance C3, the 4th capacitance C4, the 4th resistance R4,
5th resistance R5 and the 4th bias voltage input VB4；One end of third capacitance C3 and the 4th capacitance C4 are for inputting described the
One differential signal, the other end of third capacitance C3 connect one end of the 4th resistance R4, also connect with fully-differential amplifier 202, the
The other end of four capacitance C4 connects one end of the 5th resistance R5, also connect with fully-differential amplifier 202, the 4th resistance R4 and the 5th
The resistance R5 other ends are connected and are connect with the 4th bias voltage input VB4.
Referring still to Fig. 6, fully-differential amplifier 202 includes：Second source input terminal VDD2, the 6th resistance R6, the 7th electricity
Hinder R7, third NMOS tube M3, the 4th NMOS tube M4, the 5th NMOS tube M5 and the 5th bias voltage input VB5；
Second source input terminal VDD2 is respectively connected to one end of the 6th resistance R6 and the 7th resistance R7, the 6th resistance R6 and
The other end of 7th resistance R7 is separately connected the drain electrode of third NMOS tube M3 and the 4th NMOS tube M4；The grid of third NMOS tube M3
Connect third capacitance C3；The grid of 4th NMOS tube M4 connects the 4th capacitance C4；The source electrode connection the 5th of third NMOS tube M3
The drain electrode of NMOS tube M5；The source electrode of 4th NMOS tube M4 connects the drain electrode of the 5th NMOS tube M5；5th bias voltage input VB5
Connect the grid of the 5th NMOS tube M5；The source electrode of 5th NMOS tube M5 is grounded.
Further, Fig. 5 A and Fig. 7, the knot of the structure and first order buffer circuit 200 of second level buffer circuit 300 are please referred to
Structure is identical, specifically, second level buffer circuit 300 includes：High-pass filter 301 and fully-differential amplifier 302；High-pass filter
301 differential input end connects the second differential input end (In3+, In3-), and the difference output end connection of high-pass filter 301 is complete
The differential input end of difference amplifier 302；The difference output end connection third difference output end (OUT3 of fully-differential amplifier 302
+、OUT3-).High-pass filter 301 includes：5th capacitance C5, the 6th capacitance C6, the 8th resistance R8, the 9th resistance R9 and the 6th
Bias voltage input VB6；Fully-differential amplifier 302 includes：Third power input VDD3, the tenth resistance R10, the 11st electricity
Hinder R11, the 6th NMOS tube M6, the 7th NMOS tube M7, the 8th NMOS tube M8 and the 7th bias voltage input VB7.
In specific implementation process, the operation principle of low-noise amplifier shown in Fig. 5 A, Fig. 6, Fig. 7 is as follows：
The single ended signal S that antenna receivesInInto single-turn difference amplifying circuit 100, wherein single-turn difference amplifying circuit 100
In grid amplifier tube Mg make 50 ohm of input resistant matching pipe, signal is amplified, and phase and single ended signal
SInIt is identical.Source electrode amplifier tube Ms is to single ended signal SInPhase carry out reversed, and assist eliminating making an uproar for grid amplifier tube Mg
Sonic system number and nonlinear terms.The circuit output port of single-turn difference amplifying circuit 100 use two-stage buffer circuit, buffer circuit by
High-pass filter and fully-differential amplifier two parts composition.High-pass filter (201,301) is by capacitance (C3, C4, C5, C6)
It is constituted with supplying resistance (R4, R5, R8, R9), for improving gain flatness；Fully-differential amplifier (202,302) is for inhibiting
Output signal imbalance ingredient, ensures the symmetry of output signal.
Further, referring still to Fig. 5 A, the low-noise amplifier further includes：Switch selection circuit 400；
Switch selection circuit 400 and the second difference output end (OUT2+, OUT2-) and third difference output end (OUT3+,
OUT3- it) connects, for selecting second differential signal or the third differential signal as described in when on off state changes
The differential output signal of low-noise amplifier.
Specifically, please referring to Fig. 5 B, switch selection circuit 400 includes：First switch K1, second switch K2, third switch
K3 and the 4th switch K4.Difference output end (the OUT2 in first order buffer circuit 200 is arranged in first switch K1 and second switch K2
+, OUT2-) outlet line on, for controlling whether the differential output signal using first order buffer circuit 200 as low noise
The final output signal of amplifier is exported；Third switch K3 and the 4th switch K4 are arranged in second level buffer circuit 300
On the outlet line of difference output end (OUT3+, OUT3-), for controlling whether the difference output of second level buffer circuit 300
Signal is exported as the final output signal of low-noise amplifier.
When first, second switch K1, K2 is closed and third, the 4th switch K3, K4 are disconnected, from first order buffer circuit
The differential signal of 200 outputs is exported as the final output signal of low-noise amplifier.As first and second switch K1, K2
It disconnects and when third and fourth switch K3, K4 is closed, will pass through the from the differential signal of the output of second level buffer circuit 200
Level 2 buffering circuit 300 is further amplified and phase and amplitude adjustment, the difference exported from second level buffer circuit 300
Sub-signal is exported as the final output signal of low-noise amplifier.It is exported from difference output end (OUT2+, OUT2-)
Differential signal is than the gain from the few circuit that have passed through first-level buffer circuit, therefore obtain of difference output end (OUT3+, OUT3-)
It is different.Therefore first, second, third, fourth switch K1, K2, K3, K4 can be further by controlling the output of differential signal
Control and regulation circuit gain.
It is, of course, also possible to by other means come to select the output signal of low-noise amplifier be from difference output end
(OUT2+, OUT2-) is exported or is exported from difference output end (OUT3+, OUT3-), for example, being manually selected which by user
One differential signal outputs is connected to external circuit or other possible modes existing in the prior art.
It should be pointed out that in the present embodiment, as first, second switch K1, K2 disconnection, third, the 4th switch K3, K4
When closure, second level buffer circuit 300 by the output difference signal of first order buffer circuit 200 carry out further amplification with
And phase and amplitude adjustment, the differential signal of acquisition are used as low-noise amplifier from difference output end (OUT3+, OUT3-) output
Final output signal.Input signal by two-stage buffer circuit adjustment after phase difference within 1 °, amplitude difference 1dB with
It is interior, there is good symmetry.
In addition, in order to ensure that the linearity of circuit is not deteriorated, it, can be by adjusting first order buffering incorporated by reference to Fig. 6 and Fig. 7
The size of the bias voltage of 5th bias voltage input VB5 inputs of circuit 200, to adjust first order buffer circuit 200
The size for flowing through the tail current I1 of the 5th NMOS tube M5, the 7th bias voltage by adjusting second level buffer circuit 300 input
The size for holding the bias voltage of VB7 inputs, to adjust the tail current I2 for flowing through the 8th NMOS tube M8 of second level buffer circuit 300
Size, and make tail current I2 be more than tail current I1, to improve the linearity of circuit.
In conclusion following technique effect at least may be implemented by using the application low-noise amplifier：
1) the NMOS unit of in source electrode amplifier tube different numbers is connected to by selection in single-turn difference amplifying circuit, to adjust
Size multiple of the source electrode amplifier tube relative to the grid amplifier tube is stated, and then adjusts the differential amplification multiple and adjusts sub-circuit
To the differential amplification multiple of the single ended signal, the first differential signal of different amplification is obtained；Wherein, when source electrode is put
The size of big pipe is N times (N is random natural number) of grid amplifier tube, and bias voltage is equal, and first resistor is second resistance
N times, can ensure so equal in the forward signal of difference output end and the amplification factor of reverse signal, and grid be amplified
The noise cancellation that pipe generates；Enough gains can be provided as needed simultaneously, come the noise for inhibiting late-class circuit to generate.Into one
Step, enhanced processing and phase width are filtered by the first order buffer circuit of low-noise amplifier to first differential signal
Degree adjustment, to obtain the second differential signal, using when needed as the final output of the low-noise amplifier.It efficiently solves
In the prior art single ended input both-end output LNA signal gain amplifier it is insufficient and non-adjustable and export differential signal not
The technical issues of balance, realizes the differential amplification processing that adjustable gain is carried out to the single-ended signal of input, and by buffering
The preferable differential signal of balance is exported after processing of circuit.
2) by adding second level buffer circuit after first order buffer circuit, to first order buffer circuit output
Differential signal carries out further filter amplifying processing and phase amplitude adjustment, to further increase the balance of differential output signal
Degree.
3) defeated to select by the way that switch selection circuit is arranged on the basis of low-noise amplifier has two-stage buffer circuit
Go out final output signal or output second level buffering of the differential output signal as low-noise amplifier of first order buffer circuit
Final output signal of the differential output signal of circuit as low-noise amplifier, realizing can be flexibly defeated according to actual needs
Go out different gain amplifiers, the different degree of balance differential signal.
4) on the basis of low-noise amplifier has two-stage buffer circuit, by adjusting the biased electrical of two-stage buffer circuit
It presses to adjust the tail current size of two-stage buffer circuit, so that the tail current of rear class buffer circuit is more than the tail of prime buffer circuit
Electric current, to improve the linearity of entire circuit.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications can be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of low-noise amplifier of the adjustable gain of single ended input both-end output, which is characterized in that including：Single-turn difference is amplified
Circuit and first order buffer circuit；
The single-turn difference amplifying circuit includes that the single ended inputs being sequentially communicated, differential amplification multiple adjusting sub-circuit and first are poor
It includes the first differential input end and the second difference output end to divide output end, the first order buffer circuit；
The single-turn difference amplifying circuit is used to receive single ended signal by the single ended inputs, and is put by the difference
Big multiple adjusts sub-circuit and carries out differential amplification to the single ended signal, to obtain the first differential signal, and by described
First difference output end exports first differential signal；
Wherein, the differential amplification multiple adjusting sub-circuit includes：The grid amplifier tube being connect with the single ended inputs, with institute
The source electrode amplifier tube of grid amplifier tube connection is stated, the connect with the grid amplifier tube and the source electrode amplifier tube is corresponded
One resistance and second resistance；The source electrode amplifier tube includes multiple NMOS units, is connected in the source electrode amplifier tube by selecting
The NMOS units of different numbers to adjust size multiple of the source electrode amplifier tube relative to the grid amplifier tube, and then are adjusted
The differential amplification multiple that the differential amplification multiple adjusts sub-circuit to the single ended signal is saved, different amplification is obtained
The first differential signal；
The first order buffer circuit is used to receive first differential signal by first differential input end, and to described
First differential signal is filtered enhanced processing and phase amplitude adjustment, to obtain the second differential signal, and passes through described second
Difference output end exports second differential signal.
2. the low-noise amplifier of the adjustable gain of single ended input both-end output as described in claim 1, which is characterized in that institute
Stating differential amplification multiple adjusting sub-circuit further includes：
Correspond the first NMOS tube and the second NMOS tube being connect with the grid amplifier tube and the source electrode amplifier tube；Its
In, the grid amplifier tube is connect by first NMOS tube with the first resistor, and the source electrode amplifier tube passes through described
Second NMOS tube is connect with the second resistance；
Second NMOS tube includes multiple NMOS units, when size of the source electrode amplifier tube relative to the grid amplifier tube
When multiple is conditioned, by selecting to be connected to the NMOS units of different numbers in second NMOS tube, described the is adjusted with corresponding
Size multiple of two NMOS tubes relative to first NMOS tube.
3. the low-noise amplifier of the adjustable gain of single ended input both-end output as claimed in claim 1 or 2, feature exist
In the first resistor is adjustable resistance；When the source electrode amplifier tube is adjusted relative to the size multiple of the grid amplifier tube
When section, the corresponding resistance multiple for adjusting the first resistor relative to the second resistance.
4. a kind of low-noise amplifier of the adjustable gain of single ended input both-end output according to claim 1, feature
It is, the differential amplification multiple adjusts sub-circuit and further includes：First power input, the first bias voltage input, second
Bias voltage input, third bias voltage input, 3rd resistor, the first capacitance, the second capacitance and the first inductance；
First power input is respectively connected to one end of the first resistor and the second resistance, the first resistor
The other end connect the drain electrode of the first NMOS tube, the other end of the second resistance connects the drain electrode of the second NMOS tube；First
The grid of NMOS tube is connect with first bias voltage input, for passing through first bias voltage input input the
One bias voltage；The grid of second NMOS tube is connect with second bias voltage input, is biased for passing through described second
Voltage input end inputs the second bias voltage；The source electrode of first NMOS tube connects the drain electrode of the grid amplifier tube；2nd NMOS
The source electrode of pipe connects the drain electrode of the source electrode amplifier tube；The grid of the grid amplifier tube connects the third bias voltage input
End；The grid of the source electrode amplifier tube connects the third bias voltage input or 0V voltages by 3rd resistor；The grid
The source electrode of pole amplifier tube is separately connected the one of one end of first capacitance, one end of second capacitance and first inductance
End, the other end of first capacitance is for inputting the single ended signal, described in the other end connection of second capacitance
The grid of source electrode amplifier tube, the other end ground connection of first inductance；The source electrode of the source electrode amplifier tube is grounded.
5. the low-noise amplifier of the adjustable gain of single ended input both-end output as described in claim 1, which is characterized in that institute
Stating low-noise amplifier further includes：Second level buffer circuit；
The second level buffer circuit includes the second differential input end and third difference output end；Second differential input end with
The second difference output end connection；
The second level buffer circuit is used to carry out the second differential signal that the first order buffer circuit exports further
Filter amplifying processing and phase amplitude adjustment to obtain third differential signal, and export institute by the third difference output end
State third differential signal；
Two output ports of second difference output end and the third difference output end as the low-noise amplifier,
Differential output signal for selectively exporting the low-noise amplifier.
6. the low-noise amplifier of the adjustable gain of single ended input both-end output as claimed in claim 5, which is characterized in that institute
Stating low-noise amplifier further includes：Switch selection circuit；
The switch selection circuit is connect with second difference output end and the third difference output end, in switch shape
State selects the difference output of second differential signal or the third differential signal as the low-noise amplifier when changing
Signal.
7. a kind of low-noise amplifier of the adjustable gain of single ended input both-end output according to claim 1, feature
It is, the first order buffer circuit includes：High-pass filter and fully-differential amplifier；The Differential Input of the high-pass filter
End connects first differential input end, and the difference output end of the high-pass filter connects the difference of the fully-differential amplifier
Input terminal；The difference output end of the fully-differential amplifier connects second difference output end.
8. a kind of low-noise amplifier of the adjustable gain of single ended input both-end output according to claim 7, feature
It is, the high-pass filter includes：Third capacitance, the 4th capacitance, the 4th resistance, the 5th resistance and the input of the 4th bias voltage
End；One end of the third capacitance and the 4th capacitance for inputting first differential signal, the third capacitance it is another
One end connects one end of the 4th resistance, also connect with the fully-differential amplifier, the other end connection of the 4th capacitance
One end of 5th resistance is also connect with the fully-differential amplifier, and the 4th resistance and the 5th resistance other end are connected
And it is connect with the 4th bias voltage input.
9. a kind of low-noise amplifier of the adjustable gain of single ended input both-end output according to claim 8, feature
It is, the fully-differential amplifier includes：Second source input terminal, the 6th resistance, the 7th resistance, third NMOS tube, the 4th
NMOS tube, the 5th NMOS tube and the 5th bias voltage input；
The second source input terminal is respectively connected to one end of the 6th resistance and the 7th resistance, the 6th resistance
The drain electrode of the third NMOS tube and the 4th NMOS tube is separately connected with the other end of the 7th resistance；The third
The grid of NMOS tube connects the third capacitance；The grid of 4th NMOS tube connects the 4th capacitance；The third
The source electrode of NMOS tube connects the drain electrode of the 5th NMOS tube；The source electrode of 4th NMOS tube connects the 5th NMOS tube
Drain electrode；5th bias voltage input connects the grid of the 5th NMOS tube；The source electrode of 5th NMOS tube is grounded.
10. a kind of low-noise amplifier of the adjustable gain of single ended input both-end output according to claim 5, feature
It is, the structure of the second level buffer circuit is identical as the structure of first order buffer circuit.
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| CN107666289B (en) * | 2017-09-14 | 2020-12-01 | 西安电子科技大学昆山创新研究院 | High Gain Large Linear Dynamic Range Transimpedance Amplifier |
| CN107749744A (en) * | 2017-10-27 | 2018-03-02 | 天津大学 | A kind of single-ended transfer difference trans-impedance amplifier based on CMOS technology |
| CN108259704B (en) * | 2018-03-23 | 2024-04-30 | 深圳市豪恩汽车电子装备股份有限公司 | Video output circuit of vehicle-mounted camera |
| CN111030614B (en) * | 2019-12-11 | 2023-10-27 | 电子科技大学 | A transconductance-enhanced millimeter-wave low-noise amplifier |
| CN114039556B (en) * | 2021-09-30 | 2022-12-16 | 锐磐微电子科技(上海)有限公司 | Radio frequency power amplifier and radio frequency power amplification system |
| CN115664354B (en) * | 2022-12-28 | 2023-04-21 | 广州慧智微电子股份有限公司 | Differential amplifying circuit |
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