CN105979707B - A kind of line layer is without copper area recognizing method and system - Google Patents

Abstract

The invention discloses a method and system for identifying a copper-free region of a circuit layer. The method for identifying a copper-free region of a circuit layer includes the following steps: generating a circuit layer region and copper plating in the circuit layer region according to a circuit graphic file of the circuit layer layer area; a plurality of substrate areas in the circuit layer area are determined according to the circuit layer area and the copper plating layer area, wherein a plurality of the base material areas and the copper plating layer area are merged into the Circuit layer area; determine whether the area of the base material area is larger than a first preset area, and determine the base material area larger than the first preset area as a copper-free area; determine the area of the base material as a copper-free area The substrate area and the circuit layer area are displayed. The invention can quickly and accurately identify whether the line layer has a copper-free area, and production personnel can take corresponding measures for the line layer with the copper-free area.

Description

A method and system for identifying a copper-free area of a circuit layer

technical field

The invention relates to the technical field of circuit board production and manufacturing, in particular to a method and system for identifying a copper-free region of a circuit layer.

Background technique

The copper-free area refers to the closed or semi-closed copper-free area surrounded by the copper skin in the circuit layer and with an area of more than 2.1 square inches (the specific defined area can be set according to the actual process production capacity of the actual circuit board). The copper-free area is concave in the circuit board layer, and the colloid in the copper-free area is easy to lose. In this way, during the lamination process of the circuit board, the copper-free area is likely to cause glue shortage between the circuit boards, which in turn leads to quality problems such as white spots, air bubbles, and copper wrinkling on the laminated circuit board. In the process of circuit board manufacturing, the copper-free area of each circuit layer is often artificially identified according to the circuit graphic file, and corresponding production measures are made according to the copper-free area. However, when circuit boards are produced in batches, there are many circuit elements in each circuit layer of the circuit board, errors are likely to occur in human identification methods, copper-free areas in the circuit layer are easy to miss, and the product quality pass rate of circuit boards is low.

Contents of the invention

Based on this, the present invention overcomes the defects of the prior art and provides a method and system for identifying copper-free areas in the circuit layer, which can easily identify the copper-free areas in the circuit layer and improve the production efficiency of circuit boards.

Its technical scheme is as follows: a method for identifying a copper-free region of a circuit layer, comprising the steps of: generating a circuit layer region and a copper plated layer region in the circuit layer region according to a circuit graphic file of the circuit layer; The copper plated layer area determines a plurality of base material areas in the circuit layer area, wherein a plurality of the base material areas and the copper plated layer area are merged into the circuit layer area; the base material area is judged Whether the area of the substrate is greater than the first preset area, the substrate area greater than the first preset area is determined as a copper-free area; the substrate area determined as a copper-free area is compared with the circuit layer area show.

A circuit layer copper-free area identification system, comprising: a first generation module, the first generation module is used to generate a line layer area and a copper plating layer area in the line layer area according to a circuit pattern file of the line layer; A display module, the first display module is used to display the substrate area determined as the copper-free area and the circuit layer area; an inversion module, the inversion module is used to display the circuit layer area according to the Determining a plurality of substrate regions in the circuit layer region with the copper plating layer region; a judging module, the judging module is used to judge whether the area of the substrate region is greater than a first preset area; and an identification module, The identification module is used to determine the area of the base material larger than the first preset area as a copper-free area.

In one of the embodiments, the step of judging whether the area of the substrate area is greater than a first preset area includes the step of: obtaining the center point of the substrate area, and dividing the edge of the substrate area by the center The first preset area is reduced inwardly with the point as the center; the substrate area that is not enough to reduce the first preset area is shielded from the circuit layer area, and after the first preset area is reduced The edge of the base material area expands a second preset area outward with the center point as the center, and generates a copper-free identification area.

In one of the embodiments, the step of determining a plurality of substrate regions in the circuit layer region according to the circuit layer region and the copper plating layer region includes the step of: The copper layer area is shielded, and the remaining areas in the circuit layer area are displayed, and the remaining areas are multiple substrate areas.

In one of the embodiments, the step of judging whether the area of the substrate region is greater than a first preset area includes the steps of: calculating the area of the substrate region; calculating the area of the substrate region with the first Preset areas for comparison.

In one of the embodiments, after the step of determining the substrate area larger than the first preset area as a copper-free area, the step further includes: according to the circuit pattern file of the copper-free area in the circuit layer The location in generates copper-free area identification points.

In one of the embodiments, the judgment module includes an acquisition module, an area reduction module, a first shielding module and a second generation module, the acquisition module is used to obtain the center point of the substrate area, and the area reduction module The edge of the base material area is used to reduce the first preset area inwardly around the center point, and the first shielding module is used to reduce the base area that is not enough to reduce the first preset area. The material area is shielded from the circuit layer area, and the second generation module is used to expand the edge of the base material area after the first preset area is reduced, centering on the center point outward by a second Preset the area and generate a copper-free marking area.

In one of the embodiments, the inverting module includes a second shielding module and a second display module, the second shielding module is used to shield the copper plating layer region in the circuit layer region, the The second display module is used for displaying multiple substrate regions in the circuit layer region.

In one of the embodiments, the judgment module includes an area calculation module and an area comparison module, the area calculation module is used to calculate the area of the substrate area, and the area comparison module is used to calculate the area of the substrate area The area is compared with the first preset area.

In one of the embodiments, the line layer copper-free area identification system further includes a third generation module, the third generation module is used to generate Copper-free area identification point.

Principle of the present invention, effect are further described below in conjunction with above-mentioned technical scheme:

In the method for identifying the copper-free area of the circuit layer, firstly obtain a plurality of substrate layer regions through the circuit layer region and the copper plating layer region, and then determine the substrate region with an area larger than the first preset area as the copper-free region, and determine Substrate and wiring layer regions are shown for copper-free regions. In this way, the present invention can quickly and accurately identify whether the circuit layer has a copper-free area, and production personnel can take corresponding measures for the circuit layer with a copper-free area.

Description of drawings

FIG. 1 is a flow chart 1 of a method for identifying a copper-free area of a line layer according to Embodiment 1 of the present invention;

FIG. 2 is a second flow chart of the method for identifying a copper-free area of a line layer according to Embodiment 2 of the present invention;

FIG. 3 is a flow chart three of the method for identifying a copper-free area of a line layer according to Embodiment 3 of the present invention;

Fig. 4 is a schematic structural diagram of the circuit layer copper-free area identification system according to the embodiment of the present invention;

5 is a schematic diagram of the copper-plated layer region in the circuit layer region in the method for identifying the copper-free region of the circuit layer according to the embodiment of the present invention;

FIG. 6 is a schematic diagram of an inverted copper-plated layer region and a substrate region in the method for identifying a copper-free region of a circuit layer according to an embodiment of the present invention;

7 is a schematic diagram of generating a copper-free area in a substrate area in the method for identifying a copper-free area of a circuit layer according to an embodiment of the present invention.

Explanation of reference signs:

10. Circuit layer area, 11. Copper plated layer area, 12. Substrate area, 121. Copper-free area, 122. Through-hole area, 123. Copper-free identification area, 21. First generation module, 22. First display module, 23, an inversion module, 24, a judgment module, and 25, an identification module.

Detailed ways

Embodiments of the present invention are described in detail below:

Embodiment one

As shown in FIG. 1, the method for identifying a copper-free area of a circuit layer according to an embodiment of the present invention includes the following steps:

S101, generate the circuit layer region 10 and the copper plating layer region 11 in the circuit layer region 10 according to the circuit pattern file of the circuit layer, and display the copper plating layer region 11 in the circuit layer region 10 (please See Figure 5);

S102. Determine a plurality of substrate regions 12 in the circuit layer region 10 according to the circuit layer region 10 and the copper plating layer region 11, wherein a plurality of the substrate regions 12 and the copper plating layer region 11 are assembled into the circuit layer area 10; the copper-plated layer area 11 has a copper-plated layer, and the substrate area 12 includes a copper-free area 121 and a through-hole area 122, and neither the copper-free area 121 nor the through-hole area 122 has a copper-plated layer. The base material region 12 is distinguished from the copper-plated layer region 11 by whether or not it has a copper-plated layer.

S103 , judging whether the area of the substrate region 12 is larger than a first preset area, and determining the substrate region 12 larger than the first preset area as the copper-free region 121 . Wherein, the first preset area is determined according to the area defined by the copper-free region 121, if the copper-free region 121 is defined as the substrate region 12 with an area larger than 2 square inches, then the first preset area is 2 square inches;

S104 , displaying the substrate region 12 and the circuit layer region 10 determined as the copper-free region 121 .

In the method for identifying copper-free areas of the circuit layer described above, a plurality of substrate layer regions are first obtained through the circuit layer region 10 and the copper-plated layer region 11, and then the substrate region 12 with an area larger than the first preset area is determined as the copper-free region 121 , and display the substrate region 12 and the wiring layer region 10 determined as the copper-free region 121 . In this way, the present invention can quickly and accurately identify whether the circuit layer has the copper-free region 121 , and the production personnel can take corresponding measures for the circuit layer with the copper-free region 121 .

Embodiment two

As shown in FIG. 2, the method for identifying a copper-free area of a circuit layer according to an embodiment of the present invention includes the following steps:

S201. Generate the circuit layer region 10 and the copper plating layer region 11 in the circuit layer region 10 according to the circuit pattern file of the circuit layer, and display the copper plating layer region 11 in the circuit layer region 10 (please See Figure 5);

S202. Shield the copper plating layer region 11 in the circuit layer region 10, and display the remaining regions in the circuit layer region 10, and the remaining regions are a plurality of substrate regions 12 ( Please refer to Figure 6);

S203. Obtain the center point of the base material region 12, and reduce the edge of the base material region 12 inwardly to a first preset area around the center point; wherein, the first preset area is based on the copper-free region 121 The defined area is determined. If the copper-free area 121 is defined as the substrate area 12 with an area larger than 2 square inches, the first preset area is 2 square inches.

S204. Shield the substrate region 12 that is not enough to reduce the first preset area from the circuit layer region 10; the area of the through hole region 122 is smaller than the first preset area and not enough to reduce the first preset area. With a predetermined area, the via area 122 is all shielded. The area of the copper-free region 121 is greater than the first predetermined area, and the substrate region 12 that can be used to reduce the first predetermined area is the copper-free region 121 .

S205, expand the edge of the base material region 12 after reducing the first preset area to a second preset area centered on the center point, and generate a copper-free logo area 123 (see FIG. 7 ) . The size of the second preset area is different from the first preset area, and can be set to be smaller than the first preset area, so that the copper-free identification area 123 generated in the circuit layer area 10 is located inside the copper-free area 121, without The copper identification area 123 can be used to identify the substrate area 12 as the copper-free area 121 and can be distinguished from the copper-free area 121 .

S205 , displaying the substrate region 12 and the circuit layer region 10 determined as the copper-free region 121 .

Embodiment three

As shown in FIG. 3, the method for identifying a copper-free region of a circuit layer according to an embodiment of the present invention includes the following steps:

S301. Generate the circuit layer area 10 and the copper plated layer area 11 in the circuit layer area 10 according to the circuit pattern file of the circuit layer, and display the copper plated layer area 11 in the circuit layer area 10 (please See Figure 5);

S302. Determine a plurality of substrate regions 12 in the circuit layer region 10 according to the circuit layer region 10 and the copper plating layer region 11, wherein a plurality of the substrate regions 12 and the copper plating layer region 11 are assembled into the circuit layer area 10; the copper-plated layer area 11 has a copper-plated layer, and the substrate area 12 includes a copper-free area 121 and a through-hole area 122, and neither the copper-free area 121 nor the through-hole area 122 has a copper-plated layer. The base material region 12 is distinguished from the copper-plated layer region 11 by whether or not it has a copper-plated layer.

S303. Calculate the area of the substrate region 12;

S304. Comparing the area of the substrate region 12 with the first preset area; wherein, the first preset area is determined according to the area defined by the copper-free region 121, if the copper-free region 121 is defined as having an area greater than For a substrate area 12 of 2 square inches, the first predetermined area is 2 square inches.

S305. Generate identification points for the copper-free region 121 in the substrate region 12 with an area larger than the first preset area. The copper-free area 121 identification point is used to mark the copper-free area 121 in the circuit layer area 10, and the production personnel carry out the copper-free area 121 in the circuit layer area 10 according to the copper-free area 121 identification point marked in the circuit layer area 10. Identify and take corresponding measures for the circuit layer with copper-free region 121.

S306 , displaying the substrate region 12 and the circuit layer region 10 determined as the copper-free region 121 .

The difference between Embodiment 3 and Embodiment 2 lies in steps S303-S305. Embodiment 3 directly calculates the area of each substrate region 12 and judges whether the area of each substrate region 12 is greater than the first preset area, which will be larger than the first predetermined area. A substrate region 12 with a preset area is determined as the copper-free region 121 , and identification points for the copper-free region 121 are added in the corresponding substrate region 12 .

Please refer to FIG. 4 , the system for identifying the copper-free region 121 of the circuit layer according to the embodiment of the present invention includes: a first generation module 21 , an inversion module 23 , a judgment module 24 , an identification module 25 and a first display module 22 . The first generating module 21 is used to generate the circuit layer area 10 and the copper plating layer area 11 in the circuit layer area 10 according to the circuit pattern file of the circuit layer. The inversion module 23 is used for determining a plurality of substrate regions 12 in the circuit layer region 10 according to the circuit layer region 10 and the copper plating layer region 11 . The judging module 24 is used for judging whether the area of the substrate region 12 is larger than a first preset area. The identifying module 25 is configured to determine the substrate area 12 larger than the first preset area as the copper-free area 121 . The first display module 22 is used for displaying the substrate area 12 and the circuit layer area 10 determined as the copper-free area 121 .

The above identification system for the copper-free region 121 of the circuit layer obtains the circuit layer region 10 and the copper-plated layer region 11 through the first generating module 21, and then passes the circuit layer region 10 and the copper-plated layer region 11 through the inversion module 23 to obtain a plurality of basic material layer area, then determine the substrate area 12 with an area greater than the first preset area as the copper-free area 121 by the judging module 24 and the identification module 25, and finally determine the copper-free area 121 by the first display module 22. The substrate area 12 is displayed with the circuit layer area 10 . In this way, the present invention can quickly and accurately identify whether the circuit layer has the copper-free region 121 , and the production personnel can take corresponding measures for the circuit layer with the copper-free region 121 .

In one of the embodiments, the judgment module 24 includes an acquisition module, an area reduction module, a first mask module and a second generation module. The obtaining module is used to obtain the center point of the substrate area 12 . The area reduction module is used to reduce the edge of the base material region 12 inwardly with the center point as the center by a first preset area. The first shielding module is used for shielding the substrate area 12 which is not enough to reduce the first preset area from the circuit layer area 10 . The second generation module is used to expand the edge of the substrate region 12 after reducing the first preset area to a second preset area centered on the center point, and generate a copper-free logo area 123 . The inversion module 23 includes a second shielding module and a second display module. The second shielding module is used to shield the copper plating layer region 11 in the circuit layer region 10, and the second display module is used to shield the plurality of substrates in the circuit layer region 10 Area 12 is displayed.

In another embodiment, the judgment module 24 includes an area calculation module and an area comparison module. The area calculation module is used to calculate the area of the substrate region 12 , and the area comparison module is used to compare the area of the substrate region 12 with the first preset area. The system for identifying the copper-free area 121 of the circuit layer further includes a third generating module. The third generating module is configured to generate identification points of the copper-free area 121 according to the position of the copper-free area 121 in the circuit pattern file of the circuit layer.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. a kind of line layer is without copper area recognizing method, which is characterized in that includes the following steps：

According to the copper facing layer region in the line pattern file generated circuit layer region of line layer and the circuit layer region；

Multiple substrate regions in the circuit layer region are determined according to the circuit layer region and the copper facing layer region, In, multiple substrate regions piece together the circuit layer region with the copper facing layer region；

Judge whether the area of the substrate regions is more than the first preset area, will be greater than the base of first preset area Material region is determined as no copper region；

The substrate regions and the circuit layer region that will determine as no copper region are shown.

2. line layer according to claim 1 is without copper area recognizing method, which is characterized in that described to judge the substrate area Whether the area in domain is more than the first preset area step and includes step：The central point of the substrate regions is obtained, by the base material The edge in region inwardly reduces the first preset area centered on the central point；It will be fewer than and reduce the first default face The long-pending substrate regions are masked from the circuit layer region, will reduce the substrate area after first preset area The edge in domain centered on the central point is expanded the second preset area and generated without copper identified areas outward.

3. line layer according to claim 2 is without copper area recognizing method, which is characterized in that described according to the line layer Region determines that multiple substrate regions steps in the circuit layer region include step with the copper facing layer region：By the circuit The copper facing layer region in layer region is shielded, and remaining region in the circuit layer region is shown, described Remaining region is multiple substrate regions.

4. line layer according to claim 1 is without copper area recognizing method, which is characterized in that described to judge the substrate area Whether the area in domain is more than the first preset area step and includes step：Calculate the area of the substrate regions；By the substrate area The area in domain is compared with first preset area.

5. the line layer according to Claims 1 to 4 any one is without copper area recognizing method, which is characterized in that described to incite somebody to action The substrate regions more than first preset area are determined as further including step after the step of no copper region：It is more than in area Generation is without copper region recognition point in the substrate regions of first preset area.

6. a kind of line layer is without copper region recognition system, which is characterized in that including：

First generation module, first generation module be used for according to the line pattern file generated circuit layer region of line layer with Copper facing layer region in the circuit layer region；

Reversal block, the reversal block are used to determine the line layer according to the circuit layer region and the copper facing layer region Multiple substrate regions in region；

Judgment module, the judgment module are used to judge whether the area of the substrate regions to be more than the first preset area；

Identification module, the substrate regions that the identification module is used to will be greater than first preset area are determined as Wu Tongqu Domain；And

First display module, first display module are used to will determine as the substrate regions in no copper region and the circuit Layer region is shown.

7. line layer according to claim 6 is without copper region recognition system, which is characterized in that the judgment module includes obtaining Modulus block, area reduce module, the first shroud module and the second generation module, and the acquisition module is used to obtain the substrate area The central point in domain, the area reduce module for the edge of the substrate regions inwardly to be reduced centered on the central point First preset area, first shroud module are used to that the substrate regions for reducing first preset area will to be fewer than It is masked from the circuit layer region, second generation module is used to that the base after first preset area will to be reduced The edge in material region centered on the central point is expanded the second preset area and generated without copper identified areas outward.

8. line layer according to claim 6 is without copper region recognition system, which is characterized in that the reversal block includes the Two shroud modules and the second display module, the secondary shielding module are used for the copper plate area in the circuit layer region Domain is shielded, and second display module is used to show multiple substrate regions in the circuit layer region.

9. line layer according to claim 6 is without copper region recognition system, which is characterized in that the judgment module includes face Product computing module and area comparison module, the area calculation module are used to calculate the area of the substrate regions, the area Comparison module is used to the area of the substrate regions and first preset area being compared.

10. the line layer according to claim 6~9 any one is without copper region recognition system, which is characterized in that further includes Third generation module, the third generation module are used for according to the no copper region in the line pattern file of the line layer Position generate without copper region recognition point.