CN105990220A - Interconnection structure and formation method thereof - Google Patents

Abstract

The invention provides an interconnection structure and a forming method thereof. The method includes: forming a buffer layer with a density greater than that of the dielectric layer on the dielectric layer, forming a mask on the buffer layer, and the mask includes a first opening; before using the mask as a mask to etch the dielectric layer, first using the mask as a mask Etching the buffer layer, and forming a second opening in the buffer layer with a size larger than the first opening, so that when the dielectric layer is etched along the first opening, the interference of the buffer layer to the etching dielectric layer is reduced, and the formed The shape of the through hole, and the process of filling the conductive material into the through hole caused by the above defects, when the inside of the through hole is not filled with conductive material, the opening of the through hole is closed prematurely, resulting in the conductive material formed in the through hole The size and number of holes formed in it. In order to improve the structural form of the subsequently formed interconnection structure and improve the performance of the interconnection structure.

Description

Interconnect structure and method of forming the same

technical field

The invention relates to the technical field of semiconductors, in particular to an interconnection structure and a forming method thereof.

Background technique

With the development of semiconductor technology, the integration level of semiconductor devices continues to increase, and the feature size (Critical Dimension, CD) of semiconductor devices becomes smaller and smaller.

With the gradual reduction of the feature size, the RC delay (RC delay) caused by the parasitic capacitance between the interconnection structures has a greater impact on the semiconductor device. Reducing the K value of the dielectric layer material in the interconnection structure is an effective method to reduce the RC delay effect. In recent years, in the Back End of The Line (BEOL) of semiconductor devices, low K dielectric (Low K, LK) materials (K<3) and ultra-low K dielectric (Ultra Low K, ULK ) material has gradually become the mainstream material of the dielectric layer, and with the development requirements of semiconductor devices, the K value of the dielectric layer material used continues to decrease.

Referring to FIG. 1 and FIG. 2 , there are schematic diagrams of the formation process of the existing interconnect structure, including:

1, after forming a dielectric layer 11 made of LK material or ULK material on a semiconductor substrate 10, a metal mask 13 (such as titanium nitride as a material) is formed on the dielectric layer 11, and The dielectric layer 11 is etched using the metal mask 13 as a mask to form a through hole (not marked in the figure), and then a metal material 16 is filled in the through hole to form an interconnection structure.

Wherein, because the structure of existing LK material and ULK material is relatively sparse, compactness is less, if form metal mask 13 directly on dielectric layer 11, metal mask 13 contacts with dielectric layer 11 and will produce larger impact on dielectric layer 11. The stress action, thus causing damage to the dielectric layer 11. For this reason, continue to refer to Fig. 1, before forming metal mask 13 on described dielectric layer 11, earlier form buffer layer 12 on described dielectric layer 11, the density of described buffer layer 12 is greater than that of described dielectric layer 11. Density. Therefore, the damage of the metal mask to the dielectric layer 11 is reduced, and the quality of the subsequently formed semiconductor device is further improved.

But even so, it is found in the actual operation process that the performance of the interconnection structure formed by the existing technology is poor and cannot meet the development requirements of semiconductor technology. For this reason, how to further improve the performance of the metal plug is an urgent need for those skilled in the art to solve The problem.

Contents of the invention

The problem to be solved by the present invention is to provide an interconnection structure and its forming method, so as to improve the performance of the interconnection structure.

In order to solve the above problems, the method for forming the interconnection structure provided by the present invention includes:

Provide semiconductor substrates;

forming a dielectric layer on the semiconductor substrate;

forming a buffer layer on the dielectric layer, the density of the buffer layer is greater than the density of the dielectric layer;

forming a mask on the buffer layer, the mask including a first opening;

Etching the buffer layer using the mask as a mask to form a second opening in the buffer layer, the size of the second opening is larger than the size of the first opening;

Etching the dielectric layer exposed by the second opening by using the mask as a mask to form a via hole in the dielectric layer;

After etching, the mask has a protrusion protruding from the sidewall of the through hole, and the protrusion is removed;

A conductive material is filled into the through hole to form a conductive plug.

Optionally, the step of etching the buffer layer using the mask as a mask includes etching the buffer layer by using a wet etching process.

Optionally, the wet etching process uses dilute hydrofluoric acid solution as a wet etchant.

Optionally, the volume concentration of hydrofluoric acid in the diluted hydrofluoric acid solution is less than or equal to 30%, and the etching time is 30 seconds to 30 minutes.

Optionally, the material of the buffer layer is silicon dioxide made from tetraethyl orthosilicate.

Optionally, the mask is a metal mask.

Optionally, the material of the metal mask is titanium nitride.

Optionally, the step of removing the mask above the through hole includes: using a wet cleaning process to remove the mask above the through hole; the wet cleaning process uses hydroxylamine, 2-(2-aminoethoxy ) mixed solution of ethanol, catechol and hydrogen peroxide as wet etchant.

Optionally, the temperature of the wet etchant is 30-60°C.

Optionally, a ratio of the opening width of the second opening to the opening width of the first opening is less than or equal to 3.

Optionally, the conductive material is copper.

Optionally, the step of filling the through hole with a conductive material includes: forming a copper seed layer on the inner wall and bottom surface of the through hole, and then using an electroplating process to form a copper layer on the copper seed layer to fill the hole. fill the vias.

Optionally, the step of etching the dielectric layer to form a through hole includes: using a dry etching process to etch the dielectric layer using the mask as a mask to form the through hole.

Optionally, the dielectric constant of the dielectric layer is less than or equal to 3.

The present invention also provides an interconnection structure formed by the above method for forming the interconnection structure.

Compared with the prior art, the technical solution of the present invention has the following advantages:

Forming a buffer layer with a higher density than the dielectric layer on the dielectric layer, forming a mask on the buffer layer, the mask including a first opening; etching the mask using the mask as a mask Before forming the dielectric layer, the buffer layer is etched using the mask as a mask to form a second opening in the buffer layer that is larger in size than the first opening. When subsequently using the mask as a mask to etch the dielectric layer exposed by the second opening, because the size of the second opening is larger than the size of the first opening of the mask, the impact of the buffer layer on Etching the interference of the dielectric layer, improving the shape of the via hole formed in the dielectric layer (such as increasing the opening size of the via hole), and then filling the via hole with conductive material to form a conductive plug In the process, avoid the defect that the via hole opening is closed prematurely when filling the conductive material due to the too small size of the via hole opening, and reduce the premature closure of the via hole opening in the conductive plug. The size and quantity of the formed holes can improve the structure of the conductive plug, so as to improve the structural shape of the subsequently formed interconnection structure and improve the performance of the interconnection structure.

Description of drawings

Fig. 1 and Fig. 2 are structural schematic diagrams of an existing method for forming a metal plug;

3 is a schematic diagram of a semiconductor device after etching a dielectric layer to form a through hole in an existing method for forming a metal plug;

Fig. 4 and Fig. 5 are the electron micrographs of the interconnection structure formed by the prior art;

6 to 14 are structural schematic diagrams of an embodiment of a method for forming an interconnection structure according to the present invention.

detailed description

As mentioned in the background art, in the back-end process of the existing semiconductor device, the performance of the interconnection structure formed in the dielectric layer is poor, which cannot meet the development requirements of the semiconductor technology.

Analyzing the reason, in the existing interconnection structure preparation method, in order to reduce the RC delay effect of the subsequently formed semiconductor device, the existing dielectric layer is mostly made of LK material or ULK material. The density of LK material and ULK material is small, therefore, in order to avoid the stress generated by metal mask (such as titanium nitride mask) 13 from damaging the dielectric layer, in the process of etching the dielectric layer to form the through hole, in the A buffer layer 12 is formed between the dielectric layer 11 and the metal mask 13 , and the density of the buffer layer 12 is greater than that of the dielectric layer 11 , thereby reducing damage to the dielectric layer 11 by the metal mask 13 .

3 and 4, in the process of etching the buffer layer 12 and the dielectric layer 11 with the metal mask 13 as a mask to form the through hole 15 in the dielectric layer 11, because the The density of the buffer layer 12 is greater than the density of the dielectric layer 11, so the etching rate of the buffer layer 12 during etching is lower than the etching rate of the dielectric layer 11, so that after the opening is formed in the buffer layer 12, In the process of continuing to etch the dielectric layer 11, the etching amount of the dielectric layer 11 is greater than the etching amount of the buffer layer 12, and during the continuous increase of the opening size in the dielectric layer 11, the opening size in the dielectric layer 11 is increased. The size of the opening is different from the size of the opening in the buffer layer 12 . The smaller opening of the buffer layer 12 is equivalent to forming a protrusion 121 toward the center of the opening above the side wall of the opening of the dielectric layer 11, and the protrusion 121 becomes the side wall at the upper end of the opening of the dielectric layer 11 and is continuously etched. The obstruction of the through hole 15 subsequently formed in the dielectric layer 11 is a "bottle" structure whose upper opening size is significantly smaller than the size of the middle part, which reduces the structural form of the through hole 15 in the dielectric layer 11.

Referring to FIG. 3 and FIG. 5 , during the subsequent process of filling metal materials such as copper in the through hole 15 , because the opening of the through hole 15 is relatively small, the metal seed layer is easily deposited on the opening part of the through hole 15 , And it is difficult to cover the inner wall of the through hole 15. In the subsequent process of electroplating (Electro chemical plating, referred to as ECP) to continue to form metal on the metal seed layer to fill the through hole 15, the metal is difficult to cover the inner wall of the through hole 15. If the inside of the through hole 15 is not filled with metal, more metal is formed at the opening of the through hole 15 and closed, thereby forming a large-volume hole 151 in the through hole 15 .

The hole 151 will increase the resistance R of the interconnection structure, and even cause defects such as disconnection of the interconnection structure, thereby reducing the performance of the interconnection structure, and further reducing the performance of the subsequently formed semiconductor device.

Therefore, the present invention provides a method for forming an interconnection structure. include:

A dielectric layer is formed on the semiconductor substrate, and a buffer layer is formed on the dielectric layer, the density of the buffer layer is greater than that of the dielectric layer; a mask is formed on the buffer layer, and the mask includes first opening, and then etching the buffer layer using the mask as a mask to form a second opening in the buffer layer, the size of the second opening being larger than the size of the first opening; The mask is a mask to etch the dielectric layer exposed by the second opening to form a through hole in the dielectric layer; remove the protrusion formed during the process of etching the first dielectric layer to form the through hole After partially masking the sidewall of the through hole, filling the through hole with conductive material to form a conductive plug.

In the present invention, before etching the dielectric layer using the mask as a mask, the buffer layer is first etched using the mask as a mask, and the buffer layer is formed in the buffer layer with a size larger than that of the first The second opening of the opening, so that when the dielectric layer exposed by the second opening is etched using the mask as a mask, the interference of the buffer layer to the etching of the dielectric layer can be reduced, and the formation of the dielectric layer can be improved. The opening size of the through hole in the dielectric layer avoids the interference of the buffer layer, so that after the dielectric layer can be formed, the opening size of the upper end of the through hole in the dielectric layer is significantly smaller than the size of the middle part "Bottle" structure, and then in the process of filling the conductive material into the through hole to form the conductive plug, avoiding that the inside of the through hole is not filled with the conductive material due to the small size of the opening of the through hole , the defect that the opening of the through hole is closed prematurely, reducing the size and number of holes formed in the conductive plug due to the premature closure of the opening of the through hole, improving the structure of the conductive plug to improve the subsequent The structural form of the formed interconnection structure improves the performance of the interconnection structure.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

6 to 14 are structural schematic diagrams of an embodiment of a method for forming an interconnection structure according to the present invention.

The forming method of the interconnection structure provided in this embodiment includes:

Referring first to FIG. 6 , a semiconductor substrate 20 is provided.

In this embodiment, the semiconductor substrate 20 is a silicon substrate.

However, in other embodiments except this embodiment, the semiconductor substrate may also be a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate Or other III-V compound substrates, the semiconductor base material does not limit the protection scope of the present invention.

Optionally, a conductive layer 21 is formed in the semiconductor substrate 20 . Further optionally, the material of the conductive layer 21 is copper.

In addition, the semiconductor substrate 20 may also include semiconductor elements such as transistors, and the structure of the semiconductor substrate does not limit the protection scope of the present invention.

Continuing to refer to FIG. 6 , a dielectric layer 22 , a buffer layer 23 , and a mask material layer 24 are sequentially formed on the semiconductor substrate 20 from bottom to top, wherein the buffer layer 23 is denser than the dielectric layer 22 .

In this embodiment, the dielectric layer 22 is used as an insulating layer in the interconnection structure.

Optionally, the material of the dielectric layer 22 is a low-K dielectric material (with a K value less than 3) or an ultra-low-K dielectric material (with a K value less than 2.6). After the interconnection structure is subsequently formed in the dielectric layer 22 , the low-K dielectric material can effectively reduce the parasitic capacitance of the interconnection structure, thereby reducing the resistance-capacitance delay (RC Delay) problem of the interconnection structure.

In this embodiment, the dielectric layer 22 is made of an ultra-low K dielectric material, such as carbon-doped silicon oxide with a porous structure.

The formation method of the dielectric layer 22 is chemical vapor deposition (Chemical Vapor Deposition, CVD for short).

In this embodiment, the mask material layer 24 is used to form a mask for etching the dielectric layer 22 .

Optionally, the metal mask material layer is used to form a metal mask. Further optionally, the material of the mask material layer 24 is titanium nitride (TiN), and the mask material layer 24 may be formed by CVD.

Optionally, in this embodiment, the material of the buffer layer 23 is silicon oxide, and the buffer layer 23 may be formed by CVD. Specifically, the CVD process for forming the buffer layer may be a silicon oxide layer formed by using orthoethyl silicate (TEOS) as a reactant.

In this embodiment, the dielectric layer 22 has a porous structure with a relatively sparse structure and low density. If the mask material layer 24 is formed directly on the dielectric layer 22, the mask material layer 24 produces Stress causes the dielectric layer 22 to deform, thereby causing damage to the dielectric layer 22, thereby affecting the performance of the subsequently formed semiconductor device. The buffer layer 23 can effectively reduce the impact of the mask material layer 24 on the dielectric layer 22. stress to reduce the damage of the dielectric layer 22 .

Referring next to FIG. 7, a photoresist mask 25 is formed on the mask material layer 24, and the mask material layer 24 is etched to form a mask 241 using the photoresist mask 25 as a mask. The mask 241 includes a first opening 31 .

In this embodiment, the mask 241 is a metal mask made of titanium nitride, which is subsequently used to etch the dielectric layer 22 to form via holes of the interconnection structure.

The forming process of the photoresist mask 25 includes firstly forming a photoresist on the mask material layer 24 , and then performing an exposure and development process to form the photoresist mask 25 . The above process is a mature process in the field, and will not be repeated here.

Optionally, using the photoresist mask 25 as a mask, the mask material layer 24 is etched by a dry etching process to form a mask 241. The dry etching process is a mature technology in the art I won't repeat them here.

Optionally, in the step of etching the mask material layer 24, the mask material layer 24 is over-etched to remove a partial thickness of the buffer layer 23 below the mask material layer 24, so as to ensure that the first opening 31 penetrates through the mask material layer 24 and exposes the buffer layer 23 .

Referring to FIG. 8 again, the buffer layer 23 is etched using the mask 241 as a mask to form a second opening 32 in the buffer layer 23, and the size of the second opening 32 is larger than that in the mask 241. The size of the first opening 31.

In this embodiment, a wet etching process is used to etch the buffer layer 23 using the mask 241 as a mask to form the second opening 32 .

Optionally, the process of etching the buffer layer 23 includes: using dilute hydrofluoric acid solution as a wet etchant.

If the concentration of the diluted hydrofluoric acid solution is too high, it will cause damage to the mask 241 and other structures on the semiconductor substrate 20. Optionally, in the diluted hydrofluoric acid solution, hydrofluoric acid The volume concentration is less than or equal to 30%; if the concentration of the diluted hydrofluoric acid solution is too small, reduce the etching rate of the buffer layer 23, optionally, in the diluted hydrofluoric acid solution, hydrofluoric acid The volume concentration of acid is greater than or equal to 15%.

Further optionally, in the diluted hydrofluoric acid solution, the volume concentration of hydrofluoric acid is about 20%.

If the wet etching time is too long, it is easy to cause the buffer layer 23 to be etched too much, causing the size of the second opening 32 to be too large, thereby affecting the structure of the mask 241 on the buffer layer 23 and causing semiconductor substrate Other structures such as the mask 241 on the bottom 20 are damaged; if the etching time is too short, the etching amount of the buffer layer 23 is small, resulting in the size of the formed second opening 32 being too small.

Optionally, the duration of the wet etching buffer layer 23 is between 30 seconds and 30 minutes.

In this embodiment, the ratio of the width d2 of the second opening 32 to the width d1 of the first opening is greater than 1 and less than or equal to 3 (ie: 1<d2/d1≤3), further optionally, d2/d1≥ 1.5.

9, after forming the second opening 32 in the buffer layer 23, continue to use the mask 241 as a mask to etch the dielectric layer 22 exposed by the second opening 32. A through hole 33 is formed in the dielectric layer 22 .

In this embodiment, the through hole 33 penetrates through the dielectric layer 22 and exposes the conductive layer 21 .

Optionally, in this embodiment, a dry etching process is used to etch the dielectric layer 22 exposed by the second opening using the mask as a mask.

In this embodiment, the material of the dielectric layer 22 is silicon oxide, and the dry etching process for etching the dielectric layer 22 includes: using a gas containing Cl ₂ , CH ₄ , SiCl ₄ , NH ₃ and Ar as the dry etching process. method etchant. The process of etching the dielectric layer 22 is the same as the existing process, and will not be repeated here.

Referring to Fig. 8, Fig. 9 and Fig. 3 for comparison, in this embodiment, after using the mask 241 as a mask to etch the buffer layer 23 to form the second opening 32, then using the mask 241 as a mask In the process of etching the dielectric layer 22, because the size of the second opening 32 is larger than the size of the first opening 31, the etching gas passes through the buffer layer 23 and directly etches the dielectric layer 22. , thereby reducing the interference of the buffer layer 23 on the etching of the dielectric layer 22, effectively increasing the opening size of the through hole 33, and optimizing the structure of the through hole 33.

Compared with the prior art shown in FIG. 3 , which uses the metal mask 13 as a mask to continuously etch the buffer layer 12 and the dielectric layer 11, this embodiment can avoid In the layer 11 process, because the buffer layer 12 interferes, the size of the upper opening of the through hole formed in the dielectric layer 11 is significantly smaller than the size of the middle part of the through hole, so that the through hole 15 formed in the dielectric layer 11 has a bottle shape. structural defects appear. Furthermore, in the subsequent process of filling conductive material into the through hole 33 to form a conductive plug, the defect of premature closure of the opening of the through hole is avoided, and the occurrence of premature closure of the opening of the through hole is reduced. The size and number of holes formed in the plug, improving the structure of the conductive plug,

In this embodiment, the density of the dielectric layer 22 is low, so after the dielectric layer 22 is dry etched, the size of the formed through hole 35 is larger than the size of the first opening 31 of the mask 241. A protrusion 242 is formed in the mask 241 toward the center of the through hole 33 and protrudes from the sidewall of the through hole. But because the mask 241 is not in direct contact with the dielectric layer 22, and the size of the second opening 32 is larger than the size of the first opening 31, the mask 241 is used to etch the second opening 32 to expose During the process of etching the dielectric layer 22, the etching gas can diffuse in the opening formed in the etching dielectric layer 22, so the impact of the protrusion 242 on the through hole 35 is small and will not affect The opening size of the through hole 33 .

However, in order to reduce the influence of the protrusions 242 on the filling of the conductive material in the through hole 33, referring to FIG. (ie, removing the part of the mask 241 protruding from the sidewall of the through hole 33 ), so as to fill the through hole 33 with a conductive material to form an interconnection structure.

In this embodiment, the protrusion 242 above the through hole 33 is removed by a wet cleaning process.

Optionally, the wet cleaning process may use a mixed solution of EKC and hydrogen peroxide (H ₂ O ₂ ) as a cleaning agent.

Wherein, the EKC is a mixed solution of hydroxylamine (HDA), 2-(2-aminoethoxy)ethanol (DGA) and catechol. In the cleaning agent, the volume ratio concentration of EKC is 0.5%-6%, and the volume ratio concentration of hydrogen peroxide solution is 1-10%. The cleaning agent of the above components can remove the mask 241 above the through hole 33 (Titanium nitride is the material) At the same time, the structure above the semiconductor substrate 20 is prevented from being damaged.

Further optionally, the temperature of the EKC solution is 30-60° C., so as to increase the removal rate of the mask 241 and at the same time reduce the damage to the semiconductor substrate 20 and other structures above the semiconductor substrate 241 caused by the wet cleaning process. .

In addition, using a mixed solution of EKC and hydrogen peroxide (H ₂ O ₂ ) as a cleaning agent can effectively remove the etching by-products formed during the process of etching the dielectric layer 33 while removing the protrusions 242 .

It should be noted that, in another embodiment of the present invention, after the through hole 33 is formed, the mask 241 on the dielectric layer 22 is directly removed, thereby reducing the influence of the mask 241 on subsequent processes . These simple changes are all within the protection scope of the present invention.

Referring to FIG. 11 , in this embodiment, after removing the protrusion 242 and before filling the through hole 33 with conductive material, a diffusion barrier layer 25 is first formed on the sidewall and bottom of the through hole 33 .

In this embodiment, the material of the diffusion barrier layer 25 is tantalum nitride (TaN), and the formation process is CVD. In other embodiments of the present invention, the material of the diffusion barrier layer 25 can also be tantalum (Ta), etc., and the formation method of tantalum is other materials such as physical vapor deposition (Physical Vapor Deposition, PVD), and the diffusion barrier layer The material and forming method of 25 do not limit the protection scope of the present invention.

Moreover, the diffusion barrier layer 25 can also improve the bonding force between the conductive material subsequently formed in the through hole 33 and the dielectric layer 22 .

Moreover, in this embodiment, compared with the prior art, the opening of the through hole 33 is effectively enlarged, so that the diffusion barrier layer 25 is closely attached to the sidewall and bottom of the through hole 33 .

Afterwards, a conductive material is filled in the through hole 33 to form a conductive plug.

In this embodiment, the conductive material is copper, and the subsequently formed interconnection structure is a copper interconnection structure.

Specifically, the step of filling copper conductive material includes:

Referring first to FIG. 12 , a copper seed layer 26 is formed on the surface of the diffusion barrier layer 24 .

In this embodiment, the copper seed layer 26 covers the sidewall and bottom of the through hole 33 and above the semiconductor substrate 20, and the copper seed layer 26 is formed by physical vapor deposition (Physical Vapor Deposition). Vapor Deposition, referred to as PVD).

In this embodiment, because the opening of the through hole 33 is effectively enlarged, and the mask 241 and the buffer layer 23 protruding from the side wall of the through hole 33 are removed, the through hole 33 is exposed, so that the The copper seed layer 26 tightly covers the sidewall and bottom of the through hole 33 .

Referring to FIG. 13 , the copper layer 27 is continuously formed on the copper seed layer 26 , so that the copper layer 27 fills the through hole 33 .

In this embodiment, the copper layer 27 covers the semiconductor substrate 20 .

In this embodiment, the copper layer is continuously formed on the metal seed layer 26 by using electro chemical plating (ECP) until the copper layer fills the through hole 33 . The method of continuing to form the copper layer on the copper seed layer 26 by ECP process is a mature technology in the field, and will not be repeated here.

Referring again to FIG. 14 , chemical mechanical polishing (CMP) and other processes are used to remove the copper layer, buffer layer and mask above the semiconductor substrate 20, exposing the surface of the semiconductor substrate 20, so that the through hole 33 (Fig. 12) the surface of the inner copper layer is flush with the surface of the semiconductor substrate 20, a conductive plug 28 is formed in the dielectric layer 22, and the conductive plug 28 is connected to the conductive layer in the semiconductor substrate 10 21 fixed connections.

In this embodiment, before etching the dielectric layer using the mask as a mask, first etch the buffer layer using the mask as a mask, and form a A second opening of an opening, so that when the dielectric layer exposed by the second opening is etched with the mask, the interference of the buffer layer to the etching of the dielectric layer is reduced, and the dielectric layer in the dielectric layer is effectively increased. The size of the opening of the through hole, so that during the process of filling the through hole with conductive material to form a conductive plug, it overcomes the problem that the through hole is not filled with conductive material because the opening of the through hole is too small. The defect that the opening of the through hole is closed prematurely, thereby reducing the size and number of holes formed in the conductive plug due to the premature closure of the through hole opening, improving the structure of the conductive plug to improve subsequent formation. The structural form of the interconnection structure improves the performance of the interconnection structure.

In addition, the present invention also provides an interconnection structure manufactured by using the method for forming the interconnection line of the above-mentioned embodiment.

Compared with the interconnection structure formed by using the existing process, the number and volume of holes in the conductive plug in the interconnection structure formed by the above embodiment are significantly reduced, thereby effectively improving the shape and structure of the conductive plug, To improve the performance of the interconnect structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (15)

1. A method for forming an interconnection structure, comprising: Provide semiconductor substrates; forming a dielectric layer on the semiconductor substrate; forming a buffer layer on the dielectric layer, the density of the buffer layer is greater than the density of the dielectric layer; forming a mask on the buffer layer, the mask including a first opening; Etching the buffer layer using the mask as a mask to form a second opening in the buffer layer, the size of the second opening is larger than the size of the first opening; Etching the dielectric layer exposed by the second opening by using the mask as a mask to form a via hole in the dielectric layer; After etching, the mask has a protrusion protruding from the sidewall of the through hole, and the protrusion is removed; A conductive material is filled into the through hole to form a conductive plug. 2. The method for forming an interconnection structure according to claim 1, wherein the step of etching the buffer layer using the mask as a mask comprises etching the buffer layer using a wet etching process . 3. The method for forming the interconnection structure according to claim 2, wherein the wet etching process uses a diluted hydrofluoric acid solution as a wet etchant. 4. The method for forming an interconnection structure as claimed in claim 3, wherein the volume concentration of hydrofluoric acid in the diluted hydrofluoric acid solution is less than or equal to 30%, and the etching time is 30 seconds to 30 minutes . 5 . The method for forming an interconnection structure according to claim 1 , wherein the material of the buffer layer is silicon dioxide prepared from ethyl orthosilicate. 5 . 6. The method for forming an interconnection structure according to claim 1, wherein the mask is a metal mask. 7. The method for forming an interconnection structure according to claim 6, wherein the material of the metal mask is titanium nitride. 8. The method for forming an interconnection structure according to claim 1, wherein the step of removing the mask above the through hole comprises: removing the mask above the through hole by using a wet cleaning process; The wet cleaning process uses a mixed solution of hydroxylamine, 2-(2-aminoethoxy)ethanol, catechol and hydrogen peroxide as a wet etchant. 9. The method for forming an interconnection structure according to claim 8, wherein the temperature of the wet etchant is 30-60°C. 10 . The method for forming an interconnection structure according to claim 1 , wherein a ratio of the opening width of the second opening to the opening width of the first opening is less than or equal to 3. 11 . 11. The method for forming an interconnection structure according to claim 1, wherein the conductive material is copper. 12. The method for forming an interconnect structure according to claim 11, wherein the step of filling the through hole with a conductive material comprises: forming a copper seed layer on the inner wall and bottom surface of the through hole, and then using An electroplating process forms a copper layer on the copper seed layer to fill the through holes. 13. The method for forming an interconnection structure according to claim 1, wherein the step of etching the dielectric layer to form a through hole comprises: using a dry etching process, using the mask as a mask The dielectric layer is etched to form the through hole. 14. The method for forming an interconnection structure according to claim 1, wherein the dielectric constant of the dielectric layer is less than or equal to 3. 15. An interconnection structure formed by using the method for forming an interconnection structure according to any one of claims 1-14.