CN105990348B - A kind of SRAM and its manufacturing method, electronic device - Google Patents
A kind of SRAM and its manufacturing method, electronic device Download PDFInfo
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- CN105990348B CN105990348B CN201510086298.7A CN201510086298A CN105990348B CN 105990348 B CN105990348 B CN 105990348B CN 201510086298 A CN201510086298 A CN 201510086298A CN 105990348 B CN105990348 B CN 105990348B
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- 238000000034 method Methods 0.000 claims description 35
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical group [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 13
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- 239000000463 material Substances 0.000 description 19
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
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Abstract
The present invention provides a kind of SRAM and its manufacturing method, electronic device, the SRAM includes an at least PG transistor, wherein the source region of the PG transistor and drain region have different doping concentrations, the manufacturing method of the PG transistor includes: offer semiconductor substrate, it is formed with fin on a semiconductor substrate, is formed with isolation structure at the both ends of fin；The first groove, and the epitaxial growth high-dopant concentration epitaxial layer in the first groove are formed in one end of fin；The second groove, and the epitaxial growth low doping concentration epitaxial layer in the second groove are formed in the other end of fin；Gate structure is formed in the two sides of fin and top.According to the present invention, under the premise of not changing the quantitative relation of PU, PD and PG, it can effectively promote the static noise margin of the SRAM and write tolerance.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of SRAM and its manufacturing method, electronic device.
Background technique
Static random access memory (SRAM) is widely used in number and communication as a kind of important memory device
In circuit design, because having many advantages, such as small power consumption, reading fast reading is fast and is widely used in the storage of data.
Typical sram cell includes six metal-oxide-semiconductors (having 6T structure) as shown in Figure 1A, wherein pulling up transistor
(PU) and the control switch (PG) of storage basic unit to the bit line (Bit Line) for read-write is usually NMOS, lower crystal pulling
Managing (PD) is that PMOS, a pair of of PU and PD constitute CMOS inverter.In order to reduce sram cell occupancy chip area, usual PU,
The quantitative relation of PD and PG is PU:PD:PG=1:1:1.But by read-write stability analysis it is found that PU:PD:PG=1:1:1
Sram cell have and lower static noise margin and write tolerance, in order to solve this problem, when designing sram cell domain,
It needs for β value (PD/PG) to be set as that γ value (PG/PU) is set as not less than 1.5 not less than 1.2.The prior art passes through two kinds
Mode improves β value and γ value: first is that changing the quantitative relation of PU, PD and PG, drawback is the core for increasing sram cell and occupying
Piece area and the read-write stability for reducing sram cell (α value (PU/PD) is less than 1)；Second is that not changing the quantity of PU, PD and PG
Relationship, makes the height difference for respectively constituting PU, PD with the fin channel of the FinFET of PG, and drawback is to increase answering for manufacture craft
The promotion of miscellaneous degree and cost.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
Summary of the invention
In view of the deficiencies of the prior art, the present invention provides the manufacturing method of SRAM a kind of, and the SRAM includes an at least PG
Transistor, wherein the source region of the PG transistor and drain region have different doping concentrations, the manufacturing method of the PG transistor
Include: offer semiconductor substrate, be formed with fin on the semiconductor substrate, is formed with isolation junction at the both ends of the fin
Structure；The first groove, and the epitaxial growth high-dopant concentration epitaxial layer in first groove are formed in one end of the fin；?
The other end of the fin forms the second groove, and the epitaxial growth low doping concentration epitaxial layer in second groove；Institute
The two sides and top for stating fin form gate structure.
In one example, doping concentration the mixing than the high-dopant concentration carbon silicon layer of the low doping concentration carbon silicon layer
Low 2.0 × the e of miscellaneous concentration2cm-3。
In one example, when the flow direction of electric current is from the high-dopant concentration epitaxial layer to the low doping concentration extension
When layer, the SRAM is read；When electric current when flowing to from the low doping concentration epitaxial layer to described highly doped dense
When spending epitaxial layer, the SRAM carries out write operation.
In one example, the SRAM has 6T structure, and there is the high-dopant concentration epitaxial layer and described at both ends respectively
The fin of low doping concentration epitaxial layer is the fin of the PG in the 6T structure.
In one example, the quantitative relation of PU, PD and PG in the 6T structure are PU:PD:PG=1:1:1.
In one example, the epitaxial layer is silicon carbide layer.
In one embodiment, the present invention also provides a kind of SRAM manufactured using the above method.
In one embodiment, the present invention also provides a kind of electronic device, the electronic device includes the SRAM.
According to the present invention, under the premise of not changing the quantitative relation of PU, PD and PG, it can effectively promote the SRAM's
Static noise margin and write tolerance.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A is the circuit diagram of existing sram cell；
Figure 1B is the top view of the PG in the sram cell formed according to the method for exemplary embodiment of the present one；
Fig. 2A-Fig. 2 F is the device that obtains respectively the step of successively implementation according to the method for exemplary embodiment of the present one
The schematic cross sectional view of part；
Fig. 3 is flow chart the step of successively implementation according to the method for exemplary embodiment of the present one.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
SRAM and its manufacturing method, electronic device.Obviously, execution of the invention is not limited to the technical staff institute of semiconductor field
The specific details being familiar with.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention is also
It can have other embodiments.
It should be understood that when the term " comprising " and/or " including " is used in this specification, indicating described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or their combination.
In order to solve the problems, such as existing 6T structure sram cell with lower static noise margin and write tolerance, this hair
Bright proposition makes the semiconductor substrate (source region and drain region) of the grid two sides of the PG in sram cell have different doping concentrations, such as
Shown in Figure 1B, fin 101 is formed in semiconductor substrate 100, when the flow direction of electric current is low from having for 102 right side of grid is located at
The semiconductor substrate 100 (drain region) of doping concentration arrives the semiconductor substrate 100 with high-dopant concentration for being located at 102 left side of grid
When (source region), sram cell carries out write operation；When the flow direction of electric current is that have high-dopant concentration from positioned at 102 right side of grid
Semiconductor substrate 100 (drain region) arrive the semiconductor substrate 100 (source region) with low doping concentration for being located at the left side of grid 102
When, sram cell is read.By read-write stability analysis it is found that the sram cell comprising the PG with These characteristics
Static noise margin promoted 5%, write tolerance promoted 10%.It describes to make in sram cell referring to exemplary embodiment one
PG grid two sides semiconductor substrate (source region and drain region) have different doping concentrations preparation method.
[exemplary embodiment one]
The step of reference Fig. 2A-Fig. 2 F, the method for being shown according to an exemplary embodiment of the present one is successively implemented
The schematic cross sectional view of the device obtained respectively.
Firstly, as shown in Figure 2 A, semiconductor substrate is provided, since the schematic cross sectional view is the length side along fin
To acquisition, thus it is not shown.The constituent material of semiconductor substrate can use undoped monocrystalline silicon, doped with impurity
Monocrystalline silicon etc..As an example, in the present embodiment, semiconductor substrate selects single crystal silicon material to constitute.
It is formed with fin 201 on a semiconductor substrate.As an example, the processing step for forming fin 201 includes: partly to lead
Hard mask layer is formed in body substrate, formed the hard mask layer can using those skilled in the art be familiar with it is various suitable
Technique, such as chemical vapor deposition process, the material of the hard mask layer can be nitride, preferably silicon nitride；Patterning institute
Hard mask layer is stated, the exposure mask for being formed on fin 201 for etching semiconductor substrate, the work of the patterning process are formed
Skill step successively includes: the photoresist layer for being formed on the hard mask layer and having the pattern of the exposure mask, using dry etching
Technique removes the hard mask layer not covered by the photoresist layer, and removes the photoresist layer using cineration technics；It adopts
The exposure mask is removed with wet etching process.
Isolation structure 200 is formed at the both ends of fin 201.As an example, forming the processing step packet of isolation structure 200
It includes: forming another hard mask layer on a semiconductor substrate, cover fin 201, be familiar with using those skilled in the art various
Suitable technology forms another hard mask layer, such as chemical vapor deposition process, the material of another hard mask layer
Expect preferred silicon nitride；Another hard mask layer is patterned, is constituted isolation structure 200 to be formed in another hard mask layer
Pattern opening, the process include: on another hard mask layer formed have isolation structure 200 pattern photoresist
Layer is etched another hard mask layer until exposing fin 201, is removed using cineration technics using the photoresist layer as exposure mask
The photoresist layer；Using patterned another hard mask layer as exposure mask, is etched in fin 201 and be used to form isolation junction
The groove of structure 200；Depositing isolation material, the isolated material are usually in the trench and on another hard mask layer
Oxide, as an example, the isolated material is HARP in the present embodiment；It is described to grind to execute chemical mechanical milling tech
Isolated material removes another hard mask layer while exposing fin 201.
Then, as shown in Figure 2 B, the first groove 204 is formed in one end of fin 201.As an example, forming the first groove
204 processing step includes: to form the first hard mask layer 202 on a semiconductor substrate, covers fin 201 and isolation structure 200,
The first hard mask layer 202, such as chemical gaseous phase are formed using the various suitable technologies that those skilled in the art are familiar with
Depositing operation, the preferred silicon nitride of material of the first hard mask layer 202；The first hard mask layer 202 is patterned, in the first hard exposure mask
The opening for constituting the pattern of the first groove 204 is formed in layer 202, which includes: to be formed to have on the first hard mask layer 202
First photoresist layer 203 of the pattern of the first groove 204, is exposure mask with the first photoresist layer 203, etches the first hard mask layer
202 one end up to exposing fin 201 is further continued for etching to etch the first groove 204, the erosion in one end of fin 201
Quarter can remove portions of isolation structure 200 simultaneously.
Then, as shown in Figure 2 C, the epitaxial growth high-dopant concentration epitaxial layer 205 in the first groove 204.The extension is raw
Long technique can be true using low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), superelevation
One of empty chemical vapor deposition (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).Make
For example, the epitaxial layer 205 can be silicon carbide layer.Before implementing the epitaxial growth, pass through cineration technics removal first
Photoresist layer 203.After implementing the epitaxial growth, the first hard mask layer 202 is removed by etching.
Then, as shown in Figure 2 D, the second groove 208 is formed in the other end of fin 201.As an example, it is recessed to form second
The processing step of slot 208 includes: to form the second hard mask layer 206 on a semiconductor substrate, covers fin 201, isolation structure 200
With high-dopant concentration carbon silicon layer 205, it is hard that second is formed using the various suitable technologies that those skilled in the art are familiar with
Mask layer 206, such as chemical vapor deposition process, the preferred silicon nitride of material of the second hard mask layer 206；Patterning second is covered firmly
Film layer 206, to form the opening for being constituted the pattern of the second groove 208 in the second hard mask layer 206, which includes: the
Second photoresist layer 207 with the pattern of the second groove 208 is formed on two hard mask layers 206, is with the second photoresist layer 207
Exposure mask, the other end of the second hard mask layer of etching 206 up to exposing fin 201, is further continued for etching in the other end of fin 201
The second groove 208 is etched, the etching can remove portions of isolation structure 200 simultaneously.
Then, as shown in Figure 2 E, the epitaxial growth low doping concentration epitaxial layer 209 in the second groove 208.As an example,
The doping concentration of low doping concentration epitaxial layer 209 is 2.0 × e lower than the doping concentration of high-dopant concentration epitaxial layer 2052cm-3.It is described
Epitaxial growth technology can use low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high vacuum chemical gas
Mutually one of deposition, rapid thermal CVD and molecular beam epitaxy.As an example, the epitaxial layer 209 can be carbon
SiClx layer.Before implementing the epitaxial growth, the second photoresist layer 207 is removed by cineration technics.Implement the epitaxial growth
Later, the second hard mask layer 206 is removed by etching.
Then, as shown in Figure 2 F, gate structure is formed in the two sides of fin 201 and top, as an example, gate structure packet
Include the gate dielectric 210a being laminated from bottom to top, gate material layers 210b and grid hard masking layer 210c.
Specifically, the constituent material of gate dielectric 210a includes oxide, such as silica (SiO2).Select SiO2
When constituent material as gate dielectric, gate dielectric is formed by rapid thermal oxidation process (RTO), with a thickness of 8-
50 angstroms, however, it is not limited to this thickness.
The constituent material of gate material layers 210b includes polysilicon, metal, conductive metal nitride, conductive metal oxygen
One of compound and metal silicide are a variety of, wherein metal can be tungsten (W), nickel (Ni) or titanium (Ti)；Conductive metal
Nitride includes titanium nitride (TiN)；Conductive metal oxide includes yttrium oxide (IrO2)；Metal silicide includes titanium silicide
(TiSi).When selecting constituent material of the polysilicon as gate material layers, optional low-pressure chemical vapor phase deposition (LPCVD) technique
Gate material layers are formed, process conditions include: that reaction gas is silane (SiH4), flow is 100~200sccm, preferably
150sccm；Temperature in reaction chamber is 700~750 DEG C；Pressure in reaction chamber is 250~350mTorr, preferably
300mTorr；The reaction gas can also include buffer gas, and the buffer gas is helium (He) or nitrogen (N2), stream
Amount is 5~20 liters/min (slm), preferably 8slm, 10slm or 15slm.
The constituent material of grid hard masking layer 210c includes one in oxide, nitride, nitrogen oxides and amorphous carbon
Kind is a variety of, wherein oxide includes boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), ethyl orthosilicate (TEOS), do not mix
Miscellaneous silica glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD)；Nitride includes nitrogen
SiClx (SiN)；Nitrogen oxides includes silicon oxynitride (SiON).The forming method of grid hard masking layer can use art technology
Any prior art that personnel are familiar with, preferably chemical vapour deposition technique (CVD), such as low temperature chemical vapor deposition (LTCVD), low
Pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition
(PECVD)。
Then, the offset side wall 211 against gate structure, constituent material SiO are formed in gate structure two sides2、
One of SiN, SiON or their combination.During gate structure two sides form offset side wall, the two of fin 201
Side also will form offset side wall 211, therefore, next, removal is located at the offset side wall 211 of 201 two sides of fin.
So far, the processing step that the method for completing according to an exemplary embodiment of the present one is implemented.According to the present invention, exist
Under the premise of the quantitative relation for not changing PU, PD and PG, it can effectively promote the static noise margin of sram cell and write tolerance.
The process of the step of reference Fig. 3, the method for being shown according to an exemplary embodiment of the present one is successively implemented
Figure, for schematically illustrating the process of manufacturing process.
In step 301, semiconductor substrate is provided, is formed with fin on a semiconductor substrate, is formed at the both ends of fin
There is isolation structure；
In step 302, the first groove, and the epitaxial growth high-dopant concentration in the first groove are formed in one end of fin
Epitaxial layer；
In step 303, the second groove is formed in the other end of fin, and epitaxial growth is low-doped dense in the second groove
Spend epitaxial layer；
In step 304, gate structure is formed in the two sides of fin and top.
[exemplary embodiment two]
Next, the production of entire SRAM can be completed by subsequent technique, comprising: sequentially form on a semiconductor substrate
With the contact etch stop layer and interlayer dielectric layer that can produce stress characteristics, chemical mechanical grinding is executed to expose grid knot
The top of structure；Then, gate structure is removed, high k- metal gate structure is formed in the groove left, as an example, this structure
Including high k dielectric layer, coating, workfunction layers, barrier layer and the metal material layer being laminated from bottom to top；Next, shape
At another interlayer dielectric layer, then, top and the institute for being connected to the metal gate structure are formed in above-mentioned interlayer dielectric layer
The contact hole for stating source/drain region pole, by the contact hole, the top of the metal gate structure of exposing and the source/
Drain region extremely on form self-aligned silicide, fill and form connection in metal (usually tungsten) Yu Suoshu contact hole and implement back-end manufacturing
The contact plug of technique and the interconnecting metal layer that is formed and the self-aligned silicide；Next, conventional FinFET can be implemented
Device back end fabrication, such as the formation of multiple interconnecting metal layers, generally use dual damascene process to complete, metal welding
The formation of disk, for implementing wire bonding when device encapsulation.
[exemplary embodiment three]
The present invention also provides a kind of electronic devices comprising two method manufactures according to an exemplary embodiment of the present
SRAM.The electronic device can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD, DVD,
Any electronic product such as navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, be also possible to any include
The intermediate products of the semiconductor devices.The electronic device due to having used the semiconductor devices, thus has better
Performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (7)
1. a kind of manufacturing method of SRAM, the SRAM includes an at least PG transistor, wherein the source region of the PG transistor and
Drain region has different doping concentrations, and the manufacturing method of the PG transistor includes:
There is provided semiconductor substrate, be formed with fin (201) on the semiconductor substrate, the both ends of the fin be formed with every
From structure (200)；
The first groove (204) are formed in one end of the fin, and in first groove outside epitaxial growth high-dopant concentration
Prolong layer (205)；
The second groove (208) are formed in the other end of the fin, and the epitaxial growth low doping concentration in second groove
Epitaxial layer (209)；
Gate structure is formed in the two sides of the fin and top；Wherein, the doping concentration ratio of the low doping concentration epitaxial layer
The doping concentration of the high-dopant concentration epitaxial layer is low.
2. the method according to claim 1, wherein the flow direction when electric current is from the high-dopant concentration epitaxial layer
When to the low doping concentration epitaxial layer, the SRAM is read；When electric current when flowing to from the low doping concentration
When epitaxial layer is to the high-dopant concentration epitaxial layer, the SRAM carries out write operation.
3. there is the height at both ends respectively the method according to claim 1, wherein the SRAM has 6T structure
The fin of doping concentration epitaxial layer and the low doping concentration epitaxial layer is the fin of the PG in the 6T structure.
4. according to the method described in claim 3, it is characterized in that, the quantitative relation of PU, PD and PG in the 6T structure are
PU:PD:PG=1:1:1.
5. the method according to claim 1, wherein the epitaxial layer is silicon carbide layer.
6. a kind of SRAM manufactured using method described in one of claim 1-5.
7. a kind of electronic device, the electronic device includes SRAM as claimed in claim 6.
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| US6391689B1 (en) * | 2001-06-06 | 2002-05-21 | United Microelectronics Corp. | Method of forming a self-aligned thyristor |
| CN103489914A (en) * | 2012-06-12 | 2014-01-01 | 香港科技大学 | Static random access memory with asymmetric transistors and its control method |
| CN103515434A (en) * | 2012-06-26 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor and formation method thereof, and SRAM memory cell circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6391689B1 (en) * | 2001-06-06 | 2002-05-21 | United Microelectronics Corp. | Method of forming a self-aligned thyristor |
| CN103489914A (en) * | 2012-06-12 | 2014-01-01 | 香港科技大学 | Static random access memory with asymmetric transistors and its control method |
| CN103515434A (en) * | 2012-06-26 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor and formation method thereof, and SRAM memory cell circuit |
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