CN106024634B - Power transistor with electrostatic discharge protection diode structure and manufacturing method thereof - Google Patents

Abstract

The invention relates to a power transistor with an electrostatic discharge protection diode structure and a manufacturing method thereof. The power transistor comprises a terminal area, an active area and a polycrystalline silicon gate area located between the terminal area and the active area, wherein the polycrystalline silicon gate area is separated from a polycrystalline silicon gate in the active area and comprises a gate and an electrostatic discharge protection diode structure on two sides of the gate, the gate and the electrostatic discharge protection diode structure are both made of polycrystalline silicon, the electrostatic discharge protection diode structure on two sides of the gate comprises a plurality of P-type doped areas and N-type doped areas, the P-type doped areas and the N-type doped areas are arranged at intervals in a first direction, first contact holes are formed in the outermost N-type doped areas on two sides of the polycrystalline silicon gate area, and second contact holes are formed in the gate. The polysilicon gate region is separated from the polysilicon gate in the active region to form an independent island structure, so that the gate is led out through the second contact hole to be connected with the gate metal, and batch packaging is facilitated.

Description

Power transistor with electrostatic discharge protection diode structure and manufacturing method thereof

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a power transistor with an electrostatic discharge protection diode structure, and also to a manufacturing method for the power transistor with an electrostatic discharge protection diode structure.

Background technique

Electrostatic discharge is one of the most important reliability issues for power devices. Electrostatic discharge, referred to as ESD (ElectroStatic Discharge), is a rapid charge transfer phenomenon between two objects, which is accompanied by a large electric field and current density. Static electricity is hard to prevent, and it is ubiquitous in the production, storage, transportation and use of power devices. Electrostatic discharge will generate a discharge voltage of several thousand volts at both ends of the power device. In the application and production of power devices, it is an important cause of damage to power devices. When the voltage across the device exceeds the breakdown voltage, any significant current flow will cause significant power dissipation, resulting in localized heating of the device. If the temperature rise is large enough that the temperature reaches the intrinsic temperature, even if this occurs locally, the resulting current may cause a thermal run. With the increasing complexity of the electromagnetic environment and the continuous reduction of the thickness of the gate oxide layer of power devices caused by the development of microelectronics technology, the protection of ESD is becoming more and more important.

The development of power transistors with integrated anti-ESD protection in China is still in its infancy, and there is a big gap with the mature products with ESD protection of foreign mainstream power transistor manufacturers. The ESD protection structure of power devices usually adopts three structures: PN junction, SCR (silicon controlled silicon) and POLY (polysilicon) diode.

Contents of the invention

Based on this, it is necessary to provide an easily packaged power transistor with an electrostatic discharge protection diode structure.

A power transistor with an electrostatic discharge protection diode structure, comprising a terminal area and an active area surrounded by the terminal area, and also includes a polysilicon gate area located between the terminal area and the active area, the polysilicon gate The pole region is separated from the polysilicon gate in the active region, the polysilicon gate region includes the gate and electrostatic discharge protection diode structures on both sides of the gate, and the material of the gate and the electrostatic discharge protection diode structure Both are polysilicon, and the electrostatic discharge protection diode structure on both sides of the gate includes a plurality of P-type doped regions and N-type doped regions, and the P-type doped regions and N-type doped regions are in the first direction arranged at intervals, the first direction is the direction in which the gate extends to both sides; the outermost P-type doped region or N-type doped region on both sides of the polysilicon gate region is provided with a first contact hole, The gate is opened with a second contact hole.

In one of the embodiments, the doping type of the gate is N type.

In one of the embodiments, the polysilicon gate region is surrounded by the active region and the terminal region, wherein three sides of the polysilicon gate region are surrounded by the active region, and the remaining side is surrounded by the terminal region Form an encirclement.

In one embodiment, the widths of the P-type doped regions and the N-type doped regions are equal, and the direction of the widths is a second direction perpendicular to the first direction.

In one of the embodiments, the first side of the gate adjacent to the terminal region protrudes outward so that the width of the gate is greater than the widths of the P-type doped region and the N-type doped region.

In one of the embodiments, the second contact hole is disposed in a region where the first side protrudes outward.

In one of the embodiments, the cross section of the first contact hole is an elongated shape extending along the second direction, and the cross section of the second contact hole is an elongated shape extending along the first direction. .

In one of the embodiments, the doping concentration of each of the P-type doped regions is smaller than the doping concentration of each of the N-type doped regions, and the size of each of the P-type doped regions in the first direction is greater than the size of each of the N-type doped regions in the first direction.

In the above-mentioned power transistor with electrostatic discharge protection diode structure, the polysilicon gate area is separated from the polysilicon gate strip in the active area to form an independent small island structure, and the two sides of the polysilicon gate area are electrostatic discharge protection diode structures, and the middle It is used as a gate, which is convenient for the gate to be connected to the gate metal through the second contact hole, which is beneficial to batch packaging.

It is also necessary to provide a method for manufacturing a power transistor with an electrostatic discharge protection diode structure.

A method for manufacturing a power transistor with an electrostatic discharge protection diode structure, comprising: forming a field oxide layer and a gate oxide layer on a substrate; depositing polysilicon on the gate oxide layer and/or field oxide layer to form a polysilicon gate pole; the polysilicon gate includes a polysilicon grid strip in the active area and a polysilicon gate area located between the active area and the terminal area, the polysilicon gate area is separated from the polysilicon grid strip in the active area Implanting P-type ions to form a P well in the substrate, and the polysilicon gate region forms a P-region due to P-type ion implantation; implanting N-type ions to form an N+ source region in the P well, and The P-region forms a plurality of P-type doped regions and N-type doped regions on both sides of the gate of the polysilicon gate region due to N-type ion implantation, and the P-type doped regions and N-type doped regions are formed on the first side Arranging at intervals upward to form an electrostatic discharge protection diode structure, the first direction is the direction in which the gate extends to both sides; depositing a dielectric layer on the substrate and the polysilicon gate; performing contact hole photolithography and etching , forming a contact hole; performing P+ implantation on the P well through the contact hole; forming a metal interconnection layer.

In one embodiment, before the step of implanting P-type ions, a step of performing N-type ion diffusion on the polysilicon gate is further included, and the doping type of the gate in the polysilicon gate region is N-type.

The method for manufacturing the above-mentioned power transistor with the electrostatic discharge protection diode structure adjusts the second P+ implantation after the N+ implantation and before depositing the dielectric layer in the traditional power device manufacturing process to be after the contact hole etching Carry out so that the deposited dielectric layer can block the impact of the second P+ implantation on the P-type doped region in the electrostatic discharge protection diode structure, so that it does not become a P+ region, so that the Igss leakage can be greatly reduced, thereby enabling Low-cost, high-reliability power devices are manufactured.

Description of drawings

Fig. 1 is a schematic plan view of a power transistor with an electrostatic discharge protection diode structure in an embodiment;

FIG. 2 is a schematic plan view of the gate 31 in an embodiment;

FIG. 3 is a schematic plan view of the gate 31 in another embodiment;

FIG. 4 is a schematic plan view of the device after adding polysilicon gate strips 21 in the active region 2 on the basis of FIG. 1;

FIG. 5 is a flow chart of a method for manufacturing a power transistor with an ESD protection diode structure in an embodiment.

Detailed ways

In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the associated drawings. A preferred embodiment of the invention is shown in the drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The semiconductor field vocabulary used in this article is a technical vocabulary commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type simply represents P-type with heavy doping concentration, and P-type represents medium. P-type with doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents light-doped concentration Type N.

The power transistor may be a vertical double diffused metal oxide semiconductor field effect transistor (VDMOSFET), an insulated gate bipolar transistor (IGBT) and other power devices. Since the gate-source of a power transistor such as VDMOS is most susceptible to ESD damage, the present invention mainly relates to the ESD protection structure between the gate-source.

1 is a schematic plan view of a power transistor with an electrostatic discharge protection diode structure in an embodiment, including a termination region 1, an active region 2 surrounded by the termination region 1, and a region between the termination region 1 and the active region 2. The polysilicon gate region 3 is separated from the polysilicon gate (not shown in FIG. 1 ) in the active region 2 . The polysilicon gate region 3 includes a gate 31 and ESD protection diode structures 32 on both sides of the gate 31 , and both the gate 31 and the ESD protection diode structures 32 are made of polysilicon. FIG. 2 is a schematic plan view of the gate 31 in an embodiment. The electrostatic discharge protection diode structure 32 on both sides of the gate 31 includes a plurality of P-type doped regions and N-type doped regions, and the P-type doped regions and N-type doped regions are arranged at intervals in the Y-axis direction in FIG. 2 , And the Y-axis direction is the direction in which the gate 31 extends to both sides. Each pair of P-type doped region and N-type doped region forms a PN diode. A first contact hole 321 is opened in the outermost P-type doped region or N-type doped region on both sides of the polysilicon gate region 3 , and a second contact hole 311 is opened in the gate 31 . The second contact hole 311 is used to connect to the gate metal, and the first contact hole 321 is used to connect to the source metal.

In the aforementioned power transistor with electrostatic discharge protection diode structure, the polysilicon gate region 3 is separated from the polysilicon gate bars in the active region 2 to form an independent small island structure, and both sides of the polysilicon gate region 3 are electrostatic discharge protection diodes The structure 32 has a gate 31 in the middle, which is convenient for the gate 31 to be connected with the gate metal through the second contact hole 311 , which is beneficial for batch packaging. The PN diode composed of P-type doped region and N-type doped region can simultaneously clamp the gate-source forward voltage and reverse voltage to prevent damage to power devices caused by high electrostatic voltages in different directions.

Since the working range of the gate-source bias voltage is 0-20V, when designing the gate-source ESD protection structure, the turn-on voltage should not be less than 20V, so as to prevent the ESD protection diode from turning on when the power transistor (such as VDMOS) is working normally. However, the turn-on voltage of the ESD protection device should not be too high, because if the turn-on voltage is higher than the breakdown voltage of the gate oxide layer, the ESD protection effect will not be achieved. Therefore, the setting of the turn-on voltage (total breakdown voltage) Vtrig of the ESD protection diode should meet the following principles: Vgs<Vtrig<BVox, that is, it is greater than the gate-source bias voltage and less than the breakdown voltage of the gate oxide layer. Specifically, multiple polysilicon diodes can be connected in series to increase the turn-on voltage of the ESD protection diode. In one embodiment, the number of polysilicon diodes is 3 to 6 for each of the electrostatic discharge protection diode structures 32 on both sides of the gate 31 , which can be flexibly set according to the thickness of the gate oxide.

In the embodiment shown in FIG. 1, the polysilicon gate region 3 is surrounded by the active region 2 and the termination region 1, wherein three sides of the polysilicon gate region 3 are surrounded by the active region 2, and the remaining side is formed by the termination region 1 encircled.

In the embodiment shown in FIG. 2 , the doping type of the gate 31 is N-type, so the outermost doped regions in the ESD protection diode structure 32 on both sides of the gate 31 are N-type doped regions. Moreover, the size of the N-type doped region in the Y-axis direction is larger than other N-type doped regions because the first contact hole 321 is to be provided.

In the embodiment shown in FIG. 2 , the widths of the P-type doped regions and the N-type doped regions are equal, and the width here refers to the direction of the X-axis in FIG. 2 . The size of each P-type doped region in the Y-axis direction is greater than the size of each N-type doped region in the Y-axis direction, because the doping concentration of the N-type doped region is greater than that of the P-type doped region.

FIG. 3 is a schematic plan view of the gate 31 in another embodiment. In the embodiment shown in FIG. 3 , the side a of the gate 31 adjacent to the terminal region 1 protrudes outward so that the width of the gate 31 is greater than the widths of the P-type doped region and the N-type doped region. And in this embodiment, the side b opposite to a is flush with the corresponding sides of the P-type doped region and the N-type doped region.

The total length of the P-type doped region and the N-type doped region of the ESD protection diode structure 32 affects the magnitude of the HBM (Human Body Model) voltage. The anti-ESD index of general power devices is required to reach above HBM 2000V. The anti-ESD ability of power devices is related to the total length of the P-type doped region and the N-type doped region. The larger the total length, the greater the anti-ESD ability, but the total length will increase the gate-source leakage Igss. For the embodiment in which the electrostatic discharge protection diode structure 32 on both sides of the gate 31 has five polysilicon diodes, when the widths of the P-type doped region and the N-type doped region (the X-axis direction in FIG. 3 ) are all 180 microns At the same time, the HBM can reach 14KV, which is more than enough for the HBM voltage requirements, and the width of 180 microns is difficult for the packaging of large dies, which is not conducive to batch packaging. And adopt the structure shown in Fig. 3, the protruding of gate 31 can not increase the area of chip, because the outside (that is the outside of side a) usually has 30 to 50 microns of active region 2 edge grid bar of chip active area. The transition region between region 2 and terminal region 1, the upper part of this region is the gate metal for the grid voltage, and the lower part of the transition region is the terminal injection transition region, which has no cells, so that it is clever These areas are utilized to increase the gate pad area.

The above-mentioned overhanging design of the gate 31 can reduce the difficulty of packaging, is beneficial to large-scale packaging, and will not increase the gate-source leakage Igss at the same time, because the Igss leakage of the ESD protection structure is mainly determined by the logarithm of the polysilicon diode and the length of the polysilicon diode. determined, while this treatment of polysilicon shape has no effect on either of the above.

Further, in the embodiment shown in FIG. 3 , the second contact hole 311 is disposed in the area where the side a protrudes outward. Power transistors with ESD diodes (such as VDMOS) generally have smaller gates. If the second contact hole 311 is arranged at the center of the gate 31 as in FIG. 2, the bonding pad of the gate region is generally located at the center of the chip, and the existence of the second contact hole 311 will cause the metal surface of the gate region to be uneven, resulting in Difficulty in bonding. However, in the embodiment shown in FIG. 3, the second contact hole 311 is arranged in the area where the side a protrudes outwards, and an area can be vacated on the right side of the gate 31 in FIG. Pressure welding and packaging are conducive to batch packaging. Further, in the embodiment shown in FIG. 3 , the cross-section of the first contact hole 321 is a strip extending along the X-axis direction, and the cross-section of the second contact hole 311 is a strip extending along the Y-axis direction.

FIG. 4 is a schematic plan view of the device after adding polysilicon gate bars 21 in the active region 2 , and the dielectric layer, metal layer and passivation layer are not shown in FIG. 4 . A third contact hole 22 is opened on the polysilicon gate strip 21, and the third contact hole 22 is used for connecting with the gate metal. Between the dotted lines A and B and between C and D next to the third contact hole 22 are etching regions of the metal in the active region. The etched area separates the gate metal and the source metal, the peripheral areas of the active area on the dotted lines A and D are the gate metal, and the inner areas of the active area on the dotted lines B and C are the source metal. The gate-source short circuit can be avoided by separating the polysilicon gate region 3 as an island structure from the active region 2 . Because if the ESD protection diode structure 32 is connected to the polysilicon gate strip 21, since the first contact hole 321 is connected to the metal in the source region, the ESD protection diode structure 32 and the polysilicon gate strip 21 are all connected to the source, and the polysilicon gate strip 21 It is also connected to the gate through the third contact hole 22, which will cause a short circuit between the gate and the source, so that the turn-on voltage _VTH is zero, the gate-source breakdown voltage Vgs is zero, and the gate-source leakage Igss is invalid (Over). This independent small island structure of the polysilicon gate region 3 is the same for strip-shaped cells, and this should be paid more attention to for square cells.

The invention also provides a method for manufacturing a power transistor with an electrostatic discharge protection diode structure. 5 is a flowchart of a method for manufacturing a power transistor with an electrostatic discharge protection diode structure in an embodiment, including the following steps:

S110, forming a field oxide layer and a gate oxide layer on the substrate.

The gate oxide layer in the active area can be formed after forming the P-type field limiting ring in the terminal area (formed by P+ implantation, which is called the first P+ implantation in this specification) and etching the field oxide layer in the active area. preparation. In one embodiment, the gate oxide is grown by thermal oxidation. The gate oxide can be grown by a dry oxygen process, or a dry-wet-dry (dry oxygen-wet oxygen-dry oxygen) process.

S120, deposit polysilicon on the gate oxide layer and/or the field oxide layer to form a polysilicon gate.

In this embodiment, it is to deposit polysilicon, and carry out the N-type ion diffusion of polysilicon (in other embodiments, also can be to carry out N-type ion implantation to polysilicon), N-type ion can be phosphorus ion, then to polysilicon Engraving and etching to form a polysilicon gate. Referring to FIG. 4 , the polysilicon gate here includes a polysilicon gate region 3 and a polysilicon gate strip 21 . Whether the polysilicon gate region 3 is specifically arranged on the field oxide layer or the gate oxide layer can be flexibly selected according to different technological processes of each company.

S130, implanting P-type ions to form a P-well in the substrate, and forming a P-region in the polysilicon gate region due to the P-type ion implantation.

P-type impurity ions are implanted and diffused to form a P well, and the ESD protection diode structure 32 regions on both sides of the gate 31 form a P-region due to the implantation.

S140, implanting N-type ions, forming an N+ source region in the P well, and forming an ESD protection diode structure in the polysilicon gate region.

In this step, when implanting N-type ions (N+ implantation), the photoresist is used to cover the position of the P-type doped region in the electrostatic discharge protection diode structure 32, so that these regions do not have N-type impurity implantation, so in the N-type ion implantation Finally, the P-type doped regions and the N-type doped regions on both sides of the gate 31 are arranged at intervals in the first direction to form an electrostatic discharge protection diode structure 32 . Since the photoresist covering the position of the P-type doped region in the electrostatic discharge protection diode structure 32 and the N+ photoresist of the N+ source region injection blocking layer are formed at the same photolithographic level, it is different from the conventional (not The manufacturing process of the power device including the ESD protection diode structure is compatible, and the photolithography level is not increased. Compared with the traditional manufacturing method of the power device with the ESD protection structure, one photolithography level is reduced, thereby reducing the manufacturing cost.

S150, depositing a dielectric layer on the substrate and the polysilicon gate.

In this embodiment, a double-layer structure of undoped silica glass (USG) and phosphosilicate glass (PSG) is used as the dielectric layer. In other embodiments, other known dielectric layer materials and other structures (such as a single-layer dielectric layer structure) may also be used.

S160, performing contact hole photolithography and etching to form a contact hole.

The contact holes include: a second contact hole 311 for connecting to the gate metal; a first contact hole 321 for connecting to the source metal; and a third contact hole 22 for connecting to the gate metal.

S170, perform P+ implantation on the P well through the contact hole.

After the contact hole is formed, the region of the P well under the corresponding contact hole is exposed, so that P+ implantation can be performed on the P well through the contact hole. In order to reduce the problem of large gate-source Igss leakage in the conventional ESD protection structure, this embodiment adjusts the second P+ implantation usually placed between steps S140 and S150 in the traditional power device manufacturing process to be etched in the contact hole After that, the dielectric layer deposited in step S150 can block the impact of the second P+ injection on the P-type doped region in the ESD protection diode structure 32, so that it does not become a P+ region, so that Igss can be greatly reduced Leakage, so that low-cost, high-reliability power devices can be manufactured.

S180, forming a metal interconnection layer.

After filling the contact hole with metal (such as tungsten), a front metal layer is formed on the dielectric layer. After this step is completed, steps such as forming a passivation layer on the front metal layer and performing a backside process of the power transistor can also be performed.

The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (7)

1. A power transistor with an electrostatic discharge protection diode structure, comprising a termination region and an active region surrounded by the termination region, characterized in that it also includes a polysilicon gate positioned between the termination region and the active region region, the polysilicon gate region is separated from the polysilicon gate in the active region, the polysilicon gate region includes the gate and electrostatic discharge protection diode structures on both sides of the gate, the gate and the electrostatic discharge The material of the discharge protection diode structure is polysilicon, and the electrostatic discharge protection diode structure on both sides of the gate includes a plurality of P-type doped regions and a plurality of N-type doped regions, and the P-type doped regions and N-type The doped regions are arranged at intervals in a first direction, and the first direction is the direction in which the gate extends to both sides; the two sides of the polysilicon gate region are the outermost P-type doped regions or N-type doped regions. A first contact hole is opened in the gate area, and a second contact hole is opened in the gate; the polysilicon gate area is surrounded by the active area and the terminal area, and three sides of the polysilicon gate area are surrounded by the active area. region, and the remaining side is surrounded by the terminal region, the widths of each P-type doped region and N-type doped region are equal, and the direction of the width is a second direction perpendicular to the first direction, The first side of the gate adjacent to the terminal region protrudes outward so that the width of the gate is greater than the widths of the P-type doped region and the N-type doped region. 2 . The power transistor with an electrostatic discharge protection diode structure according to claim 1 , wherein the doping type of the gate is N type. 3 . 3 . The power transistor with an electrostatic discharge protection diode structure according to claim 1 , wherein the second contact hole is disposed in a region where the first side protrudes outward. 4 . 4. The power transistor with an electrostatic discharge protection diode structure according to claim 3, wherein the cross-section of the first contact hole is a long strip extending along the second direction, and the second contact The cross section of the hole is a long strip extending along the first direction. 5. the power transistor with ESD protection diode structure according to claim 1, is characterized in that, the doping concentration of each described P-type doped region is less than the doping concentration of each described N-type doped region, each The size of the P-type doped region in the first direction is greater than the size of each of the N-type doped regions in the first direction. 6. A method for manufacturing a power transistor with an electrostatic discharge protection diode structure, comprising: forming a field oxide layer and a gate oxide layer on the substrate; Polysilicon is deposited on the gate oxide layer and/or the field oxide layer to form a polysilicon gate; the polysilicon gate includes a polysilicon grid strip in an active region and a polysilicon gate region located between the active region and the terminal region , the polysilicon gate region is separated from the polysilicon gate strip in the active region; Implanting P-type ions to form a P-well in the substrate, and forming a P-region in the polysilicon gate region due to P-type ion implantation; N-type ions are implanted to form an N+ source region in the P well, and the P-region forms a plurality of P-type doped regions and N-type doped regions on both sides of the gate of the polysilicon gate region due to the N-type ion implantation. region, the P-type doped region and the N-type doped region are arranged at intervals in a first direction to form an electrostatic discharge protection diode structure, and the first direction is the direction in which the gate extends to both sides; Depositing a dielectric layer on the substrate and the polysilicon gate; Conduct contact hole photolithography and etching to form contact holes; performing P+ implantation on the P well through the contact hole; forming a metal interconnection layer; Wherein, the polysilicon gate region is surrounded by the active region and the termination region, three sides of the polysilicon gate region are surrounded by the active region, and the remaining side is surrounded by the termination region, each P-type The widths of the doped region and the N-type doped region are equal, the direction of the width is a second direction perpendicular to the first direction, and the first side of the gate adjacent to the terminal region protrudes outward The width of the gate is greater than the widths of the P-type doped region and the N-type doped region. 7. The method for manufacturing a power transistor with an electrostatic discharge protection diode structure according to claim 6, characterized in that, before the step of implanting P-type ions, it also includes performing N-type ion diffusion on the polysilicon grid. Step, the doping type of the gate of the polysilicon gate region is N type.

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