CN106098782B - A kind of production method of P channel VDMOS device - Google Patents

Abstract

The invention discloses a production method of a P-channel VDMOS device, which comprises forming an oxide layer on the epitaxial layer, covering the oxide layer with a photoresist layer, and then injecting N-type impurities with glue; The required N-type base junction depth step; the boron impurity implantation step on the oxide layer; the gate oxide layer is formed on the epitaxial layer, and then polysilicon deposition and doping are performed on the gate oxide layer, and the polysilicon gate is used again Step of forming polysilicon gate layer with photolithography plate; covering photoresist in a local area of gate oxide layer, then directly performing source P+ processing, forming P+ region step in N-type base region; and finally depositing inner metal insulating layer, at the same time The upper surface and the lower surface of the epitaxial layer are respectively provided with a metal layer to form a standard VDMOS device step. The production method of the above-mentioned P-channel VDMOS device can stabilize the Vth value of the P-channel VDMOS device between 2 and 4V, which has extremely high stability and rationality.

Description

A kind of production method of P channel VDMOS device

technical field

The invention relates to a production method of a P-channel VDMOS device, which belongs to the field of semiconductor production.

Background technique

At present, the production process of P-channel VDMOS devices is basically the same as that of N-channel VDMOS devices, as follows:

In the VTH formation process of N-type VDMOS devices, after the gate oxide growth and polysilicon gate etching are completed, a certain dose of P-type impurities is first implanted through the polysilicon gate self-alignment process, and then annealed at high temperature to form a P-type with a certain junction depth. The base region, and then use the polycrystalline gate self-alignment process to perform source N+ high-dose implantation and annealing. In this way, the channel is formed by the difference in the second lateral diffusion junction depth between the P-type base region and the N+ source region, and finally VTH The size is determined by the gate oxide thickness and the maximum compensation impurity concentration in the channel. The maximum compensation concentration is generally located in the P-type base region near the N+ junction of the P-type base region. For N-type VDMOS, after the gate oxide thickness is fixed, the required VTH value can be easily adjusted by adjusting the dose of P-type impurities. Currently, the VTH of N-type VDMOS is generally controlled between 2 and 4V, and the central value is required to be 3.0 Both V and N-type VDMOS products can be satisfied. It seems that the realization of this parameter is not a difficult task, but the same process is used in the P-type VDMOS process, and the result is not ideal. From the surface comparison, the P-type VDMOS Only the base area is replaced with N-type impurities, and the source area is changed from N+ to P+. The layout and structure are the same as N-type VDMOS. Using the same dose of implanted impurities (phosphorus and boron) in the base area, the same base annealing time, the same gate oxide thickness, and the same layout, but the corresponding impurity types are changed, and the results are very different. For N-channel Channel VDMOS, its VTH is only 4V, and P-channel VDMOS, its VTH has reached 12V, the difference is nearly three times. The main reasons for the large Vth of P-channel VDMOS devices produced by the current conventional process flow are as follows:

A: The high-temperature heat treatment process causes heavily doped phosphorus impurities in polysilicon to easily cross the gate oxide and reach the channel surface, resulting in the accumulation of similar impurities, which directly leads to a larger Vth;

B: The influence of oxide charge, especially the high temperature process after the gate oxide will lead to positive oxide charge accumulation, and positive oxidation charge will cause the Vth of P-channel VDMOS to increase;

C: There is a difference in the diffusion coefficients of the two base impurities. The base area of the N-channel VDMOS is boron impurities. The boron impurities have a large diffusion coefficient due to their small atomic coefficients. At the same temperature and time, the impurities tend to move laterally and Move vertically, so that impurities will not accumulate on the surface, and the base region of P-channel VDMOS is phosphorus impurities. The atomic coefficient of phosphorus impurities is large, so the diffusion coefficient is small. Compared with boron impurities, the same temperature and Over time, impurities are more likely to accumulate on the surface, resulting in an excessively high concentration on the surface, which is also an important factor for the high VTH of the P-channel VDMOS.

In view of this, the inventor of the present invention conducted research on this and specially developed a production method for a P-channel VDMOS device, from which this case arose.

Contents of the invention

The purpose of the present invention is to provide a kind of P channel VDMOS device production method, can utilize the current ready-made N channel VDMOS device layout to carry out development and flow, realize that the Vth value of P channel VDMOS device is stable between 2 ~ 4V, has Extremely high stability and rationality.

In order to achieve the above object, the solution of the present invention is:

A kind of P channel VDMOS device production method, comprises the steps:

Step 1), after the active area of the epitaxial layer is opened, thin oxygen growth is carried out to form an oxide layer, and the photoresist layer is covered on the oxide layer, and the glue is partially removed according to the design requirements, and then the polycrystalline gate photolithography plate is used for stripping Glue N-type impurity injection;

Step 2), remove the remaining photoresist on the oxide layer, and form the required N-type base junction depth on the upper surface of the epitaxial layer after high-temperature annealing;

Step 3), boron impurity implantation is performed on the oxide layer, and a JFET region is formed between the junction depths of the N-type base region. The implantation of boron impurities reduces the surface concentration of the N-type base region on the one hand to meet the VTH value required by the design, and on the other hand Increase the doping concentration of the JFET region to reduce the JFET resistance;

Step 4), rinse off the oxide layer, perform normal gate oxide growth on the epitaxial layer to form a gate oxide layer, then deposit and dope polysilicon on the gate oxide layer, and use the polysilicon gate photolithography plate to form polysilicon again For the gate layer, since the high-temperature pushing junction required by the N-type base region has been completed before the gate oxide, high-temperature treatment is no longer required after the gate oxide.

Step 5), cover the local area of the gate oxide layer with photoresist, and then directly process the source P+ to form a P+ region in the N-type base region. When the source P+ region is implanted, the boundary on one side is polysilicon, and the other side is covered with photoresist Define the short-circuit part of the P+ source and the N-type base region;

Step 6), finally deposit an inner metal insulating layer to cover the polysilicon gate and a thicker PSG/BPSG film and perform reflow treatment, and at the same time set a metal layer on the upper surface and lower surface of the epitaxial layer as the source and drain, Form a standard VDMOS device.

The production method of the P-channel VDMOS device of the present invention can realize that the Vth value of the P-channel VDMOS device is stable between 2 and 4V. It has the following advantages:

1) The annealing of the high-temperature base region is placed before the growth of the gate oxide, which avoids the high-temperature annealing after the gate oxide of the N-type VDMOS process. In this way, there is no high-temperature process after the gate oxide polycrystalline doping, so there is no need to worry about the polycrystalline The heavily doped N+ in the gate will run to the silicon surface (epitaxial layer) under the gate oxide. In addition, there is no high-temperature heat treatment after the gate oxide, which reduces the positive charge of the oxide layer and avoids negative effects on VTH;

2) The production method described in the present invention almost avoids all the negative impacts on VTH being too large. Although the cost of photolithography is increased once, the performance is greatly improved;

3) Although the conventional polysilicon gate self-alignment process is not used for the implantation of the mid-base region, due to the large number of applications of stepper lithography machines, the deviation of the secondary alignment before and after the front and rear is within 0.2um. In fact, the injection with glue The effect is almost the same as that of polycrystalline gate self-alignment implantation, and there is no need to worry about affecting the cell structure.

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

Description of drawings

FIG. 1 is a schematic structural diagram of a P-channel VDMOS device after step 1) of this embodiment;

FIG. 2 is a schematic structural diagram of a P-channel VDMOS device after step 2) of this embodiment;

FIG. 3 is a schematic structural diagram of a P-channel VDMOS device after step 3) of this embodiment;

FIG. 4 is a schematic structural diagram of a P-channel VDMOS device after step 4) of this embodiment;

FIG. 5 is a schematic structural diagram of a P-channel VDMOS device after step 5) of this embodiment;

FIG. 6 is a schematic diagram of the structure of a P-channel VDMOS device after step 6) of this embodiment.

Detailed ways

A kind of P channel VDMOS device production method, comprises the steps:

Step 1), after the active area of the epitaxial layer 1 is opened, thin oxygen growth is performed first to form the oxide layer 2, and then the photoresist layer 3 is covered on the oxide layer 2, and the glue is partially removed according to the design requirements, and then the polycrystalline gate is used The photolithographic plate is injected with N-type impurities (ph+) with glue, as shown in Figure 1;

Step 2), remove the remaining photoresist on the oxide layer 2, and form the required N-type base junction depth on the upper surface of the epitaxial layer 1 after high-temperature annealing, as shown in Figure 2;

Step 3) Carry out a comprehensive low-dose implantation of boron impurities (B+) on the oxide layer 2, and form a JFET region between the junction depths of the N-type base region, as shown in Figure 3. On the one hand, the comprehensive low-dose implantation of boron impurities reduces the N The surface concentration of the N-type base region meets the set required VTH value, on the other hand, the doping concentration of the JFET region located between the N-type base regions is increased to reduce the JFET resistance;

Step 4), rinse off the oxide layer 2, perform normal gate oxide growth on the epitaxial layer 1 to form a gate oxide layer 4, and then perform polysilicon deposition and doping on the gate oxide layer 4, and use the polysilicon gate light again The polysilicon gate layer 5 is formed by engraving, as shown in FIG. 4 , since the high-temperature push junction required by the N-type base region is completed before the gate oxide, so high-temperature treatment is no longer required after the gate oxide. The annealing of the high-temperature base region is placed before the growth of the gate oxide to avoid the high-temperature annealing after the gate oxide of the N-type VDMOS process. In this way, since there is no high-temperature process after the gate oxide polycrystalline doping, there is no need to worry about heavy Doping N+ will run to the silicon surface (epitaxial layer 1) under the gate oxide layer 4. In addition, there is no high-temperature heat treatment after the gate oxide layer, which reduces the positive charge of the gate oxide layer 4 and avoids negative effects on the VTH value;

Step 5), cover the photoresist 6 in the partial area of the gate oxide layer 4, and then directly perform source P+ processing to form a P+ region in the N-type base region. As shown in Figure 5, the boundary on one side when the source P+ region is implanted is Polysilicon, on the other side, use photoresist to define the short-circuit part of the P+ source and the N-type base region;

Step 6), finally deposit the inner metal insulating layer 7 to cover the polysilicon gate layer 5 and the thicker PSG/BPSG film (the inner metal insulating layer 7) and perform reflow treatment, and at the same time set the upper surface and the lower surface of the epitaxial layer respectively Metal layer 8, as source and drain, forms a standard VDMOS device.

The applicant used the existing N-type VDMOS device 30N60 photolithography plate to process the P-type VDMOS device 10P60. After the production method described in this embodiment, the first-time flow was successful, and the VTH was controlled within the requirements. The data are shown in Table 1:

Table 1:

The VTH design requirement is the central value of 2.5V, and the actual flow results are fully satisfied! In addition, it can also be found from the RDON data that the RDON of a normal 30N60 is about 35 milliohms, and as a P-type product with 60V running water, its RDON is about 100 milliohms, which is three times that of similar N-type products, which is completely in line with the theory.

By adopting the production method of the P-channel VDMOS device described in this embodiment, the Vth value of the P-channel VDMOS device can be stabilized between 2V and 4V. Although the conventional polysilicon gate self-alignment process is not used for base region implantation, due to the extensive application of stepper lithography machines, the front and rear secondary alignment deviations are within 0.2um. The effect of self-aligned injection is almost the same, so there is no need to worry about affecting the cell structure. The production method described in the present invention almost avoids all negative influences on VTH being too large, and although the photolithography cost is increased once, the performance is greatly improved.

The above-mentioned embodiments and drawings do not limit the form and style of the product of the present invention, and any appropriate changes or modifications made by those skilled in the art should be considered as not departing from the patent scope of the present invention.

Claims (1)

1. a kind of P-channel VDMOS device production method, it is characterised in that include the following steps:

After step 1), epitaxial layer active area are opened, thin oxide growth is carried out, oxide layer is generated, covers photoresist again in oxide layer Layer, and locally removed photoresist according to design requirement, band glue N-type impurity is then carried out using polysilicon gate reticle and is injected；

Step 2 removes remaining photoresist on removing oxide layer, N-type base required for being formed after high annealing in epitaxial layer upper surface Area's junction depth；

Step 3) carries out boron impurity injection in oxide layer, forms the area JFET between N-type base junction depth；

Step 4) rinses oxide layer, and normal gate oxide growth is carried out on epitaxial layer, grid oxide layer is generated, then in grid oxide layer Upper progress polysilicon deposit and doping, and polycrystalline silicon grid layer is formed using polysilicon gate reticle again；

Step 5), the regional area covering photoresist in grid oxide layer, then directly carry out source P+ processing, form P in N-type base area + area；

Step 6) deposits interior metal dielectric layer finally to cover polysilicon gate and thicker PSG/BPSG film and carry out at reflux Reason, while metal layer is respectively set in the upper and lower surfaces of epitaxial layer, as source electrode and drain electrode, form the VDMOS of standard Device.