CN106100613B - Current Controlled Oscillators and Ring Oscillators - Google Patents

Abstract

The invention discloses a kind of current control oscillator and ring oscillator, which includes ring oscillator and oscillation frequency control circuit.There is ring oscillator a normal phase connection configuration configuration is connected with a leading phase, and including an input terminal, at least level Four Postponement module and one group of oscillation frequency signal output end.The frequency of oscillation that ring oscillator is configured to the oscillation frequency signal exported when leading phase connection configuration is greater than the frequency of oscillation that ring oscillator is configured to the oscillation frequency signal exported when normal phase connection configuration.Oscillation frequency control circuit is inputted according to received bias current, digital controlled signal and control voltage input generate a driving current signal.Oscillation frequency control circuit output driving current signal to ring oscillator input terminal, with adjust ring oscillator output oscillation frequency signal frequency of oscillation.

Description

Current Controlled Oscillators and Ring Oscillators

technical field

The present invention relates to current controlled ring oscillators, and more particularly to current controlled ring oscillators using dual delay paths.

Background technique

Ring oscillators are key components in clock and data restorers used in radio frequency circuits. The oscillation frequency of the ring oscillator often depends on the total number of stages of delay modules connected in series in the ring oscillator and the delay time of each delay module. For example, as the total number of stages of delay modules increases, the oscillation frequency of the ring oscillator decreases. At present, ring oscillators are mostly voltage-controlled ring oscillators, that is, each delay module that outputs a control voltage to the ring oscillator. In view of this, the present invention proposes a current-controlled ring oscillator from another viewpoint to increase the adjustment range of the oscillation frequency.

SUMMARY OF THE INVENTION

An exemplary embodiment of the present invention provides a current controlled oscillator. The current controlled oscillator includes a ring oscillator and an oscillation frequency control circuit. The ring oscillator has a first phase connection configuration and a second phase connection configuration. The ring oscillator includes at least four stages of delay modules, an input end and a group of oscillating frequency signal output ends. Each of the delay modules has a control signal input terminal, a ground terminal, a first group of signal input terminals, a second group of signal input terminals and a first group of signal output terminals. The input terminal of the ring oscillator is coupled to the control signal input terminal of each delay module. The set of oscillating frequency signal output terminals is coupled to the first set of signal output terminals of the last stage delay module of the ring oscillator for outputting a set of oscillating frequency signals of the current controlled oscillator, wherein when the ring oscillator When configured in the first phase connection configuration, the first set of signal output terminals of each delay module is coupled to the first set of signal input terminals of the next stage delay module, and the first set of signal input terminals of the last stage delay module A group of signal output terminals are coupled to the first group of signal output terminals of the first stage delay module; wherein if the ring oscillator is changed from the first phase connection configuration to the second phase connection configuration, each delay The first group of signal output terminals of the module is also coupled to the second group of signal input terminals of the next stage delay module; and wherein if the ring oscillator is changed from the first phase connection configuration to the second phase connection configuration configuration, the first group of signal output terminals of the penultimate stage delay module is further coupled to the second group of signal input terminals of the first stage delay module, and the first group of signal output terminals of the last stage delay module is also is coupled to the second group of signal input terminals of the second stage delay module. The oscillation frequency control circuit is coupled to the ring oscillator, wherein the oscillation frequency control circuit receives an external bias current input, a digital control signal and a control voltage input, and according to the bias current input, the digital control signal and the control voltage input to generate a drive current signal; and wherein the oscillation frequency control circuit outputs the drive current signal to the control signal input end of each of the delay modules of the ring oscillator to adjust the set of ring oscillators An oscillation frequency of the oscillation frequency signal.

An exemplary embodiment of the present invention provides a ring oscillator. The ring oscillator has a first phase connection configuration and a second phase connection configuration. The ring oscillator includes at least four stages of delay modules, an input end and a group of oscillating frequency signal output ends. Each of the delay modules has a control signal input terminal, a ground terminal, a first group of signal input terminals, a second group of signal input terminals and a first group of signal output terminals. The input terminal of the ring oscillator is coupled to the control signal input terminal of each delay module. The set of oscillating frequency signal output terminals is coupled to the first set of signal output terminals of the last stage delay module of the ring oscillator for outputting a set of oscillating frequency signals of the current controlled oscillator, wherein the first set of signals The input end includes a first polarity signal input end and a second polarity signal input end, the second group of signal input ends includes a first polarity signal input end and a second polarity signal input end, and the first polarity signal input end A set of signal output terminals includes a first polarity signal output terminal and a second polarity signal output terminal; wherein when the ring oscillator is configured in the first phase connection configuration, the first phase connection of each delay module The first polarity signal output terminal of the group signal output terminal is coupled to the first polarity signal input terminal of the first group signal input terminal of the next stage delay module, and the first group signal output terminal of each delay module The second polarity signal output end of the terminal is coupled to the second polarity signal input end of the first group of signal input ends of the next stage delay module; wherein when the ring oscillator is configured as the first phase connection configuration , the first polarity signal output terminal of the first group of signal output terminals of the last stage delay module is coupled to the second polarity signal input terminal of the first set of signal output terminals of the first stage delay module, and the last The second polarity signal output terminal of the first group of signal output terminals of the stage delay module is coupled to the first polarity signal input terminal of the first group of signal output terminals of the first stage delay module; wherein if the ring oscillator When the configuration is changed from the first phase connection configuration to the second phase connection configuration, the first group of signal output terminals of each delay module is also coupled to the second group of signal input terminals of the next-stage delay module; and wherein if the ring oscillator is changed from the first phase connection configuration to the second phase connection configuration, the first group of signal output ends of the penultimate stage delay module is further coupled to the first stage delay module The second group of signal input terminals, and the first group of signal output terminals of the last stage delay module is also coupled to the second group of signal input terminals of the second stage delay module.

Description of drawings

FIG. 1 is a block diagram of implementing a current controlled oscillator 1 according to an embodiment of the present invention.

FIG. 2A illustrates a schematic diagram of ring oscillator 2 configured in a first phase connection configuration according to an embodiment of the present invention.

FIG. 2B illustrates a schematic diagram illustrating the configuration of the ring oscillator 2 in the second phase connection configuration according to an embodiment of the present invention.

FIG. 2C illustrates a schematic diagram of ring oscillator 2 configured in a first phase connection configuration according to an embodiment of the present invention.

2D illustrates a schematic diagram illustrating the configuration of the ring oscillator 2 in the second phase connection configuration according to an embodiment of the present invention.

FIG. 2E illustrates a schematic diagram of ring oscillator 2 configured in a third phase connection configuration according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of implementing the delay module 21 of the ring oscillator 2 according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of realizing the oscillation frequency control circuit 3 according to an embodiment of the present invention.

Detailed ways

The illustrated embodiments or examples of the present invention will be described below. The scope of the present invention is not limited thereto. Those skilled in the art should be aware that some changes, substitutions and substitutions can be made without departing from the spirit and structure of the present invention. In the embodiments of the present invention, reference numerals may be used repeatedly, and several embodiments of the present invention may share the same reference numerals, but characteristic elements used in one embodiment are not necessarily used in another embodiment.

FIG. 1 is a block diagram of implementing a current controlled oscillator 1 according to an embodiment of the present invention. In the embodiment of FIG. 1 , the current controlled oscillator 1 includes a ring oscillator 2 and an oscillation frequency control circuit 3 . The ring oscillator 2 is coupled to the oscillation frequency control circuit 3 and has at least a first phase connection configuration and a second phase connection configuration. The ring oscillator 2 receives a driving current signal Sci from the oscillation frequency control circuit 3, and outputs a group of oscillation frequency signals Sf according to the driving current signal Sci. The oscillation frequency control circuit 3 receives an external bias current input Ib1, a digital control signal d<M:0> and a control voltage input Vcn, and outputs the driving current signal Sci accordingly.

In the embodiment of FIG. 1 , the oscillation frequency control circuit 3 includes a frequency adjustment circuit 31 and an oscillator drive circuit 32 . The frequency adjustment circuit 31 receives an external bias current input Ib1 and a digital control signal d<M:0>, and then generates a first control current signal Ic1 according to the digital control signal d<M:0>. The oscillator driving circuit 32 receives an external control voltage input Vcn, and then generates a second control current signal Ic2 according to the control voltage input Vcn. An output end of the frequency adjustment circuit 31 and an output end of the oscillator driving circuit 32 are both coupled to an output end of the oscillation frequency control circuit 3, so that the first control current signal Ic1 is added to the second control current signal Ic2 to form a drive Current signal Sci. In the embodiment of FIG. 1 , by inputting different digital control signals d<M:0>, an oscillation frequency fc of the group of oscillation frequency signals Sf output by the current controlled oscillator 1 has multiple frequency ranges. In addition, the oscillation frequency fc can also be adjusted by changing the control voltage input Vcn.

FIG. 2A illustrates a schematic diagram of ring oscillator 2 configured in a first phase connection configuration according to an embodiment of the present invention. In an embodiment of the present invention, the ring oscillator 2 includes an input terminal 201 , a set of oscillating frequency signal output terminals 202 and 203 , and a four-stage series-connected delay module 21 , delay module 22 , delay module 23 and delay module 24 . Each of the delay modules 21-24 is the same delay module. Each of the delay modules 21-24 has a control signal input terminal T1, a ground terminal T2, a first group of signal input terminals (vin+, vin-), a second group of signal input terminals (vip+, vip-), and A first group of signal output terminals (vo+, vo-). The input terminal 201 of the ring oscillator 2 is used for receiving a driving current signal Sci from the oscillation frequency control circuit 3, and the oscillation frequency signal output terminals 202 and 203 of the ring oscillator 2 are used for outputting the group of oscillation frequency signals Sf. The control signal input terminal T1 of each delay module 21-24 is coupled to the input terminal 201, and the ground terminal T2 of each delay module 21-24 is electrically connected to a ground potential.

In the embodiment of FIG. 2A, the first group of signal input terminals includes a first polarity signal input terminal vin+ and a second polarity signal input terminal vin-. The second group of signal input terminals includes a first polarity signal input terminal vip+ and a second polarity signal input terminal vip-. The first group of signal output terminals includes a first polarity signal output terminal vo+ and a second polarity signal output terminal vo-.

In the embodiment of FIG. 2A , the ring oscillator 2 is configured in the first phase connection configuration, wherein the first phase connection configuration is a normal phase connection. At this time, the first group of signal output terminals of each delay module 21-24 is coupled to the first group of signal input terminals of the next stage delay module, and the last stage delay module (ie delay module 24) The first group of signal output terminals is coupled to the first group of signal output terminals of the first stage delay module (ie, the delay module 21 ).

In more detail, when the ring oscillator 2 is configured in the first phase connection configuration, the first polarity signal output terminal vo+ of the first group of signal output terminals of each of the delay modules 21-23 is coupled to the next The first polarity signal input terminal vin+ of the first set of signal input terminals of the stage delay modules 22-24, and the second polarity signal output terminal vo of the first set of signal output terminals of each of the delay modules 21-23 - coupled to the second polarity signal input terminal vin- of the first group of signal input terminals of the next stage delay modules 22-24.

In more detail, when the ring oscillator 2 is configured in the first phase connection configuration, the first polarity signal output terminal vo+ of the first group of signal output terminals of the last stage delay module 24 is coupled to the first stage The second polarity signal input terminal vin- of the first set of signal output terminals of the delay module 21, and the second polarity signal output terminal vo- of the first set of signal output terminals of the last stage delay module 24 is coupled to The first polarity signal input terminal vin+ of the first group of signal output terminals of the first stage delay module 21 .

FIG. 2B illustrates a schematic diagram illustrating the configuration of the ring oscillator 2 in the second phase connection configuration according to an embodiment of the present invention. In the embodiment of FIG. 2B , the ring oscillator 2 is configured in the second phase connection configuration, wherein the second phase connection configuration is a leading phase connection. When the ring oscillator 2 is configured in an advanced phase connection, the first group of signal output terminals of each of the delay modules 21-24 are coupled to the first group of signal input terminals of the next stage delay module, It is also coupled to the second group of signal input terminals (vip+, vip-) of the delay module after the next stage.

Taking the second phase connection group configured in the second phase connection configuration shown in FIG. 2B as an example, the first group of signal output terminals of each delay module 21-24 is also coupled to the first group of the delay module of the next stage. A set of signal input terminals, and the first set of signal output terminals of the last stage delay module (ie delay module 24 ) are also coupled to the first set of signal outputs of the first stage delay module (ie delay module 21 ) end. Different from the first phase connection configuration shown in FIG. 2A, the first group of signal outputs of each delay module 21-22 is also coupled to the second group of signal inputs of the next-stage delay module 23-24 terminal, the first set of signal output terminals of the penultimate stage delay module (ie delay module 23 ) is also coupled to the second set of signal output terminals of the first stage delay module (ie delay module 21 ), and finally The first group of signal output terminals of the first stage delay module (ie delay module 24 ) is also coupled to the second group of signal output terminals of the second stage delay module (ie delay module 22 ).

In more detail, when the configuration is changed from the first phase connection configuration to the second phase connection configuration, the first polarity signal output terminal vo+ of the first group of signal output terminals of each of the delay modules 21-22 is further coupled to connected to the first polarity signal input terminal vip+ of the second group of signal input terminals of the next stage delay module 23-24, and the second polarity of the first group of signal output terminals of each delay module 21-22 The polarity signal output terminal vo- is also coupled to the second polarity signal input terminal vip- of the first group of signal input terminals of the next stage delay modules 23-24.

In more detail, when the configuration is changed from the first phase connection configuration to the second phase connection configuration, the first polarity signal output of the first group of signal output terminals of the last stage delay module (ie delay module 24 ) The terminal vo+ is also coupled to the first polarity signal input terminal vip- of the second set of signal input terminals of the second stage delay module 22, and the first set of signals of the last stage delay module (ie, the delay module 24) The second-polarity signal output terminal vo- of the output terminal is further coupled to the first-polarity signal input terminal vip+ of the second group of signal input terminals of the second-stage delay module 22 .

In more detail, when the configuration is changed from the first phase connection configuration to the second phase connection configuration, the first polarity of the first group of signal output terminals of the penultimate stage delay module (ie delay module 23 ) The signal output terminal vo+ is also coupled to the second polarity signal input terminal vip- of the first group of signal input terminals of the first stage delay module 21 , and the second polarity signal input terminal vip- of the penultimate stage delay module (ie the delay module 23 ) The second polarity signal output terminal vo- of a group of signal output terminals is also coupled to the first polarity signal input terminal vip+ of the first group of signal input terminals of the first stage delay module 21 .

Compared with the first phase connection configuration shown in FIG. 2A , the second phase connection configuration shown in FIG. 2B provides the input of the second group of signal input terminals (vip+, vip-) of each of the delay modules 21 to 24 faster than the original one. Inputs at the first set of signal input terminals (vin+, vin-). On the other hand, the second phase connection configuration shown in FIG. 2B provides each delay module 21-24 with a new connection from the second group of signal input terminals (vip+, vip-) to the first group of signal output terminals (vo+, vo-). , so that each delay module 21-24 has a dual delay path. Thereby, the delay time of the signal in a single delay module is reduced. Therefore, the set of oscillation frequency signals Sf output by the ring oscillator 2 configured in the second phase connection configuration can have a higher oscillation frequency fc.

It should be noted that the ring oscillator 2 shown in the present invention is not limited to the four-stage delay modules 21-24. The ring oscillator 2 may also include N stages of delay modules 21 , delay modules 22 , . . . , delay modules 2 (N−1) to delay modules 2N, where N is any positive integer greater than 3.

It should be noted that the ring oscillator 2 shown in the present invention does not limit the leading phase connection manner of the second phase connection configuration. In another embodiment of the present invention, when the ring oscillator 2 is configured in an advanced phase connection manner, the first group of signal output terminals of each delay module 21 - 2N are coupled to the signal output terminals of the next stage delay module in addition to In addition to the first group of signal input terminals, it is also coupled to the second group of signal input terminals (vip+, vip-) of the delay modules after stage P, where P is any positive integer less than (N/2). For example, when N is 7, P can be 1, 2, 3; when N is 4, P can be 1; when N is 6, P can be 1, 2; when N is 12, P can be 1, 2, 3, 4, 5; when N is 20, P can be a positive integer less than 10.

In more detail, when the ring oscillator 2 has seven stages of delay modules 21-27, the ring oscillator 2 has a third phase connection in addition to the aforementioned first phase connection configuration and the aforementioned second phase connection configuration configuration and a fourth phase connection configuration.

2C-2E illustrate different phase connection configurations of a ring oscillator 2 having seven stages of delay modules 21-27 according to an embodiment of the present invention.

FIG. 2C illustrates a schematic diagram of ring oscillator 2 configured in a first phase connection configuration according to an embodiment of the present invention. In the embodiment of FIG. 2C , the ring oscillator 2 is configured in the first phase connection configuration, ie in the normal phase connection. At this time, the connection mode of the delay modules 21-27 is the same as the connection mode of the delay modules 21-24 shown in FIG. 2A, and the difference is only that the total number of stages N of the delay modules is different.

2D illustrates a schematic diagram illustrating the configuration of the ring oscillator 2 in the second phase connection configuration according to an embodiment of the present invention. In the embodiment of Figure 2D, the ring oscillator 2 is configured in this second phase connection configuration. At this time, the connection mode of the delay modules 21-27 is the same as the connection mode of the delay modules 21-24 shown in FIG. 2B , and the difference is only in that the total number of stages N of the delay modules is different. In other words, the first group of signal output terminals of each of the delay modules 21-25 are coupled to the first group of signal input terminals (vin+, vin-) of the next stage delay module, and are also coupled to To the second group of signal input terminals (vip+, vip-) of the delay module after the first stage. For example, the first group of signal output terminals of the delay module 23 are coupled to the first group of signal input terminals (vin+, vin-) of the delay module 24 and the second group of signal input terminals (vip+, vip) of the delay module 25 -). The first group of signal output terminals of the delay module 26 are not only coupled to the first group of signal input terminals (vin+, vin-) of the next stage delay module 27, but also coupled to the first stage delay module 21. The second group of signal input terminals (vip+, vip-). The first group of signal output terminals of the delay module 27 are not only coupled to the first group of signal input terminals (vin+, vin-) of the first stage delay module 21 , but also coupled to the second stage delay module 22 . The second group of signal input terminals (vip+, vip-).

FIG. 2E illustrates a schematic diagram of ring oscillator 2 configured in a third phase connection configuration according to an embodiment of the present invention. In the embodiment of Figure 2E, the ring oscillator 2 is configured in this third phase connection configuration. At this time, the first group of signal output terminals (vo+, vo-) of each of the delay modules 21-24 are not only coupled to the first group of signal input terminals (vin+, vin-) of the next stage delay module, but also It is coupled to the second group of signal input terminals (vip+, vip-) of the delay modules after the second stage. For example, the first group of signal output terminals of the delay module 23 are coupled to the first group of signal input terminals (vin+, vin-) of the delay module 24 and the second group of signal input terminals (vip+, vip) of the delay module 26 -).

In the embodiment shown in FIG. 2E , the first group of signal output terminals (vo+, vo-) of the delay module 25 are not coupled to the first group of signal input terminals (vin+, vin-) of the next stage delay module 26 In addition, it is also coupled to the second group of signal input terminals (vip+, vip-) of the first stage delay module 21 . The first group of signal output terminals (vo+, vo-) of the delay module 26 are not only coupled to the first group of signal input terminals (vin+, vin-) of the next stage delay module 27, but also coupled to the first group of signal input terminals (vin+, vin-). The second group of signal input terminals (vip+, vip-) of the second-level delay module 22 . The first group of signal output terminals (vo+, vo-) of the delay module 27 are not only coupled to the first group of signal input terminals (vin+, vin-) of the first stage delay module 21, but also coupled to the first group of signal input terminals (vin+, vin-). The second group of signal input terminals (vip+, vip-) of the three-stage delay module 23 .

It is worth noting that the first group of signal output terminals (vo+, vo-) of the delay modules 25-27 are respectively coupled to the second group of signal input terminals (vip+, vip-) of the delay modules 21-23 in opposite phases. In more detail, the first-polarity signal output terminal vo+ of the first group of signal output terminals of the delay module 25 is coupled to the second-polarity signal input terminal vip- of the second group of signal input terminals of the delay module 21 , and the delay module 25 The second polarity signal output terminal vo- of the first group of signal output terminals of the The first polarity signal output terminal vo+ of the delay module 22 is coupled to the second polarity signal input terminal vip- of the second group of signal input terminals of the delay module 22 , and the second polarity signal output terminal of the first group of signal output terminals of the delay module 26 vo- is coupled to the first polarity signal input terminal vip+ of the second group of signal input terminals of the delay module 22; similarly, the first polarity signal output terminal vo+ of the first group of signal output terminals of the delay module 27 is coupled to the delay module The second polarity signal input terminal vip- of the second group of signal input terminals of 23, and the second polarity signal output terminal vo- of the first group of signal output terminals of the delay module 27 is coupled to the second group of signal inputs of the delay module 23 The first polarity signal input terminal vip+ of the terminal.

Therefore, the ring oscillator 2 of the present invention obtains the set of oscillating frequency signals Sf with different oscillating frequencies fc through three different phase connection configurations shown in Figs. 2C-2E.

FIG. 3 is a circuit diagram of implementing the delay module 21 of the ring oscillator 2 according to an embodiment of the present invention. Since each delay module of the ring oscillator 2 has the same circuit structure, only the delay module 21 is used as an illustration below. In the embodiment of FIG. 3, the delay module 21 includes a first delay transistor pair (Md1, Md2), a load transistor pair (Md3, Md4), a second delay transistor pair (Md5, Md6), a third delay transistor pair (Md5, Md6) Delay transistor pair (Md7, Md8) and bias transistors Md9-Md16.

In the embodiment of FIG. 3 , the first delay transistor pair (Md1, Md2) is respectively coupled to the first group of signal input terminals (vin+, vin-) and the first group of signal output terminals (vo+, vo-), and includes a first transistor Md1 and a second transistor Md2. A gate of the first transistor Md1 and a gate of the second transistor Md2 are respectively coupled to the first-polarity signal input terminal vin+ and the second-polarity signal input terminal vin- of the first group of signal input terminals. A source of the first transistor Md and a source of the second transistor Md are respectively coupled to the first-polarity signal output terminal vo+ and the second-polarity signal output terminal vo- of the first group of signal output terminals.

In the embodiment of FIG. 3, the second delay transistor pair (Md5, Md6) includes a fifth transistor Md5 and a sixth transistor Md6. A gate Md5 of the fifth transistor and a gate of the sixth transistor Md6 are coupled to the first polarity signal input terminal vip+ of the second group of signal input terminals, and a drain of the first transistor and a drain of the fifth transistor Both the pole and a drain of the sixth transistor are coupled to the second polarity signal output terminal vo- of the first group of signal output terminals. The third delay transistor pair (Md7, Md8) includes a seventh transistor Md7 and an eighth transistor Md8. A gate of the seventh transistor and a gate of the eighth transistor are coupled to the second polarity signal input terminal vip- of the second group of signal input terminals, and a drain of the second transistor and a drain of the seventh transistor and a drain of the eighth transistor are both coupled to the first polarity signal output terminal vo+ of the first group of signal output terminals.

In the embodiment of FIG. 3 , the pair of load transistors (Md3, Md4) are coupled to the first group of signal output terminals (vo+, vo-), and include a third transistor Md3 coupled in a cross-feedback manner and a fourth transistor Md4. A source of the first transistor Md1, a source of the second transistor Md2, a source of the fifth transistor Md5, and a source of the seventh transistor Md7 are all coupled to the control signal input terminal T1. A source of the third transistor Md3, a source of the fourth transistor Md4, a source of the sixth transistor Md6, and a source of the eighth transistor Md8 are all coupled to the ground terminal T2. The bias transistors Md9-Md16 are used to provide the DC bias voltage of the delay module 21, wherein the bias transistors Md9-Md12 are NMOS, and the bias transistors Md13-Md16 are PMOS, but the invention is not limited thereto. The first transistor Md1, the second transistor Md2, the fifth transistor Md5 and the seventh transistor Md7 are all PMOS, the third transistor Md3, the fourth transistor Md4, the sixth transistor Md6 and the eighth transistor Md8 are all NMOS, but the present invention does not It is not limited to this.

It is worth noting that the load transistor pair ( Md3 , Md4 ) has the characteristic of negative resistance, and the resistance value thereof is related to the current value given by the driving current signal Sci. Therefore, the oscillation frequency control circuit 3 can adjust the impedance of the load transistor pair ( Md3 , Md4 ) by changing the driving current signal Sci output to the control signal input terminal T1 , thereby adjusting the delay time of the delay module 21 .

FIG. 4 is a circuit diagram of realizing the oscillation frequency control circuit 3 according to an embodiment of the present invention. In the embodiment shown in FIG. 4 , the frequency adjustment circuit 31 includes an input stage circuit 311 and a current switching module 312 . The input stage circuit 311 includes an NMOS transistor Mc1, an NMOS transistor Mc2, resistors R1-R3, and a capacitor C1.

In the embodiment of FIG. 4, the NMOS transistor Mc1 of the input stage circuit 311 is used to receive the bias current input Ib1. The resistors R1 - R2 of the input stage circuit 311 and the capacitor C1 form a low-pass filter, and the low-pass filter is used to filter out the low-frequency noise of the frequency adjustment circuit 31 . The resistor R3 is connected in series between a source terminal of the transistor Mc2 and the ground terminal. The resistor R3 has the effect of the noise of the transistor Mc2. The transistor Mc1 and the transistor Mc2 form a current mirror circuit, so that the bias current input Ib1 flowing through the transistor Mc1 corresponds to a bias current Ib2 flowing through the transistor Mc2.

In the embodiment of FIG. 4, the current switching module 312 includes a PMOS transistor Mc3, switches SW1-SWk, switching transistors Ms1-Msk, and a capacitor C2. The current switching module 312 receives the digital control signal d<M:0>, and uses the digital control signal d<M:0> to control whether the switches SW1 - SWk are turned on or off. The bit length M of the digital control signal d<M:0> depends on the total number of switches SW1-SWk, for example, eight switches SW1-SW8 are controlled using a 3-bit digital control signal d<3:0>. One of the transistors Mc3 and the transistors Ms1-Msk is conductive to form a current mirror circuit. Therefore, any one of the transistors Ms1-Msk that is turned on can be regarded as a PMOS current source. In the embodiment of the present invention, each of the switches SW1-SWk may be implemented by a transistor, but is not limited to this embodiment.

With the current mirror circuit, the bias current Ib2 flowing through the transistor Mc3 corresponds to the first control current signal Ic1 output by the current switching module 312 . The current value of the first control current signal Ic1 depends on the transistor size (eg, transistor aspect ratio) of the turned-on switching transistors Ms1-Msk. The greater the number of the turned-on switching transistors Ms1-Msk, the greater the current value of the first control current signal Ic1. The larger the transistor aspect ratio of the turned-on switching transistors Ms1-Msk, the larger the current value of the first control current signal Ic1. The switching transistors Ms1-Msk are realized by PMOS, but the present invention is not limited to this. Therefore, in the embodiment shown in FIG. 4 , the frequency adjustment circuit 31 can generate the first control current signal Ic1 with different current values through different digital control signals d<M:0>.

In the embodiment of FIG. 4, oscillator drive circuit 32 includes transistors Mc4-Mc6, resistor R4 and capacitor C3. Resistor R4 is a source resistance of NMOS transistor Mc5. The capacitor C3 is electrically connected to a voltage-stabilizing capacitor at the output end of the frequency adjusting circuit 31 . The capacitor C3 is used to reduce the noise generated by the PMOS current source (that is, the transistors Ms1-Msk are conductive and the PMOS transistor Mc6), and can improve the power supply rejection ratio of the frequency adjustment circuit 31 .

In the embodiment of FIG. 4 , a gate of the NMOS transistor Mc5 is used for receiving the control voltage input Vcn, and correspondingly generates a current Icn flowing through the PMOS transistor Mc4 and the NMOS transistor Mc5. The PMOS transistor Mc4 and the PMOS transistor Mc6 form a current mirror circuit. With the current mirror circuit, the current Icn flowing through the transistor Mc4 correspondingly generates the second control current signal Ic2 output by the oscillator driving circuit 32 . Therefore, in the embodiment shown in FIG. 4 , the oscillator driving circuit 32 can generate the second control current signal Ic2 with different current values by changing the control voltage input Vcn.

Although the present invention is disclosed above with preferred embodiments, those skilled in the art can more clearly understand the content of the present invention. However, those skilled in the art will appreciate that they can readily use the present invention as a basis to design or modify processes and use a current controlled oscillator for the same purposes and/or to achieve the same advantages of the embodiments presented herein. Therefore, the protection scope of the present invention should be determined by the above-mentioned claims.

Claims (14)

1. A current controlled oscillator comprising: A ring oscillator having a first phase connection configuration and a second phase connection configuration, the ring oscillator comprising: at least four delay modules, each of which has a control signal input terminal, a ground terminal, a first group of signal input terminals, a second group of signal input terminals and a first group of signal output terminals; an input terminal coupled to the control signal input terminal of each of the delay modules; and A set of oscillating frequency signal output terminals coupled to the first set of signal output terminals of the last stage delay module of the ring oscillator for outputting a set of oscillating frequency signals of the current controlled oscillator, wherein when the ring oscillator When the device is configured in the first phase connection configuration, the first group of signal output terminals of each delay module is coupled to the first group of signal input terminals of the next stage delay module, and the last stage delay module The first group of signal output terminals is coupled to the first group of signal output terminals of the first stage delay module. When the ring oscillator is changed from the first phase connection configuration to the second phase connection configuration, each delay The first group of signal output terminals of the module is also coupled to the second group of signal input terminals of the next stage delay module; and When the ring oscillator is changed from the first phase connection configuration to the second phase connection configuration, the first group of signal output terminals of the penultimate stage delay module is further coupled to the first stage delay module. Two sets of signal input terminals, and the first set of signal output terminals of the last stage delay module is also coupled to the second set of signal input terminals of the second stage delay module; and an oscillation frequency control circuit coupled to the ring oscillator, wherein the oscillation frequency control circuit receives an external bias current input, a digital control signal and a control voltage input, and according to the bias current input, the digital control circuit the signal and the control voltage input to generate a drive current signal; and The oscillating frequency control circuit outputs the driving current signal to the input end of the ring oscillator to adjust an oscillating frequency of the group of oscillating frequency signals of the ring oscillator. 2. The current controlled oscillator according to claim 1, wherein the oscillation frequency control circuit further comprises: a frequency adjustment circuit, receiving the bias current input and the digital control signal, and generating a first control current signal according to the digital control signal; and an oscillator driving circuit that receives the control voltage input and generates a second control current signal according to the control voltage input, wherein an output terminal of the frequency adjustment circuit and an output terminal of the oscillator driving circuit are both coupled to the An output end of the oscillation frequency control circuit makes the driving current signal include the first control current signal and the second control current signal. 3. The current controlled oscillator of claim 2, wherein each of the delay modules further comprises: a first delay transistor pair, respectively coupled to the first group of signal input terminals and the first group of signal output terminals, and comprising a first transistor and a second transistor; a pair of load transistors, coupled to the first group of signal output terminals, and including a third transistor and a fourth transistor coupled in a cross-positive feedback manner; a second delay transistor pair coupled to the second group of signal input terminals and the first group of signal output terminals, respectively, and comprising a fifth transistor and a sixth transistor; and A third delay transistor pair is respectively coupled to the second group of signal input terminals and the first group of signal output terminals, and includes a seventh transistor and an eighth transistor. 4. The current controlled oscillator of claim 3, wherein a gate of the first transistor and a gate of the second transistor are respectively coupled to a first polarity signal input of the first group of signal input terminals terminal and a second-polarity signal input terminal, and a source of the first transistor and a source of the second transistor are respectively coupled to a first-polarity signal output terminal and a first-polarity signal output terminal of the first group of signal output terminals The second polarity signal output terminal; A gate of the fifth transistor and a gate of the sixth transistor are coupled to a first polarity signal input terminal of the second group of signal input terminals, and a drain of the first transistor, the fifth A drain of the transistor and a drain of the sixth transistor are both coupled to the second polarity signal output terminal of the first group of signal output terminals; and A gate of the seventh transistor and a gate of the eighth transistor are coupled to a second polarity signal input terminal of the second group of signal input terminals, and a drain of the second transistor, the seventh A drain of the transistor and a drain of the eighth transistor are both coupled to the first polarity signal output terminal of the first group of signal output terminals. 5. The current controlled oscillator of claim 4, wherein a source of the first transistor, a source of the second transistor, a source of the fifth transistor and a source of the seventh transistor are both coupled to the control signal input end; and The oscillation frequency control circuit adjusts the impedance of the load transistor pair by changing the driving current signal output to the control signal input end, and further adjusts the delay time of the delay module. 6. The current controlled oscillator of claim 2, wherein the first set of signal input terminals comprises a first polarity signal input terminal and a second polarity signal input terminal, the second set of signal input terminals comprises a a first polarity signal input end and a second polarity signal input end, and the first group of signal output ends includes a first polarity signal output end and a second polarity signal output end; When the ring oscillator is configured in the first phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of each delay module is coupled to the first signal output terminal of the next stage delay module The first polarity signal input end of the group signal input end, and the second polarity signal output end of the first group signal output end of each delay module is coupled to the first group signal input of the next stage delay module the second polarity signal input terminal of the terminal; and When the ring oscillator is configured in the first phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of the last stage delay module is coupled to the first stage of the first stage delay module. the second polarity signal input terminal of the group signal output terminal, and the second polarity signal output terminal of the first group signal output terminal of the last stage delay module is coupled to the first group signal output terminal of the first stage delay module The first polarity signal input terminal of the terminal. 7 . The current controlled oscillator of claim 6 , wherein if the ring oscillator is changed from the first phase connection configuration to the second phase connection configuration, the first set of signals of each delay module is output. 8 . The first polarity signal output terminal of the terminal is also coupled to the second set of signal input terminals of the next-stage delay module, and the second polarity signal output terminal of the first set of signal output terminals of each delay module coupled to the second polarity signal input terminal of the first group of signal input terminals of the next stage delay module; If the ring oscillator is changed from the first phase connection configuration to the second phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of the penultimate stage delay module is further coupled to The second polarity signal input end of the second group of signal input ends of the first stage delay module, and the second polarity signal output end of the first group of signal output ends of the penultimate stage delay module is also coupled to the first the first polarity signal input terminal of the second group of signal input terminals of the first stage delay module; and Wherein, if the ring oscillator is changed from the first phase connection configuration to the second phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of the last stage delay module is also coupled to the first polarity signal output terminal. The second polarity signal input end of the second group of signal input ends of the second stage delay module, and the second polarity signal output end of the first set of signal output ends of the last stage delay module is also coupled to the second stage The first polarity signal input end of the second group of signal input ends of the delay module. 8. The current-controlled oscillator of claim 7, wherein if the ring oscillator includes at least seven stages of the delay module, the ring oscillator further has a third phase connection configuration; Wherein, if the ring oscillator is changed from the first phase connection configuration to the third phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of each delay module is also coupled to the lower The second set of signal input terminals of the three-stage delay module, and the second polarity signal output terminal of the first set of signal output terminals of each delay module is also coupled to the first set of signals of the next three-stage delay module the second polarity signal input end of the input end; If the ring oscillator is changed from the first phase connection configuration to the third phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of the third-to-last delay module is further coupled to The second polarity signal input end of the second group of signal input ends of the first stage delay module, and the second polarity signal output end of the first group of signal output ends of the penultimate stage delay module is also coupled to the first the first polarity signal input end of the second group of signal input ends of the first-stage delay module; If the ring oscillator is changed from the first phase connection configuration to the third phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of the penultimate stage delay module is further coupled to The second polarity signal input end of the second group of signal input ends of the second stage delay module, and the second polarity signal output end of the first group of signal output ends of the penultimate stage delay module is also coupled to the first the first polarity signal input end of the second group of signal input ends of the two-stage delay module; and Wherein, if the ring oscillator is changed from the first phase connection configuration to the third phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of the last stage delay module is also coupled to the first polarity signal output terminal. The second-polarity signal input terminal of the second group of signal input terminals of the three-stage delay module, and the second-polarity signal output terminal of the first group of signal output terminals of the last delay module is also coupled to the third-stage delay The first polarity signal input terminal of the second group of signal input terminals of the module. 9. The current controlled oscillator of claim 2, wherein the frequency adjustment circuit comprises: an input stage circuit, receiving the bias current input and correspondingly generating a bias current; and a current switching module coupled to the input stage circuit and receiving the bias current, wherein the current switching module includes a plurality of switched current sources; and The current switching module determines whether each switch current source is turned on or not according to the received digital control signal, so as to adjust the current value of the first control current signal. 10. The current controlled oscillator of claim 9, wherein the oscillator drive circuit comprises: an input transistor, the control voltage is input, and the control current is generated according to the control voltage input; a current mirror circuit electrically connected to the input transistor and the output end of the oscillator driving circuit, wherein the current mirror circuit generates the second control current signal according to the received control current; and A stabilizing capacitor is electrically connected to the output end of the frequency adjusting circuit to reduce the noise generated by the switching current sources. 11. A ring oscillator having a first phase connection configuration and a second phase connection configuration, the ring oscillator comprising: at least four delay modules, each of which has a control signal input terminal, a ground terminal, a first group of signal input terminals, a second group of signal input terminals and a first group of signal output terminals; an input terminal coupled to the control signal input terminal of each of the delay modules; and A group of oscillating frequency signal output terminals are coupled to the first group of signal output terminals of the last stage delay module of the ring oscillator for outputting a group of oscillating frequency signals, wherein the first group of signal input terminals includes a first group of signal output terminals. A polarity signal input end and a second polarity signal input end, the second group of signal input ends includes a first polarity signal input end and a second polarity signal input end, and the first group of signal output ends including a first polarity signal output end and a second polarity signal output end; When the ring oscillator is configured in the first phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of each delay module is coupled to the first signal output terminal of the next stage delay module The first polarity signal input end of the group signal input end, and the second polarity signal output end of the first group signal output end of each delay module is coupled to the first group signal input of the next stage delay module The second polarity signal input terminal of the terminal; When the ring oscillator is configured in the first phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of the last stage delay module is coupled to the first stage of the first stage delay module. the second polarity signal input terminal of the group signal output terminal, and the second polarity signal output terminal of the first group signal output terminal of the last stage delay module is coupled to the first group signal output terminal of the first stage delay module The first polarity signal input terminal of the terminal; Wherein, when the ring oscillator is changed from the first phase connection configuration to the second phase connection configuration, the first group of signal output terminals of each delay module is also coupled to the first signal output end of the next-stage delay module Two sets of signal input terminals; and When the ring oscillator is changed from the first phase connection configuration to the second phase connection configuration, the first group of signal output terminals of the penultimate stage delay module is further coupled to the first stage delay module. Two sets of signal input terminals, and the first set of signal output terminals of the last stage delay module is also coupled to the second set of signal input terminals of the second stage delay module, Wherein, the input end of the ring oscillator receives a driving current signal to adjust an oscillation frequency of the group of oscillating frequency signals of the ring oscillator, and wherein the driving current signal is input according to a bias current, a digital control signal and a control voltage input. 12. The ring oscillator of claim 11, wherein each of the delay modules further comprises: A first delay transistor pair includes a first transistor and a second transistor, wherein a gate of the first transistor and a gate of the second transistor are respectively coupled to the first signal input terminal of the first group A polarity signal input terminal and a second polarity signal input terminal, and a source of the first transistor and a source of the second transistor are both coupled to the first polarity signal of the first group of signal output terminals an output end and the second polarity signal output end; a pair of load transistors, coupled to the first group of signal output terminals, and including a third transistor and a fourth transistor coupled in a cross-positive feedback manner; A second delay transistor pair includes a fifth transistor and a sixth transistor, wherein a gate of the fifth transistor and a gate of the sixth transistor are coupled to the first electrode of the second group of signal input terminals A polarity signal input terminal, and a drain of the first transistor, a drain of the fifth transistor and a drain of the sixth transistor are all coupled to the second polarity signal output of the first group of signal output terminals end; and A third delay transistor pair includes a seventh transistor and an eighth transistor, wherein a gate of the seventh transistor and a gate of the eighth transistor are coupled to the second pole of the second group of signal input terminals a polarity signal input terminal, and a drain of the second transistor, a drain of the seventh transistor and a drain of the eighth transistor are all coupled to the first polarity signal output of the first group of signal output terminals end; and A source of the first transistor, a source of the second transistor, a source of the fifth transistor and a source of the seventh transistor are all coupled to the control signal input end, and the third A source of the transistor, a source of the fourth transistor, a source of the sixth transistor, and a source of the eighth transistor are all coupled to the ground. 13 . The ring oscillator of claim 11 , wherein if the ring oscillator is changed from the first phase connection configuration to the second phase connection configuration, the first group of signal output terminals of each of the delay modules has 13 . The first polarity signal output terminal is also coupled to the second set of signal input terminals of the next-stage delay module, and the second polarity signal output terminal of the first set of signal output terminals of each delay module is coupled to connected to the second polarity signal input terminal of the first group of signal input terminals of the next-stage delay module; If the ring oscillator is changed from the first phase connection configuration to the second phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of the penultimate stage delay module is further coupled to The second polarity signal input end of the second group of signal input ends of the first stage delay module, and the second polarity signal output end of the first group of signal output ends of the penultimate stage delay module is also coupled to the first the first polarity signal input terminal of the second group of signal input terminals of the first stage delay module; and Wherein, if the ring oscillator is changed from the first phase connection configuration to the second phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of the last stage delay module is also coupled to the first polarity signal output terminal. The second polarity signal input end of the second group of signal input ends of the second stage delay module, and the second polarity signal output end of the first set of signal output ends of the last stage delay module is also coupled to the second stage The first polarity signal input end of the second group of signal input ends of the delay module. 14. The ring oscillator of claim 13, wherein if the ring oscillator includes at least seven stages of the delay module, the ring oscillator further has a third phase connection configuration; Wherein, if the ring oscillator is changed from the first phase connection configuration to the third phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of each delay module is also coupled to the lower The second set of signal input terminals of the three-stage delay module, and the second polarity signal output terminal of the first set of signal output terminals of each delay module is also coupled to the first set of signals of the next three-stage delay module the second polarity signal input end of the input end; If the ring oscillator is changed from the first phase connection configuration to the third phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of the third-to-last delay module is further coupled to The second polarity signal input end of the second group of signal input ends of the first stage delay module, and the second polarity signal output end of the first group of signal output ends of the penultimate stage delay module is also coupled to the first the first polarity signal input end of the second group of signal input ends of the first-stage delay module; If the ring oscillator is changed from the first phase connection configuration to the third phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of the penultimate stage delay module is further coupled to The second polarity signal input end of the second group of signal input ends of the second stage delay module, and the second polarity signal output end of the first group of signal output ends of the penultimate stage delay module is also coupled to the first the first polarity signal input end of the second group of signal input ends of the two-stage delay module; and Wherein, if the ring oscillator is changed from the first phase connection configuration to the third phase connection configuration, the first polarity signal output terminal of the first group of signal output terminals of the last stage delay module is also coupled to the first polarity signal output terminal. The second-polarity signal input terminal of the second group of signal input terminals of the three-stage delay module, and the second-polarity signal output terminal of the first group of signal output terminals of the last delay module is also coupled to the third-stage delay The first polarity signal input terminal of the second group of signal input terminals of the module.