CN106128354B - Flat display apparatus and its scan drive circuit - Google Patents
Flat display apparatus and its scan drive circuit Download PDFInfo
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- CN106128354B CN106128354B CN201610817091.7A CN201610817091A CN106128354B CN 106128354 B CN106128354 B CN 106128354B CN 201610817091 A CN201610817091 A CN 201610817091A CN 106128354 B CN106128354 B CN 106128354B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a kind of flat display apparatus and its scan drive circuit.The scan drive circuit includes multiple scan drive cells of cascade, and each scan drive cell produces the first scanning signal by positive and negative scanning circuit, the first input circuit, first control circuit, the first pull-down circuit, the first pull-up circuit and the first output circuit；Second scanning signal is produced by the second input circuit, second control circuit, the second pull-down circuit, the second pull-up circuit and the second output circuit.By the above-mentioned means, the present invention can realize the circuit of simplified flat display apparatus, space is saved, and then beneficial to the narrow frame design of flat display apparatus.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of flat display apparatus and its scan drive circuit.
Background technology
Scan drive circuit is used in current flat display apparatus, that is, is shown using existing thin film transistor (TFT) plane
Scan drive circuit is produced on array base palte by device array process, realizes the type of drive to progressive scan.
Each scan drive cell only drives a scan line in existing flat display apparatus, and each turntable driving list
Member is required to complete circuit to realize generation drive signal, and all multi-strip scanning lines are set in general closed planar display device, and this will
Need to design many scan drive cells, can not realize shared, complex circuit designs, and space-consuming certainly will be caused, be unfavorable for
The narrow frame design of flat display apparatus.
The content of the invention
The present invention solves the technical problem of a kind of flat display apparatus and its scan drive circuit is provided, with simplification
The circuit of flat display apparatus, space is saved, and then beneficial to the narrow frame design of flat display apparatus.
In order to solve the above technical problems, one aspect of the present invention is：A kind of scan drive circuit is provided, its
Multiple scan drive cells including cascade, each scan drive cell include：
Positive and negative scanning circuit, for receive the first scan control signal, the second scan control signal, drive signal and under
One-level scanning signal, and forward and reverse control signal is exported, forward and reverse control signal is used to control scan drive cell to carry out just
To scanning or reverse scan；
First input circuit, for receiving the first clock signal and receiving forward and reverse control signal from positive and negative scanning circuit,
And export the first input signal；
First pull-down circuit, for receiving the first input signal and the first reference voltage, and the first pulldown signal is exported, it is right
First node is pulled down；
First pull-up circuit, for receiving the first input signal, the first reference voltage, the second reference voltage and when second
Clock signal, and the first pull-up signal is exported, first node is pulled up；
First control circuit, for receiving the first input signal and the second reference voltage, for according to the first input signal
Section point is charged；
First output circuit, for receiving second clock signal, the first scanning signal is produced according to second clock signal；
Second input circuit, for receiving second clock signal and receiving the first scanning signal from the first output circuit, and
And the second input signal of output；
Second pull-down circuit, for receiving the second input signal and the first reference voltage, and the second pulldown signal is exported, it is right
3rd node is pulled down；
Second pull-up circuit, for receiving the second input signal, the first reference voltage, the second reference voltage and when second
Clock signal, and the second pull-up signal is exported, the 3rd node is pulled up；
Second control circuit, for receiving the second input signal and the second reference voltage, for according to the second input signal
Fourth node is charged；
Second output circuit, for receiving the first clock signal, the second scanning signal is produced according to the first clock signal.
Wherein, positive and negative scanning circuit includes the first gate-controlled switch and the second gate-controlled switch, the control terminal of the first gate-controlled switch
The first scan control signal is received, the first end of the first gate-controlled switch connects the first end and the first input electricity of the second gate-controlled switch
Road, the second end of the first gate-controlled switch receive drive signal, and the control terminal of the second gate-controlled switch receives the second scan control signal,
Second termination of the second gate-controlled switch accepts one-level scanning signal.
Wherein, the first input circuit includes the 3rd gate-controlled switch, and the control terminal of the 3rd gate-controlled switch receives the first clock letter
Number, the first end of the 3rd gate-controlled switch connects the first pull-down circuit, and the second end of the 3rd gate-controlled switch connects the first gate-controlled switch
First end and the second gate-controlled switch first end；
First pull-down circuit includes the 4th gate-controlled switch, the 5th gate-controlled switch, the 6th gate-controlled switch and the first electric capacity, the
The control terminal of four gate-controlled switches, the control at the second end of the 5th gate-controlled switch, the first end of the first electric capacity and the 6th gate-controlled switch
End processed is all connected with first node, and the first end of the 4th gate-controlled switch connects the 3rd gate-controlled switch with the control terminal of the 5th gate-controlled switch
First end, the second end of the 4th gate-controlled switch, the first end of the 5th gate-controlled switch, the second end of the first electric capacity and the 6th can
The first end of control switch receives the first reference voltage.
Wherein, the first pull-up circuit includes the 7th gate-controlled switch, the 8th gate-controlled switch and the second electric capacity, and the 7th controllable opens
The first end of control terminal the 3rd gate-controlled switch of connection of pass, the first reference voltage of the second end reception of the 7th gate-controlled switch, the 7th
The first end of gate-controlled switch connects the control terminal of the 8th gate-controlled switch and the first end of the second electric capacity, the second termination of the second electric capacity
Second clock signal is received, the first end connection first node of the 8th gate-controlled switch, the second end of the 8th gate-controlled switch receives second
Reference voltage；
First control circuit includes the 9th gate-controlled switch, and the control terminal of the 9th gate-controlled switch receives the second reference voltage, the
Second end of nine gate-controlled switches connects the first end of the 3rd gate-controlled switch, the first end connection section point of the 9th gate-controlled switch；
First output circuit includes the tenth gate-controlled switch and the 3rd electric capacity, and the first end of the 3rd electric capacity and the tenth controllable is opened
The control terminal connection section point of pass, the second end of the tenth gate-controlled switch receive second clock signal, and the of the 6th gate-controlled switch
Two ends connect the second end of the 3rd electric capacity and the first end of the tenth gate-controlled switch, the second end output the first scanning letter of the 3rd electric capacity
Number.
Wherein, the second input circuit includes the 11st gate-controlled switch, when the control terminal of the 11st gate-controlled switch receives second
Clock signal, the second end of the 11st gate-controlled switch connect the second end of the 3rd electric capacity, the first end connection of the 11st gate-controlled switch
Second pull-down circuit；
Second pull-down circuit includes the 12nd gate-controlled switch, the 13rd gate-controlled switch, the 14th gate-controlled switch and the 4th
Electric capacity, control terminal, the second end of the 13rd gate-controlled switch, the first end and the 14th of the 4th electric capacity of the 12nd gate-controlled switch
The control terminal of gate-controlled switch is all connected with the 3rd node, the first end of the 12nd gate-controlled switch and the control terminal of the 13rd gate-controlled switch
Connect the first end of the 11st gate-controlled switch, the second end of the 12nd gate-controlled switch, the first end of the 13rd gate-controlled switch, the 4th
Second end of electric capacity and the first end of the 14th gate-controlled switch receive the first reference voltage.
Wherein, second control circuit includes the 15th gate-controlled switch, and the control terminal of the 15th gate-controlled switch receives the second ginseng
Examine voltage, the second end of the 15th gate-controlled switch connects the first end of the 11st gate-controlled switch, and the first of the 15th gate-controlled switch
End connection fourth node；
Second output circuit includes the 16th gate-controlled switch and the 5th electric capacity, and the first end and the 16th of the 5th electric capacity can
The control terminal connection fourth node of control switch, the second end of the 16th gate-controlled switch receive the first clock signal, and the 14th is controllable
Second end of switch connects the second end of the 5th electric capacity and the first end of the 16th gate-controlled switch, the second end output of the 5th electric capacity
Second scanning signal；
Second pull-up circuit includes the 17th gate-controlled switch, and the first end of the 17th gate-controlled switch receives second with reference to electricity
Pressure, the second end of the 17th gate-controlled switch connect the 3rd node, and the control terminal of the 17th gate-controlled switch connects the 7th gate-controlled switch
First end.
Wherein, the second pull-up circuit further comprises the 18th gate-controlled switch, the control terminal connection of the 18th gate-controlled switch
The first end of 11st gate-controlled switch, the control terminal of first end the 17th gate-controlled switch of connection of the 18th gate-controlled switch, the tenth
Second end of eight gate-controlled switches receives the first reference voltage.
Wherein, the first reference voltage is low level, and the second reference voltage is high level, and the first to the 18th gate-controlled switch is
N-type TFT, control terminal, first end and the second end of the first to the 18th gate-controlled switch correspond to N-type film crystal respectively
Grid, drain electrode and the source electrode of pipe.
Wherein, the first reference voltage is low level, and the second reference voltage is high level, and the first to the 18th gate-controlled switch is
P-type TFT, control terminal, first end and the second end of the first to the 18th gate-controlled switch correspond to p-type film crystal respectively
Grid, drain electrode and the source electrode of pipe.
In order to solve the above technical problems, another technical solution used in the present invention is：A kind of flat display apparatus is provided,
Flat display apparatus includes any of the above-described scan drive circuit.
The beneficial effects of the invention are as follows：The situation of prior art is different from, scan drive circuit of the invention passes through positive and negative
Scanning circuit is scanned forward or backwards, and section point is charged by the first input circuit and first control circuit,
First node is pulled down by the first pull-down circuit, first node pulled up by the first pull-up circuit, passes through
One output circuit produces the first scanning signal；Fourth node is charged by the second input circuit and second control circuit,
The 3rd node is pulled down by the second pull-down circuit, the 3rd node pulled up by the second pull-up circuit, passes through
Two output circuits produce the second scanning signal, and the present invention is swept by sharing positive and negative scanning circuit generation the first scanning signal and second
Signal is retouched, the circuit of simplified flat display apparatus is realized with this, saves space, and then set beneficial to the narrow frame of flat display apparatus
Meter.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, make required in being described below to embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.Wherein：
Fig. 1 is the circuit diagram of the scan drive cell of the scan drive circuit of first embodiment of the invention；
Fig. 2 is the timing diagram of the scan drive circuit forward scan in Fig. 1；
Fig. 3 is the timing diagram of the scan drive circuit reverse scan in Fig. 1；
Fig. 4 is the structural representation of scan drive circuit in Fig. 1；
Fig. 5 is the simulation waveform schematic diagram of scan drive cell in Fig. 1；
Fig. 6 is the circuit diagram of the scan drive cell of second embodiment of the invention；
Fig. 7 is the circuit diagram of the scan drive cell of third embodiment of the invention；
Fig. 8 is the circuit diagram of the scan drive cell of fourth embodiment of the invention；
Fig. 9 is the structural representation of the flat display apparatus of first embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.Based on this
Embodiment in invention, those of ordinary skill in the art are obtained every other under the premise of performing creative labour is not made
Embodiment, belong to the scope of protection of the invention.
Refer to shown in Fig. 1-5, Fig. 1 is the electricity of the scan drive cell of the scan drive circuit of first embodiment of the invention
Lu Tu；Fig. 2 is the timing diagram of the scan drive circuit forward scan in Fig. 1；Fig. 3 is that the scan drive circuit in Fig. 1 is reversely swept
The timing diagram retouched；Fig. 4 is the structural representation of scan drive circuit in Fig. 1；Fig. 5 is the emulation ripple of scan drive cell in Fig. 1
Shape schematic diagram.Scan drive circuit disclosed in the present embodiment is used to produce scanning signal, is scanned with being driven by scanning signal
Line.As shown in figure 4, scan drive circuit 10 includes multiple scan drive cells 11 of cascade.
As shown in figure 1, each scan drive cell 11 includes positive and negative scanning circuit 111, the first input circuit 112, first
Pull-down circuit 113, the first pull-up circuit 114, first control circuit 115, the first output circuit 116, the second input circuit 121,
Second pull-down circuit 122, the second pull-up circuit 123, the output circuit 125 of second control circuit 124 and second.
Wherein, positive and negative scanning circuit 111 is used to receive the first scan control signal U2D (Up to Down), the second scanning
Control signal D2U (Down to Up), drive signal STV and next stage scanning signal G7, and export forward and reverse control letter
Number CL1, forward and reverse control signal CL1 are used to control scan drive cell 11 to carry out forward scan or reverse scan.
Positive and negative scanning circuit 111 includes the first gate-controlled switch T1 and the second gate-controlled switch T2, the first gate-controlled switch T1 control
End processed receives the first scan control signal U2D, the first gate-controlled switch T1 the second gate-controlled switch T2 of first end connection first end
And first input circuit 112, the first gate-controlled switch T1 the second end receive drive signal STV, the second gate-controlled switch T2 control
The second termination that end receives the second scan control signal D2U, the second gate-controlled switch T2 accepts one-level scanning signal Gate7.
First input circuit 112 is used to receive the first clock signal CK1 and receives forward and reverse control from positive and negative scanning circuit 111
Signal CL1 processed, and export the first input signal IN1.Wherein, the first input circuit 112 includes the 3rd gate-controlled switch T3, and the 3rd
The first end that gate-controlled switch T3 control terminal receives the first clock signal CK1, the 3rd gate-controlled switch T3 connects the first pull-down circuit
113, the 3rd gate-controlled switch T3 the second end connect the first gate-controlled switch T1 first end and the second gate-controlled switch T2 first end.
First pull-down circuit 113 is used to receive the first input signal IN1 and the first reference voltage VGL, and exports under first
Signal is drawn, first node P1 is pulled down.Wherein, the first pull-down circuit 113 includes the 4th gate-controlled switch T4, the 5th controllable opened
Close T5, the 6th gate-controlled switch T6 and the first electric capacity C1, the 4th gate-controlled switch T4 control terminal, the second of the 5th gate-controlled switch T5
The control terminal at end, the first electric capacity C1 first end and the 6th gate-controlled switch T6 is all connected with first node P1, the 4th gate-controlled switch
T4 first end connects the 3rd gate-controlled switch T3 first end with the 5th gate-controlled switch T5 control terminal, the 4th gate-controlled switch T4's
Second end, the 5th gate-controlled switch T5 first end, the first electric capacity C1 the second end and the 6th gate-controlled switch T6 first end are equal
Receive the first reference voltage VGL.
First pull-up circuit 114 is used to receive the first input signal IN1, the first reference voltage VGL, the second reference voltage
VGH and second clock signal CK3, and the first pull-up signal is exported, first node P1 is pulled up.Wherein, the first pull-up
Circuit 114 includes the 7th gate-controlled switch T7, the 8th gate-controlled switch T8 and the second electric capacity C2, the 7th gate-controlled switch T7 control terminal
The 3rd gate-controlled switch T3 first end is connected, the 7th gate-controlled switch T7 the second end receives the first reference voltage VGL, and the 7th is controllable
The first end for switching T7 connects the 8th gate-controlled switch T8 control terminal and the second electric capacity C2 first end (i.e. node H1), the second electricity
The second end for holding C2 receives second clock signal CK3, the 8th gate-controlled switch T8 first end connection first node P1, and the 8th is controllable
The second end for switching T8 receives the second reference voltage VGH.
First control circuit 115 is used to receive the first input signal IN1 and the second reference voltage VGH, for according to first
Input signal IN1 charges to section point Q1.Wherein, first control circuit 115 includes the 9th gate-controlled switch T9, and the 9th can
The second end that control switch T9 control terminal receives the second reference voltage VGH, the 9th gate-controlled switch T9 connects the 3rd gate-controlled switch T3
First end, the 9th gate-controlled switch T9 first end connection section point Q1.
First output circuit 116 is used to receive second clock signal CK3, and producing first according to second clock signal CK3 sweeps
Retouch signal Gate1.Wherein, the first output circuit 116 includes the tenth gate-controlled switch T10 and the 3rd electric capacity C3, the 3rd electric capacity C3
First end connect section point Q1 with the tenth gate-controlled switch T10 control terminal, the tenth gate-controlled switch T10 the second end receives the
Two clock signal CK3, the 6th gate-controlled switch T6 the second end connects the 3rd electric capacity C3 the second end and the tenth gate-controlled switch T10
First end, the 3rd electric capacity C3 the second end export the first scanning signal Gate1.
Second input circuit 121 is used to receive second clock signal CK3 and receives the first scanning from the first output circuit 116
Signal Gate1, and export the second input signal IN2.Wherein, the second input circuit 121 includes the 11st gate-controlled switch T11,
11st gate-controlled switch T11 control terminal receives second clock signal CK3, the 11st gate-controlled switch T11 the second end connection the
Three electric capacity C3 the second end, the 11st gate-controlled switch T11 first end connect the second pull-down circuit 122.
Second pull-down circuit 122 is used to receive the second input signal IN2 and the first reference voltage VGL, and exports under second
Signal is drawn, the 3rd node P3 is pulled down.Wherein, the second pull-down circuit 122 includes the 12nd gate-controlled switch T12, the 13rd
Gate-controlled switch T13, the 14th gate-controlled switch T14 and the 4th electric capacity C4, the 12nd gate-controlled switch T12 control terminal, the 13rd
Gate-controlled switch T13 the second end, the 4th electric capacity C4 first end and the 14th gate-controlled switch T14 control terminal is all connected with the 3rd
Node P3, the 12nd gate-controlled switch T12 first end connect the 11st gate-controlled switch with the 13rd gate-controlled switch T13 control terminal
T11 first end, the 12nd gate-controlled switch T12 the second end, the 13rd gate-controlled switch T13 first end, the 4th electric capacity C4
Second end and the 14th gate-controlled switch T14 first end receive the first reference voltage VGL.
Second control circuit 124 is used to receive the second input signal IN2 and the second reference voltage VGH, for according to second
Input signal IN2 charges to fourth node Q3.Wherein, second control circuit 124 includes the 15th gate-controlled switch T15, the
15 gate-controlled switch T15 control terminal receives the second reference voltage VGH, the 15th gate-controlled switch T15 the second end connection the tenth
One gate-controlled switch T11 first end, the 15th gate-controlled switch T15 first end connection fourth node Q3.
Second output circuit 125 is used to receive the first clock signal CK1, and producing second according to the first clock signal CK1 sweeps
Retouch signal Gate3.Wherein, the second output circuit 125 includes the 16th gate-controlled switch T16 and the 5th electric capacity C5, the 5th electric capacity
C5 first end connects fourth node Q3, the 16th gate-controlled switch T16 the second end with the 16th gate-controlled switch T16 control terminal
The second end and the 16th for receiving the first clock signal CK1, the 14th gate-controlled switch T14 the 5th electric capacity C5 of the second end connection can
Control switch T16 first end, the 5th electric capacity C5 the second end export the second scanning signal Gate3.
Second pull-up circuit 123 is used to receive the second input signal IN2, the first reference voltage VGL, the second reference voltage
VGH and second clock signal CK3, and the second pull-up signal is exported, the 3rd node P3 is pulled up.Wherein, the second pull-up
Circuit 123 includes the 17th gate-controlled switch T17, and the 17th gate-controlled switch T17 first end receives the second reference voltage VGH, the
17 gate-controlled switch T17 the second end connects the 3rd node P3, and the 17th gate-controlled switch T17 control terminal connection the 7th is controllable to open
T7 first end is closed, i.e. the second pull-up circuit 123 receives the first reference voltage VGL by the 7th gate-controlled switch T7, and passes through
Second electric capacity C2 receives second clock signal CK3.
Preferably, the first reference voltage VGL is low level, and the second reference voltage VGH is high level, and first to the 17th can
Control switch is N-type TFT, and control terminal, first end and the second end of the first to the 17th gate-controlled switch correspond to N-type respectively
Grid, drain electrode and the source electrode of thin film transistor (TFT).Wherein, the controls of the 9th gate-controlled switch T9 of first control circuit 115 and second electricity
The 15th gate-controlled switch T15 conductings on road 124.
The operation principle of the forward scan of scan drive cell 11 with reference to disclosed in being described in detail the present embodiment in Fig. 2, below
Illustrated by taking a scan drive cell (such as first order scan drive cell) as an example.
When scan drive cell 11 carries out forward scan, the first scan control signal U2D is high level, the second scan control
Signal D2U is low level, and now the first gate-controlled switch T1 is turned on, and the second gate-controlled switch T2 disconnects, and positive and negative scanning circuit 111 exports
Forward and reverse control signal CL1 be drive signal STV.
When the first clock signal CK1 is low level, the 3rd gate-controlled switch T3 of the first input circuit 112 disconnects, and first
The first input signal IN1 that input circuit 112 exports is low level.
It is high level in drive signal STV, and when the first clock signal CK1 is high level, the first input circuit 112
3rd gate-controlled switch T3 is turned on, and the first input signal IN1 of the first input circuit 112 output is high level, now the first control
Circuit 115 charges to section point Q1, and section point Q1 charges to high level.5th gate-controlled switch T5 is turned on, under first
It is low level that puller circuit 113, which exports the first pulldown signal, and first node P1 is carried out to be pulled down to low level, the 6th gate-controlled switch T6
Disconnect；7th gate-controlled switch T7 is turned on, and the 8th gate-controlled switch T8 disconnects, and first node P1 is pulled down stable to low level.
Because section point Q1 charges to high level, the tenth gate-controlled switch T10 of the first output circuit 116 is turned on, now
The first scanning signal Gate1 of first output circuit 116 generation is identical with second clock signal CK3, is in second clock signal CK3
During high level, the first scanning signal Gate1 is high level, that is, produces the gate drive signal of the first order.
Now, the 11st gate-controlled switch T11 conductings of the second input circuit 121, the second input signal IN2 is high level,
Fourth node Q3 is charged, when fourth node Q3 is charged to high level, the 13rd gate-controlled switch T13 is turned on, under second
Puller circuit 122 pulls down to the 3rd node P3, and the 3rd node P3 is pulled down to low level, and the 14th gate-controlled switch T14 disconnects,
Now first node P1 and the 7th gate-controlled switch T7 first end (i.e. H1 nodes) remain low level.
Carry out interim, the second scanning signal of the second output circuit 125 output in the first clock signal CK1 high level pulse
Gate3 exports high level, i.e. third level gate drive signal is high level.Therefore the scan drive cell disclosed in the present embodiment
11 are applied to dual drive circuit simultaneously.
It is low level in drive signal STV, i.e. the first input signal IN1 is low level, the 5th gate-controlled switch T5 and the 7th
Gate-controlled switch T7 disconnects, and the 8th gate-controlled switch T8 control terminal is because the second electric capacity C2 boots to high level, the 8th gate-controlled switch
T8 is turned on, and the first pull-up circuit 114 carries out being pulled to high level to first node P1, and first node P1 passes through the first electric capacity C1
It is maintained at high level；4th gate-controlled switch T4 and the 6th gate-controlled switch T6 conductings, the 4th gate-controlled switch T4 is further by the second section
Point Q1 is pulled low to low level, and the tenth gate-controlled switch T10 disconnects, and now the 6th gate-controlled switch T6 draws the first scanning signal Gate1
As little as low level.17th gate-controlled switch T17 is turned on, and the second pull-up circuit 123 carries out being pulled to high level to the 3rd node P3,
And the 3rd node P3 high level is maintained at by the 4th electric capacity C4；12nd gate-controlled switch T12 and the 14th gate-controlled switch T14 are led
Logical, fourth node Q3 is pulled low to low level by the 12nd gate-controlled switch T12, and the 16th gate-controlled switch T16 disconnects, and the 14th is controllable
Second scanning signal Gate3 is pulled low to low level by switch T14, now the first scanning signal Gate1 and the second scanning signal
Gate3 stably exports low level.
As shown in figure 3, operation principle and the forward scan of the reverse scan of scan drive cell 11 disclosed in the present embodiment
Work similar, will not be repeated here.
As illustrated in figures 4-5, the function of scan drive circuit 10 of the invention is consistent with description and is passed in the intercaste of multistage
Also can be worked well.From fig. 4, it can be seen that drive signal STV includes left side drive signal STVL and the right driving letter
Number STVR, each scan drive cell 11 on the left side are operated alone by clock signal CK1 and clock signal CK3, the right
Each scan drive cell 11 is operated alone by clock signal CK2 and clock signal CK4, and the flat display apparatus uses
Interleaved type of drive, certain scan drive circuit 10 provided by the invention can also be used for double drives driving of panel.
The present embodiment produces the first scanning signal Gate1 and the second scanning signal by sharing positive and negative scanning circuit 111
Gate3, common circuit is realized, simplified circuit is realized with this, save space, and then set beneficial to the narrow frame of flat display apparatus
Meter.
As shown in fig. 6, the present invention also provides the scan drive cell of second embodiment, it is disclosed in first embodiment
The difference of scan drive cell 10 is：First to the 17th gate-controlled switch is P-type TFT, and first to the 17th can
Control terminal, first end and the second end of control switch correspond to grid, drain electrode and the source electrode of P-type TFT respectively.In other realities
Apply in example, the first to the 17th gate-controlled switch is alternatively other kinds of switch, as long as the purpose of the present invention can be realized.
As shown in fig. 7, the present invention also provides the scan drive cell of 3rd embodiment, it is disclosed in first embodiment
The difference of scan drive cell 10 is：Second pull-up circuit 123 further comprises the 18th gate-controlled switch T18, the 18th
Gate-controlled switch T18 control terminal connects the 11st gate-controlled switch T11 first end, and the 18th gate-controlled switch T18 first end connects
The 17th gate-controlled switch T17 control terminal is connect, the 18th gate-controlled switch T18 the second end receives the first reference voltage VGL.
Preferably, the 18th gate-controlled switch T18 is N-type TFT, the 18th gate-controlled switch T18 control terminal,
One end and the second end correspond to grid, drain electrode and the source electrode of N-type TFT respectively.
Relative to the scan drive cell 10 disclosed in first embodiment, the fourth node Q3 of the present embodiment passes through the 18th
Controls of the gate-controlled switch T18 to node H1, increase node H1 stability.
As shown in figure 8, the present invention also provides the scan drive cell of fourth embodiment, it is disclosed in 3rd embodiment
Scan drive cell difference is：First to the 18th gate-controlled switch is P-type TFT, and first to the 18th is controllable
Control terminal, first end and the second end of switch correspond to grid, drain electrode and the source electrode of P-type TFT respectively.In other implementations
In example, the first to the 18th gate-controlled switch is alternatively other kinds of switch, as long as the purpose of the present invention can be realized.
As shown in figure 9, the present invention also provides the flat display apparatus of first embodiment.As shown in figure 9, flat display apparatus
Including foregoing scan drive circuit, scan drive circuit is arranged on the both sides of flat display apparatus.In flat display apparatus
Other devices and function and the device and function phase of existing flat display apparatus are same, will not be repeated here.Wherein, plane display dress
It is set to LCD or OLED.
In summary, scan drive circuit of the invention is scanned forward or backwards by positive and negative scanning circuit, is passed through
First input circuit and first control circuit are charged to section point, and first node is carried out down by the first pull-down circuit
Draw, first node is pulled up by the first pull-up circuit, the first scanning signal is produced by the first output circuit；Pass through
Two input circuits and second control circuit are charged to fourth node, and the 3rd node is carried out down by the second pull-down circuit
Draw, the 3rd node is pulled up by the second pull-up circuit, the second scanning signal, the present invention are produced by the second output circuit
The first scanning signal and the second scanning signal are produced by sharing positive and negative scanning circuit, simplified flat display apparatus is realized with this
Circuit, space is saved, and then beneficial to the narrow frame design of flat display apparatus.
Embodiments of the present invention are the foregoing is only, are not intended to limit the scope of the invention, it is every to utilize this
The equivalent structure or equivalent flow conversion that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other correlations
Technical field, it is included within the scope of the present invention.
Claims (10)
- A kind of 1. scan drive circuit, it is characterised in that the scan drive circuit includes multiple scan drive cells of cascade, Each scan drive cell includes：Positive and negative scanning circuit, for receiving the first scan control signal, the second scan control signal, drive signal and next stage Scanning signal, and forward and reverse control signal is exported, forward and reverse control signal is used to control the scan drive cell to enter Row forward scan or reverse scan；First input circuit, for receiving the first clock signal and receiving forward and reverse control letter from the positive and negative scanning circuit Number, and export the first input signal；First pull-down circuit, for receiving first input signal and the first reference voltage, and the first pulldown signal is exported, it is right First node is pulled down；First pull-up circuit, for receiving first input signal, first reference voltage, the second reference voltage and Two clock signals, and the first pull-up signal is exported, the first node is pulled up；First control circuit, for receiving first input signal and second reference voltage, for according to described first Input signal charges to section point；First output circuit, for receiving the second clock signal, the first scanning is produced according to the second clock signal and believed Number；Second input circuit, for receiving the second clock signal and receiving first scanning from first output circuit Signal, and export the second input signal；Second pull-down circuit, for receiving second input signal and first reference voltage, and export the second drop-down letter Number, the 3rd node is pulled down；Second pull-up circuit, for receive second input signal, first reference voltage, second reference voltage with And the second clock signal, and the second pull-up signal is exported, the 3rd node is pulled up；Second control circuit, for receiving second input signal and second reference voltage, for according to described second Input signal charges to fourth node；Second output circuit, for receiving first clock signal, the second scanning is produced according to first clock signal and believed Number.
- 2. scan drive circuit according to claim 1, it is characterised in that it is controllable that the positive and negative scanning circuit includes first Switch and the second gate-controlled switch, control terminal reception first scan control signal of first gate-controlled switch, described first The first end of gate-controlled switch connects the first end of second gate-controlled switch and first input circuit, and described first controllable opens The second end closed receives the drive signal, and the control terminal of second gate-controlled switch receives second scan control signal, Second end of second gate-controlled switch receives the next stage scanning signal.
- 3. scan drive circuit according to claim 2, it is characterised in that it is controllable that first input circuit includes the 3rd Switch, the control terminal of the 3rd gate-controlled switch receive first clock signal, and the first end of the 3rd gate-controlled switch connects Connect first pull-down circuit, the second end of the 3rd gate-controlled switch connects the first end of first gate-controlled switch and described The first end of second gate-controlled switch；First pull-down circuit includes the 4th gate-controlled switch, the 5th gate-controlled switch, the 6th gate-controlled switch and the first electric capacity, institute State the control terminal of the 4th gate-controlled switch, the second end of the 5th gate-controlled switch, the first end of first electric capacity and described The control terminal of 6th gate-controlled switch is all connected with the first node, the first end of the 4th gate-controlled switch and described 5th controllable The control terminal of switch connects the first end of the 3rd gate-controlled switch, the second end of the 4th gate-controlled switch, the described 5th can First end, the second end of first electric capacity and the first end of the 6th gate-controlled switch of control switch receive described first Reference voltage.
- 4. scan drive circuit according to claim 3, it is characterised in that it is controllable that first pull-up circuit includes the 7th Switch, the 8th gate-controlled switch and the second electric capacity, the control terminal of the 7th gate-controlled switch connect the 3rd gate-controlled switch First end, the second end of the 7th gate-controlled switch receive first reference voltage, the first end of the 7th gate-controlled switch The control terminal of the 8th gate-controlled switch and the first end of second electric capacity are connected, the second end of second electric capacity receives institute State second clock signal, the first end of the 8th gate-controlled switch connects the first node, and the of the 8th gate-controlled switch Two ends receive second reference voltage；The first control circuit includes the 9th gate-controlled switch, and the control terminal of the 9th gate-controlled switch receives second reference Voltage, the second end of the 9th gate-controlled switch connect the first end of the 3rd gate-controlled switch, the 9th gate-controlled switch First end connects the section point；First output circuit includes the tenth gate-controlled switch and the 3rd electric capacity, and the first end and the described tenth of the 3rd electric capacity can The control terminal of control switch connects the section point, and the second end of the tenth gate-controlled switch receives the second clock signal, Second end of the 6th gate-controlled switch connects the second end of the 3rd electric capacity and the first end of the tenth gate-controlled switch, institute The second end for stating the 3rd electric capacity exports first scanning signal.
- 5. scan drive circuit according to claim 4, it is characterised in that second input circuit can including the 11st Control switch, the control terminal of the 11st gate-controlled switch receive the second clock signal, and the of the 11st gate-controlled switch Two ends connect the second end of the 3rd electric capacity, and the first end of the 11st gate-controlled switch connects second pull-down circuit；Second pull-down circuit includes the 12nd gate-controlled switch, the 13rd gate-controlled switch, the 14th gate-controlled switch and the 4th Electric capacity, the control terminal of the 12nd gate-controlled switch, the second end of the 13rd gate-controlled switch, the first of the 4th electric capacity The control terminal of end and the 14th gate-controlled switch is all connected with the 3rd node, the first end of the 12nd gate-controlled switch The first end of the 11st gate-controlled switch, the 12nd gate-controlled switch are connected with the control terminal of the 13rd gate-controlled switch The second end, the first end of the 13rd gate-controlled switch, the second end of the 4th electric capacity and the described 14th controllable open The first end of pass receives first reference voltage.
- 6. scan drive circuit according to claim 5, it is characterised in that the second control circuit can including the 15th Control switch, the control terminal of the 15th gate-controlled switch receive second reference voltage, and the of the 15th gate-controlled switch Two ends connect the first end of the 11st gate-controlled switch, described Section four of the first end connection of the 15th gate-controlled switch Point；Second output circuit includes the 16th gate-controlled switch and the 5th electric capacity, the first end of the 5th electric capacity and described The control terminal of 16th gate-controlled switch connects the fourth node, and the second end of the 16th gate-controlled switch receives described first Clock signal, the second end of the 14th gate-controlled switch connect the second end of the 5th electric capacity and the described 16th and controllable opened The first end of pass, the second end of the 5th electric capacity export second scanning signal；Second pull-up circuit includes the 17th gate-controlled switch, and the first end of the 17th gate-controlled switch receives described second Reference voltage, the second end of the 17th gate-controlled switch connect the 3rd node, the control of the 17th gate-controlled switch End connects the first end of the 7th gate-controlled switch.
- 7. scan drive circuit according to claim 6, it is characterised in that second pull-up circuit further comprises 18 gate-controlled switches, the control terminal of the 18th gate-controlled switch connect the first end of the 11st gate-controlled switch, and described the The first end of 18 gate-controlled switches connects the control terminal of the 17th gate-controlled switch, the second end of the 18th gate-controlled switch Receive first reference voltage.
- 8. scan drive circuit according to claim 7, it is characterised in that first reference voltage is low level, institute It is high level to state the second reference voltage, and the described first to the 18th gate-controlled switch is N-type TFT, described first to the tenth Control terminal, first end and the second end of eight gate-controlled switches correspond to grid, drain electrode and the source electrode of the N-type TFT respectively.
- 9. scan drive circuit according to claim 7, it is characterised in that first reference voltage is low level, institute It is high level to state the second reference voltage, and the described first to the 18th gate-controlled switch is P-type TFT, described first to the tenth Control terminal, first end and the second end of eight gate-controlled switches correspond to grid, drain electrode and the source electrode of the P-type TFT respectively.
- 10. a kind of flat display apparatus, it is characterised in that the flat display apparatus is included as described in claim 1-9 is any Scan drive circuit.
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| CN201610817091.7A CN106128354B (en) | 2016-09-12 | 2016-09-12 | Flat display apparatus and its scan drive circuit |
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| CN107016970B (en) * | 2017-04-17 | 2019-12-24 | 深圳市华星光电半导体显示技术有限公司 | DEMUX circuit |
| CN111326096A (en) * | 2020-04-07 | 2020-06-23 | 武汉华星光电技术有限公司 | GOA circuit and display panel |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104485079A (en) * | 2014-12-31 | 2015-04-01 | 深圳市华星光电技术有限公司 | GOA (Gate Driver On Array) circuit for liquid crystal display device |
| CN104537992A (en) * | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | GOA circuit for liquid crystal display device |
| CN104849928A (en) * | 2015-04-16 | 2015-08-19 | 上海中航光电子有限公司 | TFT array substrate, display panel and display device |
| CN104882107A (en) * | 2015-06-03 | 2015-09-02 | 深圳市华星光电技术有限公司 | Gate drive circuit |
| CN105206244A (en) * | 2015-10-29 | 2015-12-30 | 武汉华星光电技术有限公司 | GOA circuit and liquid crystal display |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3832439B2 (en) * | 2003-02-19 | 2006-10-11 | ソニー株式会社 | Display device and driving method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104537992A (en) * | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | GOA circuit for liquid crystal display device |
| CN104485079A (en) * | 2014-12-31 | 2015-04-01 | 深圳市华星光电技术有限公司 | GOA (Gate Driver On Array) circuit for liquid crystal display device |
| CN104849928A (en) * | 2015-04-16 | 2015-08-19 | 上海中航光电子有限公司 | TFT array substrate, display panel and display device |
| CN104882107A (en) * | 2015-06-03 | 2015-09-02 | 深圳市华星光电技术有限公司 | Gate drive circuit |
| CN105206244A (en) * | 2015-10-29 | 2015-12-30 | 武汉华星光电技术有限公司 | GOA circuit and liquid crystal display |
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