CN106129056A - The export structure of high ESD tolerance based on PD SOI technology - Google Patents

Abstract

The present invention relates to an output structure with high ESD tolerance based on PD-SOI technology, including a first NMOS transistor N1, a second NMOS transistor N2 and a PMOS transistor P1. When the output structure is used at an output port, the first NMOS transistor N1 The drain terminal and the drain terminal of the PMOS transistor P1 are connected to the output port, the source terminal of the PMOS transistor P1 is connected to the power supply, the source terminal of the first NMOS transistor N1 is connected to the drain terminal of the second NMOS transistor N2, and the source terminal of the second NMOS transistor N2 The substrates of the PMOS transistor P1, the first NMOS transistor N1 and the second NMOS transistor N2 are respectively connected to their respective source terminals, and the gates of the NMOS transistors are biased by the front-stage drive. The invention uses a common NMOS tube in the SOI process, uses gate control diodes and other ESD protection devices to discharge current when ESD comes, the output NMOS tube is not easy to damage, and the ESD protection ability of the circuit output is improved.

Description

High ESD tolerance output structure based on PD-SOI process

technical field

The invention belongs to the technical field of ESD protection design of SOI technology, and relates to an output structure with high ESD tolerance based on PD-SOI (partially depleted SOI) technology.

Background technique

SOI technology refers to the material preparation technology of forming a single crystal semiconductor silicon thin film layer with a certain thickness on the insulating layer and the process technology of manufacturing semiconductor devices on the thin film layer. This technology can achieve complete dielectric isolation. Compared with bulk silicon devices isolated by P-N junctions, it has the advantages of no latch, high speed, low power consumption, high integration, high temperature resistance, and radiation resistance.

According to the thickness of SOI silicon film, SOI devices can be divided into thick film devices and thin film devices. For thick-film SOI devices, when the thickness of the SOI silicon film is greater than twice the maximum depletion width, it is called a partially depleted device; for thin-film SOI devices, when the thickness of the SOI silicon film is less than the maximum depletion width, are called fully depleted devices.

In SOI technology, the device is fabricated in a very thin silicon film on the top, separated from the substrate by a layer of buried oxide. It is this structure that makes SOI/MOS devices have many advantages such as low power consumption. Compared with the traditional bulk silicon MOS process, it is more suitable for high-performance ULSI and VLSI circuits. Its advantages mainly include:

1. No latch-up effect. Due to the existence of the dielectric isolation structure in the SOI/MOS device, there is no current channel to the substrate, the channel of the latch effect is cut off, and the devices are physically and electrically isolated from each other, which improves the reliability of the circuit.

2. The structure is simple, the process is simple, and the integration density is high. The SOI/MOS device has a simple structure and does not require complex isolation processes such as preparing wells for bulk silicon CMOS circuits. The minimum device spacing only depends on the limitations of lithography and etching technology, and the integration density is greatly improved. SOI/MOS devices are also particularly suitable for integrating high-voltage and low-voltage circuits on the same chip, so they have high chip area utilization and cost performance.

3. The parasitic capacitance is small and the working speed is fast. The main capacitance of the bulk silicon MOS device is the capacitance between the source and drain regions of the tube and the source/drain diffusion region and the substrate, which increases with the increase of the doping concentration of the substrate, which will increase the load capacitance of the circuit and affect the circuit performance. Working speed; in SOI/MOS devices, due to the existence of the buried oxide layer, the source and drain regions and the substrate cannot form a P-N junction, and the parasitic capacitance of the P-N junction disappears, replaced by the capacitance of the buried oxide layer, which is proportional to the capacitive material The dielectric constant is much smaller than the parasitic capacitance of the P-N junction between the source and drain regions and the substrate in bulk silicon, and is not affected by scaling.

4. Low power consumption. The power consumption of SOI/MOS devices is composed of static power consumption and dynamic power consumption. SOI devices have a steep sub-threshold slope, which is close to the ideal level, so the leakage current is very small and the static power consumption is very low; due to SOI/MOS The device has smaller junction capacitance and connection capacitance than bulk silicon devices, so the dynamic power consumption is also greatly reduced at the same operating speed.

From the analysis of ESD protection, since the SOI process MOS device is formed above the buried oxide layer, compared with bulk silicon, the heat dissipation volume of the device is reduced, so the ESD protection capability of the device is greatly weakened, especially the output NMOS tube.

At present, there are two methods of ESD protection for SOI process circuits in the world: 1. Using gate-controlled diodes for ESD protection, mainly using the forward conduction characteristics of gate-controlled diodes. 2. The MOS tube that is dynamically turned on is used, and the MOS tube and the parasitic gate-controlled diode are turned on at the same time. It is difficult for the above two methods to meet the diverse demands of input/output ports.

Contents of the invention

The technical problem to be solved by the present invention is to overcome existing defects, provide a high ESD tolerance output structure based on PD-SOI process, use common MOS transistors in SOI process, and use gate-controlled diodes when ESD arrives, etc. The ESD protection device discharges current, and the output NMOS tube is not easily damaged, which improves the ESD protection capability of the circuit.

In order to solve the problems of the technologies described above, the present invention provides the following technical solutions:

The present invention is based on the output structure with high ESD tolerance of PD-SOI process, the output structure includes the first NMOS transistor N1, the second NMOS transistor N2 and the PMOS transistor P1, when the output structure is used in the output port, the first NMOS transistor The drain end of N1 and the drain end of PMOS transistor P1 are connected to the output port, the source end of PMOS transistor P1 is connected to the power supply, the source end of the first NMOS transistor N1 is connected to the drain end of the second NMOS transistor N2, and the second NMOS transistor N2 The source terminal of the PMOS transistor P1, the substrate of the first NMOS transistor N1 and the second NMOS transistor N2 are respectively connected to their respective source terminals, and the gates of the first NMOS transistor N1 and the second NMOS transistor N2 are connected and connected to the ground. The gates of the PMOS transistor P1 are all biased by the previous stage driver.

Further, the output port includes a first gate control diode D1, a second gate control diode D2 and an output pad, the cathode of the first gate control diode D1 is connected to the power supply VDD, the anode of the first gate control diode D1, the second gate The cathode of the control diode D2, the drain of the first NMOS transistor N1, the drain of the PMOS transistor P1 are connected to the output pad, and the anode of the second gate control diode D2 is connected to the ground GND.

Further, in the output structure, both the first NMOS transistor N1 and the second NMOS transistor N2 are P-type substrate NMOS transistors, and the P-type substrate NMOS transistor includes a poly gate, an N+ source diffusion region, an N+ drain diffusion region, a P well, Silicon dioxide isolation region, BOX buried oxide layer and silicon substrate, P well is located between N+ source diffusion region and N+ drain diffusion region, BOX buried oxide layer is located on silicon substrate, N+ source diffusion region, N+ drain diffusion region , P well, and silicon dioxide isolation region are located on the BOX buried oxide layer, the poly gate is located on the P well, and the silicon dioxide isolation region surrounds the N+ source diffusion region and the N+ drain diffusion region.

Beneficial effects of the present invention: use ordinary MOS tubes in SOI technology, and use gate-controlled diodes and other ESD protection devices to discharge current when ESD arrives, and the output NMOS tubes are not easy to damage; this structure uses series-connected NMOS tubes to improve the overall withstand voltage of NMOS tubes , to improve the ESD withstand capability of the output.

Description of drawings

Fig. 1 is a circuit diagram of the present invention;

Fig. 2 is used for output port circuit diagram of the present invention;

FIG. 3 is a sectional view of an NMOS device used between an output port and GND according to the present invention.

detailed description

The embodiments listed in the present invention are only used to help understand the present invention, and should not be interpreted as limiting the protection scope of the present invention. For those of ordinary skill in the art, they can also Improvements and modifications are made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

As shown in Figure 1, the output structure with high ESD tolerance based on the PD-SOI process includes the first NMOS transistor N1, the second NMOS transistor N2 and the PMOS transistor P1. When the output structure is used in the output port 3, the first The drain terminal 8 of the NMOS transistor N1 and the drain terminal 7 of the PMOS transistor P1 are connected to the output port 3 through the semiconductor metal aluminum, the source terminal 6 of the PMOS transistor P1 is connected to the power supply 1 through the semiconductor metal aluminum, and the source terminal 9 of the first NMOS transistor N1 The drain terminal 10 of the second NMOS transistor N2 is connected through the semiconductor metal aluminum, the source terminal 11 of the second NMOS transistor N2 is connected to the ground 2 through the semiconductor metal aluminum, the PMOS transistor P1, the first NMOS transistor N1 and the second NMOS transistor N2 The substrates are respectively connected to their source terminals through semiconductor metal aluminum, and the gates 5 of the first NMOS transistor N1 and the second NMOS transistor N2 are connected.

As shown in Figure 2, the output port 3 includes a first gate-control diode D1, a second gate-control diode D2 and an output pad 20, the cathode of the first gate-control diode D1 is connected to the power supply VDD, and the first gate-control diode D1 The anode, the cathode of the second gate control diode D2, the drain 8 of the first NMOS transistor N1, the drain 7 of the PMOS transistor P1 are connected to the output pad 20, and the anode of the second gate control diode D2 is connected to the ground GND. When the second gate control diode D2 is used at the output pad 20 and the ground GND, and the first gate control diode D1 is used at the output pad 20 and the power supply VDD for ESD protection, the drain terminal 8 of the first NMOS transistor N1 passes through the semiconductor The metal aluminum is connected to the output pad 20, the drain 7 of the PMOS transistor P1 is connected to the output pad 20 through the semiconductor metal aluminum, the source end of the first NMOS transistor N1 is also connected to the drain end of the second NMOS transistor N2 through the semiconductor metal aluminum, The source end of the second NMOS transistor N2 is connected to the ground through semiconductor metal aluminum, the gates of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to the front-stage drive circuit 19, and are biased by the front-stage drive circuit 19, and the gate of the PMOS transistor P1 The pole 4 is also connected to the pre-stage drive circuit 19 .

As shown in FIG. 3, the first NMOS transistor N1 and the second NMOS transistor N2 in the output structure are both P-type substrate NMOS transistors, and the P-type substrate NMOS transistor includes a poly gate 18, an N+ source diffusion region 14, an N+ drain Diffusion region 15, P well 16, silicon dioxide isolation region 17, BOX buried oxide layer 13 and silicon substrate 12, P well 16 is located between N+ source diffusion region 14 and N+ drain diffusion region 15, BOX buried oxide layer 13 is located On the silicon substrate 12, the N+ source diffusion region 14, the N+ drain diffusion region 15, the P well 16, and the silicon dioxide isolation region 17 are located on the BOX buried oxide layer 13, and the poly gate 18 is located on the P well 16. Silicon isolation region 17 surrounds N+ source diffusion region 14 and N+ drain diffusion region 15 .

The working principle of the present invention is as follows: First, the voltage of the output voltage pad 20 rises, and the ESD current discharges the current through the first gate-control diode D1. When the breakdown voltage of the second gate-control diode D2 is reached, the second gate-control diode D2 Breakdown, as the ESD current gradually increases, the voltage of the output pad 20 further increases, because the first NMOS transistor N1 and the second NMOS transistor N2 are connected in series, the drain terminal of the first NMOS transistor N1 breaks down to the ground 2 The voltage is twice that of a single NMOS transistor, so as long as the voltage of the output pad 20 is less than twice the breakdown voltage of the NMOS transistor, the output of the first NMOS transistor N1 and the second NMOS transistor N2 will not be broken down and will not be damaged , greatly improving the ESD capability of the output port 3.

Compared with the prior art, the present invention has the advantages of using ordinary NMOS transistors in SOI technology, using gate-controlled diodes and other ESD protection devices to discharge current when ESD comes, and the output NMOS transistors are difficult to break down, so it is not easy to be damaged, and the circuit is improved. Output ESD protection capability; compared with the traditional SOI process output structure, the output structure based on PD-SOI process is simple, easy to popularize, and has a wide range of applications, such as the internal fragile structure between power and ground, mixed voltage compatibility The port can effectively improve the ESD tolerance level of the integrated circuit.

Claims (3)

1. the export structure of high ESD tolerance based on PD-SOI technique, it is characterised in that: described export structure includes first NMOS tube N1, the second NMOS tube N2 and PMOS P1, when described export structure is used in output port (3), the first NMOS tube N1 Drain terminal (8) be connected with output port (3) with the drain terminal (7) of PMOS P1, the source (6) of PMOS P1 is connected with power supply (1), The source (9) of the first NMOS tube N1 is connected with the drain terminal (10) of the second NMOS tube N2, the source (11) of the second NMOS tube N2 and ground (2) being connected, the substrate of PMOS P1, the first NMOS tube N1 and the second NMOS tube N2 is connected with respective source respectively, and first The grid (5) of NMOS tube N1 and the second NMOS tube N2 is connected and all drives (19) inclined by prime with the grid (4) of PMOS P1 Put.

The export structure of high ESD tolerance based on PD-SOI technique the most according to claim 1, it is characterised in that: Described output port (3) includes the first gate control diode D1, the second gate control diode D2 and output pressure welding point (20), the first grid-control The negative pole of diode D1 is connected with power vd D, the positive pole of the first gate control diode D1, the negative pole of the second gate control diode D2, The drain terminal (8) of one NMOS tube N1, the drain terminal (7) of PMOS P1 are connected with output pressure welding point (20), the second gate control diode D2's Positive pole is connected with ground GND.

The export structure of high ESD tolerance based on PD-SOI technique the most according to claim 1, it is characterised in that: In described export structure, the first NMOS tube N1 and the second NMOS tube N2 are P type substrate NMOS tube, and this P type substrate NMOS tube includes Poly grid (18), diffusion region, N+ source (14), N+ leakage diffusion region (15), p-well (16), silicon dioxide isolation area (17), BOX bury oxidation Layer (13) and silicon substrate (12), p-well (16) is positioned between diffusion region, N+ source (14) and N+ leakage diffusion region (15), and BOX buries oxide layer (13) it is positioned on silicon substrate (12), diffusion region, N+ source (14), N+ leakage diffusion region (15), p-well (16), silicon dioxide isolation area (17) being positioned at BOX and bury on oxide layer (13), poly grid (18) are positioned on p-well (16), and silicon dioxide isolation area (17) surround N Diffusion region ,+source (14) and N+ leakage diffusion region (15).